CN211606648U

CN211606648U - BY PASS circuit

Info

Publication number: CN211606648U
Application number: CN202020592765.XU
Authority: CN
Inventors: 宣振生
Original assignee: Beijing Jiagu Jinsheng Technology Co ltd
Current assignee: Beijing Jiagu Jinsheng Technology Co ltd
Priority date: 2020-04-20
Filing date: 2020-04-20
Publication date: 2020-09-29
Anticipated expiration: 2030-04-20

Abstract

The application discloses BY PASS circuit relates to the circuit field. The BY PASS circuit is applied to a video and audio program processing device, is respectively connected with a main control chip, an HDMI IN interface and an HDMI OUT interface of the device, and is configured into: IN a first working mode, when the device enters a working state, the HDMI IN interface, the main control chip and the HDMI OUT interface are controlled to be conducted, so that video and audio programs input by the HDMI IN interface are transmitted to the HDMI OUT interface for output after being processed by the main control chip; IN the second working mode, when the device enters a standby state, the HDMI IN interface and the HDMI OUT interface are controlled to be directly connected, so that video and audio programs input by the HDMI IN interface are directly transmitted to the HDMI OUT interface to be output. The method and the device can also normally watch the video and audio programs without rewiring or resetting, facilitate the watching requirements of various users and are very convenient.

Description

BY PASS circuit

Technical Field

The application relates to the field of circuits, in particular to a BY PASS circuit.

Background

In the digital cable television era, the cable television adopts a mode of a television and an external set top box to realize playing. In various types of video and audio programs, the video and audio programs such as news and live sports events have no subtitles, and in such a case, the deaf people cannot accurately know the content of the video and audio programs. Therefore, it is necessary to process the video and audio programs and convert the speech into text for the hearing impaired to watch.

Generally, a device for converting voice into text needs to be connected between a television and a set-top box, and a video and audio program received by the set-top box is processed by the device and then transmitted to a television screen for display. However, this method obviously has a disadvantage that for a viewer who does not need to convert the voice into text, if the device is not opened, the television cannot normally display the video and audio programs, which causes inconvenience for use.

SUMMERY OF THE UTILITY MODEL

It is an object of the present application to overcome the above problems or to at least partially solve or mitigate the above problems.

The application provides a BY PASS circuit, be applied to audio and video program processing apparatus, the device includes: the circuit is respectively connected with the main control chip, the HDMI IN interface and the HDMI OUT interface and is configured to provide two working modes;

IN a first working mode, when the device enters a working state, the HDMI IN interface, the main control chip and the HDMI OUT interface are controlled to be conducted, so that video and audio programs input by the HDMI IN interface are transmitted to the HDMI OUT interface for output after being processed by the main control chip;

and IN a second working mode, when the device enters a standby state, the HDMI IN interface and the HDMIOUT interface are controlled to be directly connected, so that video and audio programs input by the HDMI IN interface are directly transmitted to the HDMI OUT interface for output.

Optionally, the circuit comprises a first multiplexer and a second multiplexer;

the first multiplexer is provided with a first channel, a second channel and a data channel, the first channel is connected with the second multiplexer, the second channel is connected with the main control chip, and the data channel is connected with the HDMI IN interface;

the first multiplexer is configured to: in a first working mode, when the device enters a working state, controlling to conduct the second channel and the data channel; in a second working mode, when the device enters a standby state, controlling to conduct the first channel and the data channel;

the second multiplexer is provided with a first channel, a second channel and a data channel, the first channel is connected with the main control chip, the second channel is connected with the first multiplexer, and the data channel is connected with the HDMI OUT interface;

the second multiplexer is configured to: under a first working mode, when the device enters a working state, controlling to conduct the first channel and the data channel; and under a second working mode, when the device enters a standby state, controlling to conduct the second channel and the data channel.

Optionally, the first multiplexer has a pin SEL2 configured to be set to a high level by software when the device enters an operating state in a first operating mode and to be set to a low level by an external pull-down when the device enters a standby state in a second operating mode.

Optionally, the first multiplexer has:

a first set of pins D0+, D0-, D1+, D1-, D2+, D2-, D3+, D3-, HPD, CEC, SCL and SDA, corresponding to HDMI data lines and control lines of the data channel;

a second set of pins D0A +, D0A-, D1A +, D1A-, D2A +, D2A-, D3A +, D3A-, HPD _ a, CEC _ a, SCL _ a and SDA _ a, corresponding to the HDMI data and control lines of the first channel;

a third group of pins D0B +, D0B-, D1B +, D1B-, D2B +, D2B-, D3B +, D3B-, HPD _ B, CEC _ B, SCL _ B and SDA _ B, corresponding to the HDMI data and control lines of the second channel;

the concrete configuration is as follows:

in a first working mode, when the device enters a working state, controlling and conducting pins D0+ and D0B +, pins D0-and D0B-, pins D1+ and D1B +, pins D1-and D1B-, pins D2+ and D2B +, pins D2-and D2B-, pins D3+ and D3B +, pins D3-and D3B-, pins HPD and HPD _ B, pins CEC and CEC _ B, pins SCL and SCL _ B, and pins SDA and SDA _ B;

in the second operation mode, when the device enters the standby state, the control turns on pins D0+ and D0A +, pins D0-and D0A-, pins D1+ and D1A +, pins D1-and D1A-, pins D2+ and D2A +, pins D2-and D2A-, pins D3+ and D3A +, pins D3-and D3A-, pins HPD and HPD _ A, pins CEC and CEC _ A, pins SCL and SCL _ A, and pins SDA and SDA _ A.

Optionally, the second multiplexer has a pin SEL2 configured to be set to a low level by software when the device enters an operational state in a first mode of operation and to be set to a high level by an external pull-up when the device enters a standby state in a second mode of operation.

Optionally, the second multiplexer has:

the concrete configuration is as follows:

in a first working mode, when the device enters a working state, controlling and conducting pins D0+ and D0A +, pins D0-and D0A-, pins D1+ and D1A +, pins D1-and D1A-, pins D2+ and D2A +, pins D2-and D2A-, pins D3+ and D3A +, pins D3-and D3A-, pins HPD and HPD _ A, pins CEC and CEC _ A, pins SCL and SCL _ A, and pins SDA and SDA _ A;

in the second operation mode, when the device enters the standby state, the control turns on pins D0+ and D0B +, pins D0-and D0B-, pins D1+ and D1B +, pins D1-and D1B-, pins D2+ and D2B +, pins D2-and D2B-, pins D3+ and D3B +, pins D3-and D3B-, pins HPD and HPD _ B, pins CEC and CEC _ B, pins SCL and SCL _ B, and pins SDA and SDA _ B.

Optionally, the first and second multiplexers are each 12-channel 1:2 multiplexers.

Optionally, the first and second multiplexers each have a 1.8v compatible control and power down mode.

The technical scheme that this application provided, through two kinds of mode, both guaranteed audio and video program processing apparatus when operating condition, audio and video program export after main control chip handles, also guaranteed the device when standby state, HDMIIN interface and HDMI OUT interface through connection, direct output audio and video program to need not to reconnect or reset and also can normally watch audio and video program, made things convenient for all kinds of users' watching demand, it is convenient to bring for the user.

The above and other objects, advantages and features of the present application will become more apparent to those skilled in the art from the following detailed description of specific embodiments thereof, taken in conjunction with the accompanying drawings.

Drawings

Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:

FIG. 1 is a diagram illustrating a BY PASS circuit application scenario according to an embodiment of the present application;

FIG. 2 is a block diagram of a BY PASS circuit according to another embodiment of the present application;

FIG. 3 is a block diagram of a first multiplexer according to another embodiment of the present application;

FIG. 4 is a block diagram of a second multiplexer according to another embodiment of the present application;

FIG. 5 is a schematic diagram of the control of data lines in a multiplexer according to another embodiment of the present application;

FIG. 6 is a schematic diagram of an HDMI IN interface according to another embodiment of the present application;

fig. 7 is a schematic diagram of an HDMI OUT interface according to another embodiment of the present application.

Detailed Description

The application relates to a BY PASS circuit and a video and audio program processing device thereof. Wherein the apparatus involves processing speech of a video-audio program, converting the speech to text and then outputting. The device can also generate corresponding subtitles from the converted text, add the subtitles to the picture of the video and audio program and output the subtitles, and the specific process is not explained in the application.

Fig. 1 is a schematic diagram of a BY PASS circuit application scenario according to an embodiment of the present application. Referring to fig. 1, the BYPASS circuit 11 is applied to a video/audio program processing apparatus S0, which includes: the circuit comprises a main control chip 12, an HDMI IN interface 13 and an HDMI OUT interface 14, wherein the circuit is respectively connected with the main control chip, the HDMI IN interface and the HDMI OUT interface and is configured to provide two working modes;

and IN the second working mode, when the device enters a standby state, the HDMI IN interface and the HDMI OUT interface are controlled to be directly connected, so that video and audio programs input by the HDMI IN interface are directly transmitted to the HDMI OUT interface for output.

Fig. 2 is a block diagram of a BY PASS circuit according to another embodiment of the present application. Referring to fig. 2, the BY PASS circuit includes a first multiplexer 21 and a second multiplexer 22, and is applied to an audio/video program processing apparatus including: a main control chip 23, an HDMI IN interface 24, and an HDMI OUT interface 25.

A first multiplexer 21 having a first channel a, a second channel B and a data channel DQ, wherein the first channel a is connected to the second multiplexer 22, the second channel B is connected to the main control chip 23, and the data channel DQ is connected to the HDMI IN interface 24;

the first multiplexer 21 is configured to: in a first working mode, when the device enters a working state, the second channel B and the data channel DQ are controlled to be conducted; in a second working mode, when the device enters a standby state, the first channel A and the data channel DQ are controlled to be conducted;

the second multiplexer 22 is provided with a first channel A, a second channel B and a data channel DQ, wherein the first channel A is connected with the main control chip 23, the second channel B is connected with the first multiplexer 21, and the data channel DQ is connected with the HDMI OUT interface 25;

the second multiplexer 22 is configured to: in a first working mode, when the device enters a working state, the first channel A and the data channel DQ are controlled to be conducted; in the second operation mode, when the apparatus enters the standby state, the second channel B and the data channel DQ are controlled to be conducted.

In this embodiment, optionally, the first multiplexer has a pin SEL2 configured to be set to a high level by software when the device enters an operating state in the first operating mode and to be set to a low level by an external pull-down when the device enters a standby state in the second operating mode.

In this embodiment, optionally, the second multiplexer has a pin SEL2 configured to be set to a low level by software when the device enters an operating state in the first operating mode and to be set to a high level by an external pull-up when the device enters a standby state in the second operating mode.

Fig. 3 is a block diagram of a first multiplexer according to another embodiment of the present application, and fig. 4 is a block diagram of a second multiplexer according to another embodiment of the present application. The control principle of the first multiplexer and the second multiplexer is explained in detail in conjunction with fig. 3 and 4.

First, the first multiplexer has:

the first group of pins D0+, D0-, D1+, D1-, D2+, D2-, D3+, D3-, HPD, CEC, SCL and SDA, corresponding to the HDMI data lines and control lines of the data channel;

the second group of pins D0A +, D0A-, D1A +, D1A-, D2A +, D2A-, D3A +, D3A-, HPD _ A, CEC _ A, SCL _ A and SDA _ A, corresponding to the HDMI data line and control line of the first channel;

the third group of pins D0B +, D0B-, D1B +, D1B-, D2B +, D2B-, D3B +, D3B-, HPD _ B, CEC _ B, SCL _ B and SDA _ B, corresponding to the HDMI data and control lines of the second channel;

the specific configuration of the first multiplexer is as follows:

in the first working mode, when the device enters the working state, the device is controlled to be switched on pins D0+ and D0B +, pins D0-and D0B-, pins D1+ and D1B +, pins D1-and D1B-, pins D2+ and D2B +, pins D2-and D2B-, pins D3+ and D3B +, pins D3-and D3B-, pins HPD and HPD _ B, pins CEC and CEC _ B, pins SCL and SCL _ B, and pins SDA and SDA _ B;

in the second operation mode, when the device enters the standby state, the control turns on the pins D0+ and D0A +, the pins D0-and D0A-, the pins D1+ and D1A +, the pins D1-and D1A-, the pins D2+ and D2A +, the pins D2-and D2A-, the pins D3+ and D3A +, the pins D3-and D3A-, the pins HPD and HPD _ A, the pins CEC and CEC _ A, the pins SCL and SCL _ A, and the pins SDA and SDA _ A.

Next, the second multiplexer has:

the specific configuration of the second multiplexer is as follows:

in the first working mode, when the device enters the working state, the control switches on the pins D0+ and D0A +, the pins D0-and D0A-, the pins D1+ and D1A +, the pins D1-and D1A-, the pins D2+ and D2A +, the pins D2-and D2A-, the pins D3+ and D3A +, the pins D3-and D3A-, the pins HPD and HPD _ A, the pins CEC and CEC _ A, the pins SCL and SCL _ A, and the pins SDA and SDA _ A;

in the second operation mode, when the device enters the standby state, the control turns on the pins D0+ and D0B +, the pins D0-and D0B-, the pins D1+ and D1B +, the pins D1-and D1B-, the pins D2+ and D2B +, the pins D2-and D2B-, the pins D3+ and D3B +, the pins D3-and D3B-, the pins HPD and HPD _ B, the pins CEC and CEC _ B, the pins SCL and SCL _ B, and the pins SDA and SDA _ B.

Referring to fig. 3 and 4, U14 is a first multiplexer and U13 is a second multiplexer. The two multiplexers may be specifically configured as follows. Under the first working mode, when the video and audio program processing device enters the working state, the first multiplexer U14 controls to conduct the second channel and the data channel by setting the pin SEL2 to be high level (for example, 3.3v) through software; in the second operation mode, when the device enters the standby state, the external pull-down setting pin SEL2 is set to low (e.g. 0v) to control the conduction between the first channel and the data channel. Under the first working mode, when the device enters a working state, the second multiplexer U13 controls to conduct the first channel and the data channel by setting a pin SEL2 to be low level through software; in the second operation mode, when the device enters the standby state, the external pull-up setting pin SEL2 is set to high level to control the conduction of the second channel and the data channel.

In this embodiment, optionally, the first multiplexer and the second multiplexer are both 12-channel 1:2 multiplexers. Further, optionally, the first multiplexer and the second multiplexer each have a 1.8v compatible control and power down mode.

FIG. 5 is a control schematic of data lines in a multiplexer according to another embodiment of the present application. Referring to fig. 5, wherein the first set of pins D0+, D0-, D1+, D1-, D2+, D2-, D3+ and D3-within the multiplexer correspond to HDMI data lines of a data channel, the second set of pins D0A +, D0A-, D1A +, D1A-, D2A +, D2A-, D3A + and D3A-correspond to HDMI data lines of the first channel, and the third set of pins D0B +, D0B-, D1B +, D1B-, D2B +, D2B-, D3B + and D3B-correspond to HDMI data lines of the second channel. Specifically, the first group of pins and the second group of pins can be controlled to be conducted in a one-to-one correspondence manner, so that the first channel and the data channel are conducted; the first group of pins and the third group of pins can be controlled to be conducted in a one-to-one correspondence mode, and therefore the second channel and the data channel are conducted.

Fig. 6 is a schematic diagram of an HDMI IN interface structure according to another embodiment of the present application. Fig. 7 is a schematic diagram of an HDMI OUT interface according to another embodiment of the present application. The HDMI IN interface is used for receiving video and audio programs, and is connected to the first multiplexer through each pin as shown IN fig. 6, so as to transmit the video and audio programs to the first multiplexer. The HDMI OUT interface is used for outputting video and audio programs, and is connected to the second multiplexer through each pin shown in fig. 7, so that the video and audio programs are received from the second multiplexer and then transmitted, and the specific process is not described herein.

The above-mentioned BY PASS circuit that this embodiment provided, through two kinds of mode, both guaranteed that audio and video program processing apparatus is when operating condition, audio and video program exports after main control chip handles, also guaranteed that the device is when standby state, HDMI IN interface and HDMI OUT interface through connection, direct output audio and video program to need not to reconnect or reset and also can normally watch audio and video program, made things convenient for the demand of watching of all kinds of users, it is convenient to bring for the user.

The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A BY PASS circuit for use in a video and audio program processing apparatus, the apparatus comprising: the circuit is respectively connected with the main control chip, the HDMIIN interface and the HDMI OUT interface and is configured to provide two working modes;

in a first working mode, when the device enters a working state, the HDMIIN interface, the main control chip and the HDMI OUT interface are controlled to be conducted, so that video and audio programs input by the HDMIIN interface are transmitted to the HDMI OUT interface for output after being processed by the main control chip;

and in a second working mode, when the device enters a standby state, the HDMIIN interface and the HDMI OUT interface are controlled to be directly connected, so that video and audio programs input by the HDMIIN interface are directly transmitted to the HDMI OUT interface to be output.

2. The circuit of claim 1, wherein the circuit comprises a first multiplexer and a second multiplexer;

the first multiplexer is provided with a first channel, a second channel and a data channel, the first channel is connected with the second multiplexer, the second channel is connected with the main control chip, and the data channel is connected with the HDMIIN interface;

3. The circuit of claim 2, wherein the first multiplexer has a pin SEL2 configured to be set to a high level by software when the device enters an operating state in a first operating mode and to be set to a low level by an external pull down when the device enters a standby state in a second operating mode.

4. The circuit of claim 2, wherein the first multiplexer has:

the concrete configuration is as follows:

5. The circuit of claim 2, wherein the second multiplexer has a pin SEL2 configured to be set to a low level by software when the device enters an operating state in a first operating mode and to be set to a high level by an external pull-up when the device enters a standby state in a second operating mode.

6. The circuit of claim 2, wherein the second multiplexer has:

the concrete configuration is as follows:

7. The circuit of claim 2, wherein the first and second multiplexers are each 12-channel 1:2 multiplexers.

8. The circuit of claim 2, wherein the first and second multiplexers each have a 1.8v compatible control and power down mode.