CN211604098U - Circuit for realizing IAP program upgrading based on single chip microcomputer ISP - Google Patents
Circuit for realizing IAP program upgrading based on single chip microcomputer ISP Download PDFInfo
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- CN211604098U CN211604098U CN202020516726.1U CN202020516726U CN211604098U CN 211604098 U CN211604098 U CN 211604098U CN 202020516726 U CN202020516726 U CN 202020516726U CN 211604098 U CN211604098 U CN 211604098U
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Abstract
The utility model relates to a circuit based on singlechip ISP realizes IAP procedure upgrading, it has solved the not enough problem of current IAP procedure upgrading mode, it is equipped with the singlechip, ISP transient state enabling circuit and regularly long reset circuit, the singlechip respectively with ISP transient state enabling circuit with regularly long reset circuit connection, the inside FLASH district that is equipped with of singlechip, FLASH district deposits the firmware program, ISP transient state enabling circuit drive singlechip restarts gets into the ISP state, upgrade FLASH district firmware program, regularly long reset circuit hardware resets the singlechip, normally operate FLASH district firmware program. The utility model discloses can extensively be in order to possess the singlechip IAP program upgrading of level control ISP pin.
Description
Technical Field
The utility model relates to an embedded equipment program upgrading technical field especially relates to a circuit based on singlechip ISP realizes IAP program upgrading.
Background
The embedded equipment single chip program upgrading commonly uses ISP and IAP two modes. The ISP (In system programming) is a mode provided by a single chip microcomputer manufacturer, and by some auxiliary means, the single chip microcomputer is not started from a normal internal FLASH area when being started, but enters an internal solidified ISP upgrading program, receives data from a serial port, an SPI or an I2C, and completes program updating and writing of the whole FLASH area. IAP (In-application programming) is a program upgrading mode implemented by a single chip microcomputer developer, and when the developer writes a program, the developer divides a FLASH area inside the single chip microcomputer into a BOOT area and an APP area, and respectively stores an upgrading program and an application program. When the single chip microcomputer operates, the single chip microcomputer firstly enters a BOOT area to operate an upgrading program, if the upgrading is not needed, the single chip microcomputer jumps to an APP area to execute the application program, otherwise, the program upgrading process is started, and the APP area application program is rewritten.
The features and problems of the ISP and IAP approaches are as follows:
1. the ISP upgrading program is a program solidified in a specific address in the singlechip when the singlechip manufacturer leaves a factory, an internal FLASH area provided by the singlechip for a user is not required to be occupied, and extra storage space is not required to be consumed, but the ISP function is provided by the singlechip manufacturer, needs to be controlled by an auxiliary circuit means, is commonly used for downloading programs in the research and development and production processes of the manufacturer, and cannot be used after equipment leaves the factory.
2. The IAP mode is flexible, no additional auxiliary means is needed, the upgrading process can be completed through a standard serial interface or even a remote network, the method is often used for upgrading programs after leaving a factory, an additional storage space is occupied, storage resources in low-end equipment are limited, the support of the jump function of part of single-chip microcomputers is incomplete, and the realization of two-stage programs of BOOT and APP is complex.
Disclosure of Invention
The utility model discloses a solve prior art not enough, provide a circuit based on singlechip ISP realizes IAP program upgrading, carry out hardware circuit and software function extension on singlechip ISP function basis, the singlechip resets the back and gets into the ISP state automatically, and the host computer utilizes ISP upgrading agreement to realize program upgrading like the IAP function, has saved the FLASH resource of singlechip, reduces BOOT, the development degree of difficulty of APP two-stage program, is applicable to the singlechip that possesses level control ISP pin.
The utility model provides a circuit based on singlechip ISP realizes IAP procedure upgrading, be equipped with the singlechip, ISP transient state enable circuit and regularly long reset circuit, the singlechip respectively with ISP transient state enable circuit with regularly long reset circuit connection, the inside FLASH district that is equipped with of singlechip, the firmware program is deposited in the FLASH district, ISP transient state enable circuit drive singlechip restarts gets into the ISP state, upgrading FLASH district firmware program, regularly long reset circuit hardware resets the singlechip, normally operate FLASH district firmware program.
Preferably, the single chip microcomputer is provided with an ISP pin, a RESET RESET pin, a serial port communication pin and a general IO pin, the general IO pin is provided with a GPIO1 pin and a GPIO2 pin, the general IO pin is respectively connected with the ISP transient enabling circuit and the timing length RESET circuit, the GPIO1 pin and the GPIO2 pin are respectively used for being connected with the ISP transient enabling circuit and the timing length RESET circuit, a program upgrading instruction drives the single chip microcomputer through the GPIO1 pin, and firmware programs are downloaded from the communication serial port by running the ISP program solidified in the single chip microcomputer.
Preferably, the high level state of the ISP pin enables the single chip to enter the ISP enabling function, and the level adaptation circuit is directly connected to the ISP pin.
Preferably, the low level state of the ISP pin enables the single chip to enter the ISP enabling function, and an inverter is added to the level adaptation circuit to connect to the ISP pin.
Preferably, the ISP transient enabling circuit comprises a capacitor C1, a resistor R1 and an ISP level adaptation circuit, the capacitor C1 is a uF class energy storage capacitor, and the capacitor C1 can hold a level threshold of more than 10 milliseconds.
Preferably, the timing long reset circuit comprises a watchdog U2TPL5010 and a reset time setting resistor R2; the single chip microcomputer ISP serial port is interconnected and communicated with external equipment, and after the single chip microcomputer enters the ISP state, an ISP serial port upgrading protocol is used for upgrading the program.
The utility model has the advantages that:
(1) because the utility model discloses the upgrading interface is completely through host computer software program control, and the operation mode is the same completely with IAP upgrading process, and the user perception can not arrive complicated ISP control mode, simple easy operation.
(2) Because the utility model discloses upgrading based on the ISP program that the singlechip was dispatched from the factory, the user need not develop the BOOT program alone, has reduced the development degree of difficulty of FLASH resource consumption and BOOT program greatly.
(3) Because the utility model discloses ISP serial ports based on the singlechip, local upgrading such as RS232, RS485 or long-range upgrading such as ethernet, GPRS can be convenient expand, the suitability is stronger.
The utility model provides a circuit based on singlechip ISP realizes IAP program upgrading possesses the function that hardware realizes ISP enables and resets and restart completely automatically, and the user need not know ISP control mode, and is the same completely with ordinary IAP upgrading process, and simple easy operation need not develop BOOT program simultaneously, has reduced FLASH resource consumption and the development degree of difficulty of BOOT program greatly, has stronger suitability.
Drawings
Fig. 1 is a schematic structural diagram of the present invention.
Description of the symbols of the drawings:
an ISP transient enable circuit; ISP level adaptation circuitry; 2. a single chip microcomputer; 21. a communication serial port pin; 3. a timing length reset circuit.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples, so that those skilled in the art can easily implement the present invention.
Example 1: as shown in fig. 1, the utility model is provided with a hardware circuit comprising a single chip microcomputer 2, an ISP transient state enabling circuit 1 and a timing length resetting circuit 3, wherein the single chip microcomputer 2 is provided with an ISP pin, a RESET resetting pin and 2 general IO pins which are GPIO1 and GPIO2 peripheral circuit control pins and a communication serial port pin 21, and the communication serial port pin 21 comprises TX and RX serial port communication pins; the ISP transient enabling circuit 1 comprises a capacitor C1, a resistor R1 and an ISP level adaptation circuit 11; the fixed-duration reset circuit 3 includes a watchdog U2 and a reset-time setting resistor R2. The 2 general IO pins GPIO1 and GPIO2 are respectively used for connecting a watchdog timer feed in an ISP transient enabling and timing length resetting circuit.
The single chip microcomputer 2 has a function of entering ISP enabling through a high level or low level state of a special ISP pin when being powered on and started, when the ISP high level is enabled, the ISP level adapting circuit 11 does not need a device and is directly connected, and when the ISP low level is enabled, an inverter is added in the ISP level adapting circuit 11. The energy storage capacitor C1 in the ISP transient enabling circuit 1 is a uF-level capacitor, can keep a level threshold value of more than 10 milliseconds, ensures that an ISP pin can enter an ISP state after the single chip microcomputer 2 is reset, and ensures that the ISP pin is quickly recovered to a forbidden state after the single chip microcomputer is started because the discharge resistor R1 and the C1 are connected in series to form a discharge loop. When the application program of the singlechip 2 runs, the singlechip 2 feeds dogs regularly through the GPIO2 pin, if a dog feeding signal is not received after the U2 is overtime, the singlechip 2 is RESET through the RESET pin, the time interval set by the chip is confirmed by the resistance value of the resistor R2, and the value is larger than the dog feeding time interval in the singlechip 2 and the time required by upgrading the singlechip ISP.
The software programs of the singlechip 2 comprise a serial port instruction processing program, an ISP enabling control program and a reset program. When the equipment normally runs, the upper computer issues a program upgrading instruction through the serial port, the ISP enabling control program sets the GPIO1 pin to output high level, the capacitor C1 is charged for at least 1 second, the reset program software resets the single chip microcomputer 2 after the level is stable, the ISP pin is kept in an enabling state due to the charging of the capacitor C1 at the resetting moment, and the single chip microcomputer 2 enters the ISP state. The ISP serial port of the single chip microcomputer 2 which leaves the factory is designed to be interconnected and communicated with external equipment, and after the single chip microcomputer 2 enters an ISP state, the upper computer uses the ISP serial port upgrading protocol to upgrade a program. After the ISP program is upgraded, the single chip microcomputer 2 is still in an ISP state, the single chip microcomputer 2 is reset until the watchdog in the timing length reset circuit is overtime, and the single chip microcomputer 2 is in a normal operation state after being restarted.
The serial port of the singlechip 2 intercommunicated with the external equipment is an ISP (internet service provider) functional serial port instead of a common serial port, the serial port can directly output TTL (transistor-transistor logic) level outwards, the upper computer can upgrade the program through the TTL serial port and also can realize wired modes such as RS232, RS485 and M-Bus or wireless modes such as infrared and the like, the upper computer still upgrades the program according to an ISP serial port protocol, and the upper computer can also remotely upgrade the program through Ethernet and GPRS (general packet radio service).
The watchdog circuit is reset over time, a TPL5010 low-power consumption watchdog chip capable of setting reset time is selected in the watchdog circuit, sufficient upgrade time for an ISP is guaranteed, after upgrade is completed, normal operation program state is entered again through RSET pin reset equipment, normal operation in the program is realized by sending high-level pulse with the width of 1us to a DOG pin of the TPL5010 at regular time, and the DOG feeding function is realized.
Example 2: the method for realizing the IAP program upgrading based on the single chip microcomputer ISP comprises the following steps:
And 3, after the upgrading is finished, the ISP pin is restored to a forbidden state, the timing reset circuit resets the single chip microcomputer 2 through hardware, the application program is started to run normally, after the upgrading of the ISP program is finished, the single chip microcomputer 2 is still in the ISP state, the single chip microcomputer 2 is reset until the watchdog in the timing reset circuit is overtime, and the single chip microcomputer 2 is in the normal running state after being restarted.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the present invention, as various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the scope defined by the claims of the present invention shall be within the protection scope of the present invention.
Claims (6)
1. A circuit for realizing IAP program upgrading based on a single chip microcomputer ISP is characterized by being provided with a single chip microcomputer, an ISP transient state enabling circuit and a timing length resetting circuit, wherein the single chip microcomputer is respectively connected with the ISP transient state enabling circuit and the timing length resetting circuit, a FLASH area is arranged in the single chip microcomputer and stores firmware programs, the ISP transient state enabling circuit drives the single chip microcomputer to restart to enter an ISP state to upgrade the firmware programs of the FLASH area, and the timing length resetting circuit resets the single chip microcomputer through hardware and normally runs the firmware programs of the FLASH area.
2. The circuit for realizing IAP program upgrading based on the single chip microcomputer ISP is characterized in that the single chip microcomputer is provided with an ISP pin, a RESET RESET pin, a serial port communication pin and a general IO pin, the general IO pin is provided with a GPIO1 pin and a GPIO2 pin, the general IO pin is respectively connected with the ISP transient enabling circuit and the timing length RESET circuit, the GPIO1 pin and the GPIO2 pin are respectively used for connecting the ISP transient enabling circuit and the timing length RESET circuit, the ISP transient enabling circuit is provided with an ISP level adapting circuit, a program upgrading instruction drives the single chip microcomputer through the GPIO1 pin, and an ISP program solidified in the single chip microcomputer is operated to download a firmware program from a communication serial port.
3. The circuit for realizing upgrading of an IAP program based on the ISP of the single chip microcomputer as claimed in claim 2, wherein the high level state of the ISP pin enables the single chip microcomputer to enter an ISP enabling function, and the ISP level adapting circuit is directly connected with the ISP pin.
4. The circuit for realizing the upgrading of the IAP program based on the ISP of the single chip microcomputer as claimed in claim 2, wherein the low level state of the ISP pin enables the single chip microcomputer to enter an ISP enabling function, and an inverter is added in the ISP level adapting circuit to be connected with the ISP pin.
5. The circuit for realizing IAP program upgrade based on the single chip microcomputer ISP (internet service provider) as claimed in claim 1, wherein the ISP transient enabling circuit comprises a capacitor C1, the capacitor C1 is a uF-class energy storage capacitor, and the capacitor C1 can keep a level threshold value of more than 10 milliseconds.
6. The circuit for realizing IAP program upgrading based on the single chip microcomputer ISP (Internet service provider) as claimed in claim 1, wherein the fixed-time-length resetting circuit comprises a watchdog U2TPL5010 and a resetting time setting resistor R2; the single chip microcomputer ISP serial port and the external equipment are interconnected and intercommunicated through a serial port upgrading protocol, and the single chip microcomputer uses the ISP serial port upgrading protocol to upgrade a program after entering an ISP state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020516726.1U CN211604098U (en) | 2020-04-10 | 2020-04-10 | Circuit for realizing IAP program upgrading based on single chip microcomputer ISP |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020516726.1U CN211604098U (en) | 2020-04-10 | 2020-04-10 | Circuit for realizing IAP program upgrading based on single chip microcomputer ISP |
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| CN211604098U true CN211604098U (en) | 2020-09-29 |
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| CN202020516726.1U Expired - Fee Related CN211604098U (en) | 2020-04-10 | 2020-04-10 | Circuit for realizing IAP program upgrading based on single chip microcomputer ISP |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111273938A (en) * | 2020-04-10 | 2020-06-12 | 威海市天罡仪表股份有限公司 | Circuit and method for realizing IAP program upgrading based on single chip microcomputer ISP |
| CN113311931A (en) * | 2021-06-08 | 2021-08-27 | 合肥磐芯电子有限公司 | Double-reset vector 8-bit MCU (microprogrammed control Unit) architecture convenient for IAP (inter Access Point) and method thereof |
-
2020
- 2020-04-10 CN CN202020516726.1U patent/CN211604098U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111273938A (en) * | 2020-04-10 | 2020-06-12 | 威海市天罡仪表股份有限公司 | Circuit and method for realizing IAP program upgrading based on single chip microcomputer ISP |
| CN113311931A (en) * | 2021-06-08 | 2021-08-27 | 合肥磐芯电子有限公司 | Double-reset vector 8-bit MCU (microprogrammed control Unit) architecture convenient for IAP (inter Access Point) and method thereof |
| CN113311931B (en) * | 2021-06-08 | 2022-12-13 | 合肥磐芯电子有限公司 | Double-reset vector 8-bit MCU (microprogrammed control Unit) architecture convenient for IAP (inter Access Point) and method thereof |
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Granted publication date: 20200929 |