CN211529955U - III-V semiconductor device - Google Patents

Abstract

A III-V semiconductor device comprises a substrate, an epitaxial layer arranged on the substrate, and a plurality of contact regions arranged on the epitaxial layer. The epitaxial layer comprises a plurality of channels, the channels extend from the epitaxial layer to part of the substrate and expose the surface of the substrate, an active region is arranged between every two channels, and the active region at least comprises two contact regions. The III-V semiconductor device can rapidly verify the characteristics of III-V epitaxy with the minimum cost and the minimum process manufacturing time.

Description

III-V semiconductor device

Technical Field

The present invention relates to a semiconductor device, and more particularly to a semiconductor device manufactured by a laser cutting technique.

Background

Group iii-v semiconductor devices, such as gallium nitride, are currently one of the trends in future Radio Frequency (RF) and high power (highpower) devices. However, the fabrication process of the iii-v semiconductor device is very complicated, and takes about three days, and several tens of process steps are required to fabricate an active region (mesa) and a contact region (metal contact) to measure the hall effect (hall effect) so as to verify the electron concentration (electron concentration), the electron mobility (electron mobility) or the breakdown Voltage (VBD) of the epitaxial layer, thereby verifying the breakdown voltage capability of the epitaxial layer.

Referring to fig. 1A to fig. 1G, fig. 1A to fig. 1G are flowcharts illustrating steps of forming a iii-v semiconductor device in the prior art. As shown in fig. 1A, a substrate 10 is provided, and the material of the substrate 10 is silicon, sapphire, or silicon carbide. Next, as shown in fig. 1B, a iii-v epitaxial layer 20 is formed on the substrate 10 by using a general epitaxial technique. Next, as shown in fig. 1C, a photoresist 11 is coated on the iii-v epitaxial layer 20, and the photoresist 11 is exposed to light and hardened. Next, as shown in fig. 1D, an etching step is performed on the iii-v epitaxial layer 20 by using the hardened photoresist 11 as a mask, and a channel 40 is etched in the iii-v epitaxial layer 20, wherein the channel 40 extends to the substrate 10 and exposes a portion of the surface of the substrate 10. The photoresist 11 is then removed. Then, as shown in fig. 1E, the iii-v epitaxial layer 20 is covered with the evaporation mask 12, and the evaporation mask 12 is first patterned to form the contact region 30. Next, as shown in fig. 1F, a metal plating film is formed through the vapor deposition mask 12, and a metal layer 30 is sputtered on the group iii-group v epitaxial layer 20. Next, as shown in fig. 1G, the vapor deposition mask 12 is removed, and the contact region 30 is formed at a predetermined position on the group iii-v epitaxial layer 20.

As can be seen from the above, the manufacturing steps of the iii-v semiconductor device in the prior art require complicated photolithography and etching processes, which are time and labor consuming, and therefore, simple process steps are needed to reduce the manufacturing time and the manufacturing cost.

SUMMERY OF THE UTILITY MODEL

In order to improve the deficiency of the prior art, the present invention is directed to a simple process for fabricating iii-v semiconductor devices to reduce the complicated etching process and photolithography process and reduce the fabrication time.

To achieve the above object, the present invention discloses a iii-v semiconductor device, which includes a substrate, an epitaxial layer disposed on the substrate, and a plurality of contact regions disposed on the epitaxial layer. The epitaxial layer comprises a plurality of channels, the channels extend from the epitaxial layer to part of the substrate and expose the surface of the substrate, an active region is arranged between every two channels, and the active region at least comprises two contact regions.

The utility model has the advantages of, be applied to and belong to pure ripe technique and the originally numerous and complicated three five semiconductor process technologies of technology step, can be with minimum cost and shortest technology preparation time, the measurement of direct leading-in hall effect reaches the purpose of verifying three five epitaxial characteristics fast.

Drawings

Fig. 1A to 1G are flowcharts illustrating steps in forming a iii-v semiconductor device according to the prior art.

Fig. 2 is a schematic cross-sectional diagram illustrating a iii-v semiconductor device, in accordance with the techniques of the present invention.

Fig. 3A-3E are schematic cross-sectional views illustrating the formation of active regions and contact regions in a iii-v semiconductor device, according to the present technology.

Detailed Description

In order to make the objects, technical features and advantages of the present invention more comprehensible to those skilled in the relevant art and to enable implementation of the present invention, accompanying drawings are provided herein to illustrate the technical features and embodiments of the present invention, and preferred embodiments are described below. The drawings referred to below are for illustrative purposes only and are not necessarily drawn to scale. The description of the embodiments related to the present invention will not be repeated, except for those skilled in the art.

First, please refer to fig. 2, which is a schematic cross-sectional view of a iii-v semiconductor device according to the present invention. As shown in fig. 2, the iii-v semiconductor device of the present invention includes a bottommost substrate 10 made of silicon, sapphire, or silicon carbide, particularly a silicon substrate (Si substrate). Then, an epitaxial layer 20 is disposed on the substrate 10, wherein the epitaxial layer 20 is made of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and may be formed by a gallium nitride layer, and may be a multilayer structure, and the multilayer structure is formed by stacking gallium nitride layers or aluminum gallium nitride layers with different five-to-three ratios one on another. Next, a plurality of contact regions 30 are disposed on the epitaxial layer 20, wherein the contact regions 30 are metal layers. In order to simplify the process steps and define the active region, the present invention employs a laser cutting method to cut the epitaxial layer 20 at the periphery of every two contact regions 30 so as to cut a plurality of channels 40 on the epitaxial layer 20, and the plurality of channels 40 segment and separate the epitaxial layer 20. Each via 40 extends from the epitaxial layer 20 to a portion of the substrate 10 and exposes a surface of the substrate 10. Therefore, an active region is defined between each two channels 40, and at least two contact regions 30 are included in the active region. In the invention, the laser with the wavelength suitable for the III-V heterostructure can rapidly break the covalent bond of III-V material, and in the preferred embodiment of the invention, the wavelength of the laser is 255nm-375 nm.

Next, referring to fig. 3A to fig. 3E, a flow chart of steps for forming an active region and a contact region in a iii-v semiconductor device according to the present invention is shown. First, as shown in fig. 3A, a substrate 10 is provided, and the material of the substrate 10 is silicon, sapphire, or silicon carbide. A iii-v epitaxial layer 20 is then formed on the substrate 10 using common epitaxial techniques. Next, as shown in fig. 3B, the epitaxial layer 20 is covered with the evaporation mask 12, and the evaporation mask 12 is designed to have a pattern for forming the contact region 30. Next, as shown in fig. 3C, a metal plating film is formed through the vapor deposition mask 12, and a metal layer 30 is sputtered on the epitaxial layer 20. Next, as shown in fig. 3D, the evaporation mask 12 is removed, and the contact region 30 is formed at a predetermined position on the epitaxial layer 20. Finally, as shown in fig. 3E, the epitaxial layer 20 is cut by laser to form the channel 40, so as to complete the structure of the present invention.

As can be seen from the above, compared to the prior art, the present invention reduces the photolithography process by 60-80%, and does not require expensive photoresist, thereby saving the manufacturing cost. For measuring the Hall effect, the verification efficiency of the epitaxial quality is greatly accelerated, and the time consumption can be shortened by more than 80%.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; while the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A group iii-v semiconductor device, comprising:

a substrate;

an epitaxial layer disposed on the substrate; and

a plurality of contact regions disposed on the epitaxial layer;

the epitaxial layer comprises a plurality of channels, the channels extend from the epitaxial layer to part of the substrate and expose the surface of the substrate, an active region is arranged between every two channels, and at least two contact regions are arranged in the active region.

2. The group iii-v semiconductor device of claim 1, wherein the channel segments the epitaxial layer.

3. The group iii-v semiconductor device of claim 1, wherein the via formation method is laser cutting.

4. The group iii-v semiconductor device of claim 1, wherein the contact region is a metal layer.

5. The group iii-v semiconductor device of claim 1, wherein the substrate is silicon, sapphire, or silicon carbide.

6. The group iii-v semiconductor device of claim 1, wherein the epitaxial layer is of gallium nitride or aluminum gallium nitride.

7. The group iii-v semiconductor device of claim 1, wherein the epitaxial layer comprises at least one gallium nitride layer.

8. The group iii-v semiconductor device of claim 1, wherein the epitaxial layer is a multilayer structure having different five to three ratios.

Images