CN211507637U - Semiconductor structure - Google Patents
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- CN211507637U CN211507637U CN202020400433.7U CN202020400433U CN211507637U CN 211507637 U CN211507637 U CN 211507637U CN 202020400433 U CN202020400433 U CN 202020400433U CN 211507637 U CN211507637 U CN 211507637U
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Abstract
A semiconductor structure, comprising: a memory chip; a temperature detection unit for detecting a temperature of the memory chip before the memory chip is started; and the control chip is used for heating the storage chip before the storage chip is started, judging whether the temperature detected by the temperature detection unit reaches a set threshold value or not, and controlling the storage chip to be started if the temperature detected by the temperature detection unit reaches the set threshold value. When the utility model discloses a semiconductor structure work is when low temperature environment, can make memory chip heat up to the settlement threshold value through control chip to bit line, word line and metal connecting line (metal contact) in the memory chip can be prevented because ambient temperature crosses the increase of the resistance that brings excessively, thereby the write-in time when having reduced under the low temperature environment carrying out data writing to the memory has improved the stability that the memory was write in.
Description
Technical Field
The utility model relates to a memory field especially relates to a semiconductor structure.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and a Memory array region thereof is composed of many repetitive Memory cells. Each memory cell generally includes a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor, and a voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line or written into the capacitor through the bit line for storage.
The prior art has the problems that the writing time is long and the writing stability still needs to be improved when the memory is written in a low-temperature environment.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is how to reduce the write-in time when carrying out data writing to the memory in low temperature environment, improves the stability of writing in.
Therefore, the utility model provides a semiconductor structure, include:
a memory chip;
a temperature detection unit for detecting a temperature of the memory chip before the memory chip is started;
and the control chip is used for heating the storage chip before the storage chip is started, judging whether the temperature detected by the temperature detection unit reaches a set threshold value or not, and controlling the storage chip to be started if the temperature detected by the temperature detection unit reaches the set threshold value.
Optionally, the number of the memory chips is 1 or greater than or equal to 2, and when the number of the memory chips is greater than or equal to 2, the memory chips are sequentially stacked upward.
Optionally, the memory chip is located on the control chip, and the memory chip is electrically connected to the control chip.
Optionally, still include the circuit base plate, connecting line has in the circuit base plate, memory chip and control chip all are located the circuit base plate, memory chip and control chip are connected through the connecting line in the circuit base plate.
Optionally, the temperature detection units are electrically connected to the control chip, the number of the temperature detection units is 1 or more than or equal to 2, and the temperature detection units are located in the control chip or in the memory chip, or on the circuit substrate between the memory chip and the control chip.
Optionally, when the number of the temperature detection units is 1, and the control chip determines that the temperature detected by the 1 temperature detection unit reaches a set threshold, all the memory chips are controlled to start.
Optionally, when the number of the temperature detection units is 1 and the number of the memory chips is greater than or equal to 2, the control chip controls the memory chip closest to the control chip to start first when judging that the temperature of the 1 temperature detection unit reaches a set threshold, and then controls the other memory chips above to start sequentially.
Optionally, when the number of the temperature detection units is greater than or equal to 2, and when the number of the memory chips is greater than or equal to 2, each memory chip has one temperature detection unit, the control chip sequentially judges whether all the temperatures detected by the temperature detection units reach the set threshold, and if the temperature detected by a certain temperature detection unit reaches the set threshold, the memory chip corresponding to the temperature detection unit is controlled to start.
Optionally, after the control chip controls the memory chip to start, the control chip further controls the memory chip to perform writing, reading and erasing operations.
Optionally, before the control chip heats the memory chip, the control chip is started first, and the control chip heats the memory chip by using heat generated by the control chip after being started.
Optionally, the control chip has an additional heating circuit therein for heating the memory chip.
Optionally, before or after the control chip heats the memory chip, the control chip determines whether the temperature of the memory chip detected by the temperature detection unit reaches a set threshold, and if not, controls the heating circuit to heat the memory chip, and if so, controls the heating circuit to stop heating the memory chip.
Optionally, the memory chip is a DRAM memory chip.
Compared with the prior art, the utility model discloses technical scheme has following advantage:
the utility model discloses a semiconductor structure, include: a memory chip; a temperature detection unit for detecting a temperature of the memory chip before the memory chip is started; and the control chip is used for heating the storage chip before the storage chip is started, judging whether the temperature detected by the temperature detection unit reaches a set threshold value or not, and controlling the storage chip to be started if the temperature detected by the temperature detection unit reaches the set threshold value. Through control chip and temperature detecting element's cooperation, control chip heats memory chip before memory chip starts, temperature detecting element detects memory chip's temperature before memory chip starts, control chip judges whether the temperature that temperature detecting element detected reaches the settlement threshold value, if reach the settlement threshold value, then control memory chip starts, therefore works as the utility model discloses a semiconductor structure work is when low temperature environment, can make memory chip heat up to the settlement threshold value through control chip to bit line, word line and metal connecting line (metal contact) in the memory chip can be prevented because the increase of the resistance that ambient temperature crossed the low and brought, thereby write in time when having reduced under the low temperature environment when carrying out data writing to the memory has improved the stability that the memory wrote in.
Further, the quantity of temperature detecting element is 1, and is concrete, 1 temperature accurate measurement unit can be located control chip, or 1 temperature detecting element also can be located storage chip, or 1 temperature detecting element also can be located the circuit base plate between storage chip and the control chip, control chip judges when the temperature that 1 temperature detecting element detected reaches the settlement threshold value, then control all storage chip starts. When a plurality of memory chips exist in the semiconductor structure, the control structure and the control mode are relatively simple, the writing time of writing data into the memory chips in a low-temperature environment can be shortened, and the writing stability of the memory chips is improved.
Further, when the number of the temperature detection units is 1 and the number of the memory chips is greater than or equal to 2, the control chip controls the memory chip closest to the control chip to start first and then controls the other memory chips on the memory chip to start sequentially when judging that the temperature of the 1 temperature detection unit reaches a set threshold value. When a plurality of memory chips exist in the semiconductor structure, each memory chip can be started after reaching a set threshold temperature by the control structure and the control mode, so that the starting time precision of each memory chip is improved, the writing time of writing data into each memory chip in a low-temperature environment can be shortened, and the writing stability of each memory chip is improved.
Further, when the number of the temperature detection units is greater than or equal to 2, and the number of the storage chips is greater than or equal to 2, each storage chip is provided with one temperature detection unit, the control chip sequentially judges whether the temperature detected by the temperature detection units reaches a set threshold value, and if the temperature detected by a certain temperature detection unit reaches the set threshold value, the storage chip corresponding to the temperature detection unit is controlled to be started. When a plurality of memory chips exist in the semiconductor structure, the control structure and the control method can further improve the precision of the starting time of each memory chip, further reduce the writing time of writing data into each memory chip in a low-temperature environment, and further improve the stability of writing data into each memory chip.
Further, before the control chip heats the storage chip, the control chip is started first, and the control chip heats the storage chip by utilizing heat generated by the control chip after being started, so that an additional heating circuit is not needed, and the structure of the semiconductor structure is simplified.
Further, the control chip may have an additional heating circuit therein for heating the memory chip. Before or after the control chip heats the storage chip, the control chip judges whether the temperature of the storage chip detected by the temperature detection unit reaches a set threshold value, if not, the heating circuit is controlled to heat the storage chip, and if the temperature of the storage chip does not reach the set threshold value, the heating circuit is controlled to stop heating the storage chip. Therefore, the accurate control of the heating process is realized, the temperature of the memory chip can be kept near the set threshold, the temperature of the memory chip is prevented from being too high or too low, and the writing time of the memory can be kept short all the time.
Drawings
Fig. 1-7 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention;
fig. 8 is a schematic flow chart illustrating a semiconductor structure preheating method according to an embodiment of the present invention.
Detailed Description
As described in the background art, when writing into a memory in a low-temperature environment, there are problems that the writing time is long and the writing stability needs to be improved.
It has been found that when a conventional memory operates in a low-temperature environment, the resistance of bit lines, word lines, metal lines (metal contacts), and the like in the memory increases due to a temperature drop, and the increase in resistance changes or increases the time for writing data into the memory, which affects the stability of memory writing.
Therefore, the utility model provides a semiconductor structure includes: a memory chip; a temperature detection unit for detecting a temperature of the memory chip before the memory chip is started; and the control chip is used for heating the storage chip before the storage chip is started, judging whether the temperature detected by the temperature detection unit reaches a set threshold value or not, and controlling the storage chip to be started if the temperature detected by the temperature detection unit reaches the set threshold value. Through control chip and temperature detecting element's cooperation, control chip heats memory chip before memory chip starts, temperature detecting element detects memory chip's temperature before memory chip starts, control chip judges whether the temperature that temperature detecting element detected reaches the settlement threshold value, if reach the settlement threshold value, then control memory chip starts, therefore works as the utility model discloses a semiconductor structure work is when low temperature environment, can make memory chip heat up to the settlement threshold value through control chip to bit line, word line and metal connecting line (metal contact) in the memory chip can be prevented because the increase of the resistance that ambient temperature crossed the low and brought, thereby write in time when having reduced under the low temperature environment when carrying out data writing to the memory has improved the stability that the memory wrote in.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In describing the embodiments of the present invention in detail, the drawings are not necessarily to scale, and the drawings are merely exemplary and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1-7 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention; fig. 8 is a schematic flow chart illustrating a semiconductor structure preheating method according to an embodiment of the present invention.
Referring to fig. 1, an embodiment of the present invention provides a semiconductor structure, including:
a memory chip 201;
a temperature detection unit 203 for detecting the temperature of the memory chip 201 before the memory chip 201 is started up;
the control chip 301 is configured to heat the memory chip 201 before the memory chip 201 is started, determine whether the temperature detected by the temperature detection unit 203 reaches a set threshold, and control the memory chip 201 to start if the temperature reaches the set threshold.
The memory chip 201 is a conventional memory capable of performing data writing, data reading and/or data deleting, the memory chip 201 is formed by a semiconductor integrated manufacturing process, specifically, the memory chip 201 may include a memory array and a peripheral circuit connected to the memory array, the memory array includes a plurality of memory cells, bit lines, word lines and metal connecting lines (metal contacts) connected to the memory cells, the memory cells are used for storing data, and the peripheral circuit is a related circuit when the memory array is operated. In this embodiment, the memory chip 201 is a DRAM memory chip, the DRAM memory chip includes a plurality of memory cells, the memory cells generally include a capacitor and a transistor, a gate of the transistor is connected to a word line, a drain of the transistor is connected to a bit line, and a source of the transistor is connected to the capacitor. The memory chip 201 may be other types of memory chips in other embodiments.
The number of the memory chips 201 is at least one, and specifically, the number of the memory chips 201 may be 1 or more than or equal to 2. And when the number of the memory chips is more than or equal to 2, the plurality of memory chips are sequentially stacked upwards to form a memory chip stacking structure. In this embodiment, referring to fig. 2, taking the number of the memory chips 201 as 4 as an example, the 4 memory chips 201 are stacked from bottom to top in sequence to form a memory chip stack structure, and the adjacent memory chips 201 are attached together through a bonding process or an adhesion process. In one embodiment, a through silicon via interconnection (TSV) is formed in the memory chip 201, and the memory chip 201 and the control chip 301 are electrically connected through the TSV. When there are a plurality of memory chips 201 stacked, each of the memory chips 201 may be connected with the control chip 201 through a different through-silicon via interconnection structure (TSV). In other embodiments, the memory chip 201 may also be connected to the control chip 301 through metal wires (formed through a wire bonding process).
In this embodiment, the memory chip 201 is located on the control chip 301, and the memory chip 201 is electrically connected to the control chip 301. Specifically, when there is only one memory chip 201, the control chip 301 is bonded to the memory chip 201, and when there are a plurality of memory chips 201 forming a memory chip stack structure, the control chip 301 is bonded to the memory chip 201 at the bottom layer in the stack structure.
In other embodiments, the memory chip 201 and the control chip 301 may adopt different connection manners, please refer to fig. 4 (or fig. 4-7), the semiconductor structure further includes a circuit substrate 401, the circuit substrate 401 has a connection line, the memory chip 201 and the control chip 301 are both located on the circuit substrate 104, the memory chip 201 and the control chip 301 are connected by the connection line in the circuit substrate 104, and specifically, the circuit substrate 401 may be a PCB substrate.
Referring to fig. 1 or 4, the control chip 301 is formed through a semiconductor integrated manufacturing process. The control chip 301 can be used for heating the memory chip 201 to enable the temperature of the memory chip 201 to reach a set threshold (the set threshold can be set in the control chip 301, and the specific size of the set threshold can be set according to actual needs or experience), and the control chip 301 is further used for controlling the startup of the memory chip 201 (the startup of the memory chip includes power-on and self-detection) and performing related operations on the memory chip 201 (the related operations include writing data into the memory chip 201, reading data from the memory chip 201, deleting data accessed in the memory chip 201, and the like).
The semiconductor structure further comprises a temperature detection unit 203, the temperature detection unit 203 is used for measuring the temperature of the memory chip 201 before the memory chip 201 is started, the temperature detection unit 203 is electrically connected with the control chip 301, the temperature detected by the temperature detection unit 203 is transmitted to the control chip, and the temperature measured by the temperature detection unit 203 is used as a basis for the control chip 301 to control the start of the memory chip 201. Specifically, through the cooperation of the control chip 301 and the temperature detection unit 203, the control chip 301 heats the memory chip 201 before the memory chip 201 is started, the temperature detection unit 203 detects the temperature of the memory chip 201 before the memory chip 201 is started, the control chip 30 determines whether the temperature detected by the temperature detection unit 203 reaches a set threshold, and controls the memory chip 201 to be started if the temperature reaches the set threshold, so that when the semiconductor structure of the present invention works in a low-temperature environment, the control chip 301 can heat the memory chip 201 to the set threshold, thereby preventing the bit line, the word line, and the metal connecting line (metal contact portion) in the memory chip from increasing in resistance due to too low environmental temperature, and reducing the writing time when data is written into the memory in the low-temperature environment, the stability of memory writing is improved.
The temperature detection unit 203 comprises a temperature sensor, and the temperature sensor is used for sensing temperature and converting the sensed temperature into an electric signal. In a specific embodiment, the temperature sensor is a PN junction temperature sensor or a capacitance temperature sensor, and the temperature sensor may be formed in the memory chip 201 or the control chip 301 through a semiconductor integrated manufacturing process, or located on the circuit substrate 104 (refer to fig. 5) between the memory chip 201 and the control chip 301
The number of the temperature detection units 203 may be 1 or 2 or more, and the temperature detection units 203 may be located in the control chip 301 or in the memory chip 201.
In an embodiment, the number of the temperature detecting units 203 is 1, specifically, the 1 temperature detecting unit 203 may be located in the control chip 203 (refer to fig. 1 or fig. 4), or the 1 temperature detecting unit 203 may also be located in the memory chip 201 (when there is only one memory chip 201, the one temperature detecting unit 203 is directly located in the memory chip 201; when a plurality of memory chips 201 form a stacked structure, the one temperature detecting unit 203 is located in one of the memory chips 201, preferably, in the memory chip 201 located at the lowest layer in the stacked structure (refer to fig. 2 or fig. 6)), or the 1 temperature detecting unit 203 may also be located on the circuit substrate 104 (refer to fig. 5) between the memory chip 201 and the control chip 301, and when the control chip 301 determines that the temperature detected by the 1 temperature detecting unit reaches a set threshold, all the memory chips 201 are controlled to be started. When a plurality of memory chips 201 exist in the semiconductor structure, the control structure and the control mode are relatively simple, the writing time of writing data into the memory chips in a low-temperature environment can be reduced, and the writing stability of the memory chips is improved.
In another embodiment, referring to fig. 1 (or fig. 2, or fig. 4 to fig. 6), when the number of the temperature detection units 203 is 1 and the number of the memory chips 201 is greater than or equal to 2, and when the control chip 301 determines that the temperature of the 1 temperature detection unit reaches a set threshold, the memory chip 201 closest to the control chip 301 is controlled to start, and then the other memory chips 201 above are controlled to start sequentially. Specifically, referring to fig. 2, when there are 4 memory chips 201, when the control chip 301 determines that the temperature of the 1 temperature detection unit reaches the set threshold, the memory chip 201 closest to the control chip 301 (the memory chip at the bottom layer in the stacked structure) is controlled to start, and then the other 3 memory chips 201 above are controlled to start sequentially. When a plurality of memory chips 201 exist in the semiconductor structure, the control structure and the control method can enable each memory chip 201 to be started after the memory chip 201 reaches the set threshold temperature, so that the precision of the starting time of each memory chip 201 is improved, the writing time of writing data into each memory chip in a low-temperature environment can be reduced, and the stability of writing data into each memory chip is improved.
In another embodiment, referring to fig. 3 (or fig. 7), when the number of the temperature detection units 203 is greater than or equal to 2, and the number of the memory chips 201 is greater than or equal to 2, each memory chip 201 has one temperature detection unit 203, and the control chip 301 sequentially determines whether the temperatures detected by all the temperature detection units 203 reach the set threshold, and if the temperature detected by one of the temperature detection units 203 reaches the set threshold, controls the memory chip corresponding to the temperature detection unit 203 to start. Specifically, there are 4 memory chips 201 in the stacked structure shown in fig. 3 (or fig. 7), and each memory chip 201 has a corresponding temperature detection unit 203, so that each temperature detection unit 203 detects the temperature of the corresponding memory chip 201 to obtain four temperature detection values, the control chip 301 sequentially determines whether the temperature detected by the 4 temperature detection units 203 reaches a set threshold, if the temperature detected by one of the temperature detection units 203 reaches the set threshold, the control chip 203 controls the memory chip corresponding to the temperature detection unit 203 to start, for example, when the temperature detected by the temperature detection unit 203 in the memory chip 201 at the bottom of the stacked structure first reaches the set threshold, the control chip 301 controls the memory chip 201 at the bottom of the stacked structure to start first, and then, when the temperature detected by the corresponding temperature detection unit 203 in the memory chip 201 at the second last layer of the stacked structure also reaches the set threshold, the control unit 301 then controls the memory chip 201 on the next to last layer in the stacked structure to be activated, the memory chips 201 on the upper two layers to be activated, and so on. When a plurality of memory chips 201 exist in the semiconductor structure, the control structure and the control method can further improve the precision of the starting time of each memory chip 201, further reduce the writing time of writing data into each memory chip in a low-temperature environment, and further improve the stability of writing data into each memory chip.
In an embodiment, before the control chip 301 heats the memory chip 201, the control chip 301 needs to be started first, for example, the control chip 301 is powered on and self-tested, when the control chip 301 is started, the control chip 301 does not issue an instruction to the memory chip 201, only when the temperature detected by the temperature detection unit reaches a set threshold value, the control chip 301 controls the memory chip 201 to be started, and the control chip 301 heats the memory chip by using the heat generated by the control chip 301 after being started, so that an additional heating circuit is not needed, and the structure of the semiconductor structure is simplified.
In an embodiment, after the control chip 301 controls the memory chip 201 to start, the control chip 301 further controls the memory chip 201 to perform writing, reading and erasing operations. Specifically, the control chip 301 has a control circuit therein, and the control circuit is used for controlling the memory chip 201 to start and controlling the memory chip 201 to perform writing, reading and erasing operations.
In another embodiment, the control chip 301 may have an additional heating circuit therein for heating the memory chip 201. Before or after the control chip 301 heats the memory chip 201, the control chip determines whether the temperature of the memory chip detected by the temperature detection unit reaches a set threshold, and if not, controls the heating circuit to heat the memory chip, and if so, controls the heating circuit to stop heating the memory chip. Therefore, the heating process can be accurately controlled, the temperature of the memory chip 201 can be kept near a set threshold, the temperature of the memory chip 201 is prevented from being too high or too low, and the writing time of the memory can be kept short all the time.
Referring to fig. 8, the present invention also provides a method of preheating a semiconductor structure, comprising the steps of:
step S101, providing a semiconductor structure, wherein the semiconductor structure comprises a storage chip, a control chip electrically connected with the storage chip and a temperature detection unit;
step S102, starting a control chip;
step S103, heating the memory chip which is not started through the control chip;
step S104, detecting the temperature of the memory chip through a temperature detection unit;
and step S105, judging whether the temperature detected by the temperature detection unit reaches a set threshold value through a control chip, and controlling the starting of the storage chip if the temperature reaches the set threshold value.
Specifically, the number of the temperature detection units is 1 or 2 or more, the number of the memory chips is 1 or 2 or more, and when the number of the memory chips is 2 or more, the memory chips are sequentially stacked upward.
In an embodiment, when the number of the temperature detection units is 1, and the control chip determines that the temperature detected by the 1 temperature detection unit reaches a set threshold, all the memory chips are controlled to be started.
In an embodiment, when the number of the temperature detection units is 1 and the number of the memory chips is greater than or equal to 2, and the control chip determines that the temperature of the 1 temperature detection unit reaches a set threshold, the memory chip closest to the control chip is controlled to start first, and then the other memory chips on the control chip are controlled to start sequentially.
In an embodiment, when the number of the temperature detection units is greater than or equal to 2, and the number of the memory chips is greater than or equal to 2, each memory chip has one temperature detection unit, and the control chip sequentially determines whether the temperatures detected by all the temperature detection units reach a set threshold, and controls the memory chip corresponding to the temperature detection unit to start if the temperature detected by one of the temperature detection units reaches the set threshold.
In an embodiment, after the control chip controls the memory chip to start, the control chip further controls the memory chip to perform writing, reading and erasing operations.
It should be noted that, the definitions or descriptions of the same or similar parts in this embodiment as those in the foregoing embodiment are not repeated in this embodiment, and specific reference is made to the definitions or descriptions of the corresponding parts in the foregoing embodiment of the semiconductor structure.
Although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the above-mentioned method and technical contents to make possible changes and modifications to the technical solution of the present invention without departing from the spirit and scope of the present invention, therefore, any simple modification, equivalent changes and modifications made to the above embodiments by the technical substance of the present invention all belong to the protection scope of the technical solution of the present invention.
Claims (13)
1. A semiconductor structure, comprising:
a memory chip;
a temperature detection unit for detecting a temperature of the memory chip before the memory chip is started;
and the control chip is used for heating the storage chip before the storage chip is started, judging whether the temperature detected by the temperature detection unit reaches a set threshold value or not, and controlling the storage chip to be started if the temperature detected by the temperature detection unit reaches the set threshold value.
2. The semiconductor structure of claim 1, wherein the number of the memory chips is 1 or 2 or more, and when the number of the memory chips is 2 or more, a plurality of the memory chips are sequentially stacked upward.
3. The semiconductor structure of claim 2, wherein the memory chip is located on a control chip, the memory chip being electrically connected to the control chip.
4. The semiconductor structure of claim 2, further comprising a circuit substrate having connection lines therein, the memory chip and the control chip being located on the circuit substrate, the memory chip and the control chip being connected by the connection lines in the circuit substrate.
5. The semiconductor structure according to claim 3 or 4, wherein the temperature detection units are electrically connected to the control chip, the number of the temperature detection units is 1 or 2 or more, and the temperature detection units are located in the control chip or in the memory chip or on a wiring substrate between the memory chip and the control chip.
6. The semiconductor structure of claim 5, wherein when the number of the temperature detection units is 1, and the control chip determines that the temperature detected by the 1 temperature detection units reaches a set threshold, the control chip controls all the memory chips to be activated.
7. The semiconductor structure of claim 5, wherein when the number of the temperature detection units is 1 and the number of the memory chips is greater than or equal to 2, the control chip controls the memory chip closest to the control chip to start first and then controls the other memory chips above to start sequentially when judging that the temperature of the 1 temperature detection unit reaches a set threshold.
8. The semiconductor structure of claim 5, wherein when the number of the temperature detection units is 2 or more and the number of the memory chips is 2 or more, each memory chip has one temperature detection unit, the control chip sequentially determines whether the temperatures detected by all the temperature detection units reach a set threshold, and controls the memory chip corresponding to one of the temperature detection units to be activated if the temperature detected by one of the temperature detection units reaches the set threshold.
9. The semiconductor structure of claim 1, wherein after the control chip controls the memory chip to be activated, the control chip further controls the memory chip to perform write, read and erase operations.
10. The semiconductor structure of claim 9, wherein the control chip is activated before the control chip heats the memory chip, and the control chip heats the memory chip using self-generated heat after activation.
11. The semiconductor structure of claim 1, wherein the control chip has an additional heating circuit therein for heating the memory chip.
12. The semiconductor structure of claim 11, wherein the control chip determines whether the temperature of the memory chip detected by the temperature detection unit reaches a set threshold before or after the memory chip is heated, and controls the heating circuit to heat the memory chip if the temperature of the memory chip detected by the temperature detection unit does not reach the set threshold, and controls the heating circuit to stop heating the memory chip if the temperature of the memory chip reaches the set threshold.
13. The semiconductor structure of claim 1, wherein the memory chip is a DRAM chip.
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| CN202020400433.7U CN211507637U (en) | 2020-03-25 | 2020-03-25 | Semiconductor structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021189887A1 (en) * | 2020-03-25 | 2021-09-30 | 长鑫存储技术有限公司 | Semiconductor structure and preheating method therefor |
| WO2022000926A1 (en) * | 2020-06-30 | 2022-01-06 | 长鑫存储技术有限公司 | Semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021189887A1 (en) * | 2020-03-25 | 2021-09-30 | 长鑫存储技术有限公司 | Semiconductor structure and preheating method therefor |
| US11862223B2 (en) | 2020-03-25 | 2024-01-02 | Changxin Memory Technologies, Inc. | Semiconductor structure and preheating method thereof |
| WO2022000926A1 (en) * | 2020-06-30 | 2022-01-06 | 长鑫存储技术有限公司 | Semiconductor device |
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