CN211505687U - Residual voltage memory circuit and residual voltage detection device - Google Patents
Residual voltage memory circuit and residual voltage detection device Download PDFInfo
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- CN211505687U CN211505687U CN201921901535.0U CN201921901535U CN211505687U CN 211505687 U CN211505687 U CN 211505687U CN 201921901535 U CN201921901535 U CN 201921901535U CN 211505687 U CN211505687 U CN 211505687U
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Abstract
The utility model discloses a residual voltage memory circuit, which comprises a residual voltage signal input end, a residual voltage signal output end, a trigger module, a resetting module and a power module, wherein the residual voltage signal input end, the residual voltage signal output end, the trigger module, the resetting module and the power module are used for connecting a residual voltage signal identification circuit; the power supply end is connected with the power supply module, the trigger signal input end is connected with the residual voltage signal input end, the reset end is connected with the reset module, and the trigger signal output end is connected with the residual voltage signal output end; the trigger module further comprises a JK trigger, a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a first capacitor, and the reset module comprises an eighth resistor and a second capacitor. Correspondingly, the utility model also discloses two kinds of residual voltage detection device. The utility model discloses a low voltage drive's trigger module comes memory residual voltage signal, low power dissipation, the energy can be saved.
Description
Technical Field
The utility model relates to a power electronic technology field especially relates to residual voltage memory circuit and residual voltage detection device.
Background
In a power supply system of a power distribution network, if a branch circuit is short-circuited, the voltage on a bus connected with the branch circuit is seriously reduced suddenly, the residual voltage of the bus is generally lower than 20% of the rated voltage, and the bus voltage can be recovered only when a branch circuit breaker is disconnected and the short-circuit fault is removed. The time of bus voltage from abrupt drop to recovery is the time of breaker breaking short circuit fault, about 0.1 second, that is, the time of microcomputer comprehensive protection fault judgment (20ms-30ms), plus the intrinsic action time of breaker (40ms-80ms), plus the arc zero crossing time (about 16 ms). During the period of bus voltage sag, the enterprise power supply system is called as 'power dazzling'. During the electricity dazzling period, the residual voltage of the bus is very low, so that the operation of some power distribution terminals in a region without short-circuit fault is interrupted. The feeder line terminal can receive the residual voltage signal sent by the residual voltage detection device under the electrified state, and when the feeder line terminal loses the power, the residual voltage signal cannot be normally received and corresponding fault indication is made.
The prior art provides a residual voltage detection device, when a feeder terminal is powered off, a backup power supply supplies power, a residual voltage identification circuit acquires a voltage signal from a primary incoming line PT, and judgment and identification are performed to determine whether the residual voltage is generated; then, a residual voltage signal sent by the residual voltage identification circuit is received through a memory relay element and is stored; and the feeder terminal acquires the residual voltage signal transmitted by the memory relay element at the moment of power-on and gives a corresponding fault indication. The memory relay element commonly used in the prior art needs a large enough voltage to drive, and has high power consumption, which greatly influences the service life of a backup power supply.
Disclosure of Invention
The utility model aims to solve the technical problem that a residual voltage memory circuit and residual voltage detection device are provided, remember the residual voltage signal through low-voltage drive's trigger module, the low power dissipation, the energy can be saved.
In order to solve the technical problem, the utility model provides a residual voltage memory circuit, which comprises a residual voltage signal input end, a residual voltage signal output end, a trigger module, a resetting module and a power module, wherein the residual voltage signal input end, the residual voltage signal output end, the trigger module, the resetting module and the power module are used for connecting a residual voltage identification circuit;
the power supply end is connected with the power supply module, the trigger signal input end is connected with the residual voltage signal input end, the reset end is connected with the reset module, and the trigger signal output end is connected with the residual voltage signal output end;
the trigger module further comprises a JK trigger, a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a first capacitor, and the resetting module comprises an eighth resistor and a second capacitor;
the power supply end of the JK trigger is connected with the power supply end, the first input end of the JK trigger is respectively connected with the trigger signal input end and the first end of the first resistor, the first end of the first resistor is grounded through the second resistor, the second end of the first resistor is respectively connected with the first end of the first capacitor and the clock input end of the JK trigger, the second end of the first capacitor is grounded, the third resistor is connected with the first capacitor in parallel, the clear end of the JK trigger is connected with the reset end, the second input end of the JK trigger and the set end of the JK trigger are grounded through the fourth resistor, the in-phase output end of the JK trigger is connected with the negative electrode of the first diode, and the positive electrode of the first diode is respectively connected with the first end of the sixth resistor and the positive electrode of the second diode through the fifth resistor, a second end of the sixth resistor is connected to a power supply, a cathode of the second diode is respectively connected with a first end of the seventh resistor and the trigger signal output end, and a second end of the seventh resistor is grounded;
the first end of the eighth resistor is connected to a feeder terminal power supply, the second end of the eighth resistor is respectively connected with the first end of the second capacitor and the reset end of the trigger module, and the second end of the second capacitor is grounded.
Further, the power module comprises a third diode, a fourth diode, a ninth resistor and a battery;
the anode of the third diode is connected to a feeder terminal power supply, the cathode of the third diode is respectively connected with the power supply end of the trigger module and the cathode of the fourth diode, the anode of the fourth diode is connected with the first end of the ninth resistor, the second end of the ninth resistor is connected with the anode of the battery, and the cathode of the battery is grounded.
Further, the JK trigger adopts a chip CD4027 BM.
The utility model provides a residual voltage memory circuit, when the residual voltage signal input end received the high level residual voltage signal, this high level signal charges for first electric capacity through first resistance, the first input of JI trigger is the high level, because the second input of JK trigger and the setting end of JK trigger pass through fourth resistance ground connection, keep the low level, when first electric capacity charges, the clock input end of JI trigger forms the rising edge signal, the cophase output end of JK trigger exports the high level signal, first diode ends, residual voltage signal output end exports the high level residual voltage signal, when feeder terminal incoming call, feeder terminal power supply charges for the second electric capacity gradually through eighth resistance, delay a period, treat feeder terminal to receive provide the zero clearing signal of high level for the zero clearing end of JK trigger again after the residual voltage signal, thereby remember the residual voltage signal through trigger module, and after the feeder line terminal receives the high-level residual voltage signal, the residual voltage signal is cleared, and because the driving voltage of the JK trigger is small, the residual voltage signal is memorized through the trigger module driven by low voltage, so that the power consumption is low, and the energy is saved.
Correspondingly, the utility model also provides a residual voltage detection device, including residual voltage identification circuit and residual voltage memory circuit, residual voltage identification circuit includes A looks voltage input, B looks voltage input, C looks voltage input, partial pressure module, vary voltage module, rectifier module, filter module, voltage stabilizing module and discernment output;
the residual voltage memory circuit is the residual voltage memory circuit;
the voltage input end of the A phase, the voltage input end of the B phase and the voltage input end of the C phase are connected with the input end of the voltage dividing module, the output end of the voltage dividing module is connected with the input end of the voltage transforming module, the output end of the voltage transforming module is connected with the input end of the rectifying module, the output end of the rectifying module is connected with the input end of the filtering module, the output end of the filtering module is connected with the input end of the voltage stabilizing module, the output end of the voltage stabilizing module is connected with the identification output end, and the identification output end is connected with the residual voltage signal input end of the residual voltage memory circuit.
Further, the voltage transformation module comprises a first voltage transformer, a second voltage transformer, a tenth resistor and an eleventh resistor;
the first output end of the first voltage transformer is connected with the first end of the tenth resistor, the second output end of the first voltage transformer is connected with the second end of the tenth resistor, the first output end of the second voltage transformer is connected with the first end of the eleventh resistor, and the second output end of the second voltage transformer is connected with the second end of the eleventh resistor.
Further, the voltage division module comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor;
a first end of the twelfth resistor is connected to the a-phase voltage input terminal, a second end of the twelfth resistor is connected to the first input terminal of the first voltage transformer, a second input terminal of the first voltage transformer is connected to a first end of the thirteenth resistor, a second end of the thirteenth resistor is connected to the B-phase voltage input terminal and a first end of the fourteenth resistor, a second end of the fourteenth resistor is connected to the first input terminal of the second voltage transformer, a second input terminal of the second voltage transformer is connected to a first end of the fifteenth resistor, and a second end of the fifteenth resistor is connected to the C-phase voltage input terminal.
Further, the rectifier module comprises a first rectifier chip and a second rectifier chip, and the first rectifier chip and the second rectifier chip adopt a chip MB 8F;
the first end of the tenth resistor is connected with the first input end of the first rectifying chip, the second end of the tenth resistor is connected with the second input end of the first rectifying chip, the first end of the eleventh resistor is connected with the first input end of the second rectifying chip, the second end of the eleventh resistor is connected with the second input end of the second rectifying chip, the positive output end of the first rectifying chip and the positive output end of the second rectifying chip are both connected with the filtering module, and the negative output end of the first rectifying chip and the negative output end of the second rectifying chip are grounded.
Further, the filtering module comprises a sixteenth resistor and a third capacitor;
and the first end of the sixteenth resistor is respectively connected with the negative output end of the first rectifying chip and the positive output end of the second rectifying chip, and the second end of the sixteenth resistor is grounded through the third capacitor.
Further, the voltage stabilizing module comprises a TVS tube, and the input end of the TVS tube is connected with the first end of the third capacitor and the identification output end respectively.
The utility model also provides another residual voltage detection device, which comprises two residual voltage identification circuits, two trigger modules, a reset module, a power supply module and a seventeenth resistor;
the two residual voltage identification circuits are the residual voltage identification circuits, the two trigger modules are the trigger modules, the reset module is the reset module, and the power supply module is the power supply module;
the A phase voltage input end, the B phase voltage input end and the C phase voltage input end of one residual voltage identification circuit of the two residual voltage identification circuits are connected to a primary incoming line PT, the A phase voltage input end, the B phase voltage input end and the C phase voltage input end of the other residual voltage identification circuit of the two residual voltage identification circuits are connected to a bus PT, and the identification output ends of the two residual voltage identification circuits are respectively connected with the trigger signal input ends of the two trigger modules;
the power supply ends of the two trigger modules are connected with the power supply module, the resetting ends of the two trigger modules are connected with the resetting module, the resetting end of one trigger module of the two trigger modules is grounded through the seventeenth resistor, and the trigger signal output ends of the two trigger modules are connected to a feeder line terminal.
The utility model provides a residual voltage detection device, residual voltage identification circuit receives the residual voltage signal of inlet wire PT once through A looks voltage input end, B looks voltage input end and C looks voltage input end, received residual voltage signal carries out the partial pressure through voltage division module and handles, carry out the vary voltage through the vary voltage module and handle, carry out rectification processing through rectifier module, carry out filtering through filter module and handle, export for residual voltage memory circuit via the discernment output after rethread voltage division module steady voltage, residual voltage memory circuit remembers the residual voltage signal through low voltage drive's trigger module, treat that feeder terminal receives clear away the residual voltage signal again behind the high level residual voltage signal, the low power dissipation, the energy can be saved.
Drawings
FIG. 1 is a circuit schematic diagram of one embodiment of a residual voltage memory circuit provided by the present invention;
fig. 2 is a circuit block diagram of a first residual voltage detection device provided by the present invention;
fig. 3 is a schematic circuit diagram of an embodiment of a residual voltage identification circuit of a first residual voltage detection apparatus provided by the present invention;
fig. 4 is a circuit block diagram of a second residual voltage detection device provided by the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
Fig. 1 is a schematic circuit diagram of an embodiment of a residual voltage memory circuit according to the present invention.
The embodiment of the utility model provides a residual voltage memory circuit, including residual voltage signal input part VP1, residual voltage signal output part EN1, trigger module 1, reset module 2 and power module 3 that are used for connecting residual voltage signal identification circuit, trigger module 1 includes supply terminal VI, trigger signal input part a, reset terminal CY _ RST and trigger signal output part b;
the power supply end VI is connected with the power supply module 3, the trigger signal input end a is connected with the residual voltage signal input end VP1, the reset end CY _ RST is connected with the reset module 2, and the trigger signal output end b is connected with the residual voltage signal output end EN 1;
the trigger module 1 further comprises a JK trigger U12A, a first diode V3, a second diode V4, a first resistor RC4, a second resistor RC6, a third resistor RC5, a fourth resistor RC7, a fifth resistor RC2, a sixth resistor RC3, a seventh resistor RC10 and a first capacitor CC1, and the reset module 2 comprises an eighth resistor RC14 and a second capacitor CC 3;
a power supply terminal VDD of the JK flip-flop U12A is connected to the power supply terminal VI, a first input terminal 1J of the JK flip-flop U12A is connected to the trigger signal input terminal a and a first terminal of a first resistor RC4, respectively, a first terminal of the first resistor RC4 is grounded through a second resistor RC6, a second terminal of the first resistor RC4 is connected to a first terminal of a first capacitor CC1 and a clock input terminal C1 of the JK flip-flop U12A, a second terminal of the first capacitor CC1 is grounded, a third resistor RC5 is connected in parallel with a first capacitor CC1, a clear terminal R of the JK flip-flop U12A is connected to a reset terminal CY _ connected to a negative terminal of the JK flip-flop U12A, a second input terminal 1K of the JK flip-flop U12A and a set terminal S of the JK flip-flop U12A are grounded through a fourth resistor RC7, a non-phase output terminal Q of the JK flip-flop U12A is connected to a negative electrode of a first diode RST diode V3, a positive terminal V3 of the first diode V is connected to a positive terminal V4 and a first terminal RC 573, a second end of the sixth resistor RC3 is connected to the power supply VCC1, a cathode of the second diode V4 is respectively connected to a first end of the seventh resistor RC10 and the trigger signal output end b, and a second end of the seventh resistor RC10 is grounded;
a first end of the eighth resistor RC14 is connected to the feeder terminal VCC, a second end of the eighth resistor RC14 is connected to the first end of the second capacitor CC3 and the reset end CY _ RST of the flip-flop module 1, and a second end of the second capacitor CC3 is grounded.
In a specific implementation, when the residual voltage signal input terminal VP1 receives a high level residual voltage signal, the high level signal charges the first capacitor CC1 through the first resistor RC4, the first input terminal 1J of the JI flip-flop U12A is at a high level, since the second input terminal 1K of the JK flip-flop U12A and the set terminal S of the JK flip-flop U12A are grounded through the fourth resistor RC7 to maintain a low level, during the gradual charging process of the first capacitor CC1, the clock input terminal C1 of the JI flip-flop U12A forms a rising edge signal, the in-phase output terminal 1Q of the JK flip-flop U12A outputs a high level signal, the first diode V3 is turned off, the residual voltage signal output terminal EN1 outputs a high level residual voltage signal, when the feeder terminal VCC terminal receives an incoming call, the feeder terminal VCC gradually charges the second capacitor CC3 through the eighth resistor RC14, the zero clearing signal R of the JK flip-flop U12 is delayed for a period, and after the feeder terminal receives the high level residual voltage signal, the reset signal R12A is reset signal, therefore, the residual voltage signal is memorized through the trigger module U12A, the residual voltage signal is cleared after the feeder line terminal receives the high-level residual voltage signal, and the residual voltage signal is memorized through the trigger module driven by low voltage because the driving voltage of the JK trigger is small, so that the power consumption is low, and the energy is saved.
It should be noted that the eighth resistor RC14 and the second capacitor CC3 form the reset module 2. When the power supply terminal is powered on, the time is delayed for 200 seconds, then a high-level zero clearing signal is provided for the zero clearing end R of the JK trigger U12A, and the residual voltage signal can be automatically eliminated without an external input signal after the detected bus voltage is recovered to be normal.
Further, the power module 3 includes a third diode V1, a fourth diode V2, a ninth resistor RC1, and a battery BT 1;
the anode of the third diode V1 is connected to the feeder terminal VCC, the cathode of the third diode V1 is connected to the power supply terminal VI of the flip-flop module 2 and the cathode of the fourth diode V2, the anode of the fourth diode V2 is connected to the first end of the ninth resistor RC1, the second end of the ninth resistor RC1 is connected to the anode of the battery BT1, and the cathode of the battery BT1 is grounded.
It should be noted that the residual voltage memory circuit is powered by dual power supplies, a feeder terminal power supply VCC is used in normal operation, and a backup battery BT1 is automatically switched to be used after power loss, so as to keep the residual voltage memory circuit in a working state all the time, and meanwhile, a third diode V1 and a fourth diode V2 are used for isolating the circuit, so that multiplexing of an IO port of a feeder terminal processor is not affected.
Further, the JK flip-flop U12A employs a chip CD4027 BM. The CD4027BM trigger with small volume, wide voltage and low power consumption is used, the voltage range can reach 2.5-15V, and the sensitivity is high; the trigger voltage can be started only by 2.5V, the power consumption is only 50nW, the power consumption is low, and the energy is saved.
Referring to fig. 2, it is a circuit block diagram of a first residual voltage detection apparatus provided in the present invention.
The utility model provides a residual voltage detection device, including residual voltage identification circuit 11 and residual voltage memory circuit 12, residual voltage identification circuit 11 includes A phase voltage input Va, B phase voltage input Vb, C phase voltage input Vc, partial pressure module 4, vary voltage module 5, rectifier module 6, filter module 7, voltage stabilizing module 8 and discernment output VPO;
the residual voltage memory circuit 12 is the residual voltage memory circuit as the previous embodiment;
a phase voltage input end Va, B phase voltage input end V and C phase voltage input end Vc are connected with the input of voltage division module 4, the output of voltage division module 4 is connected with the input of voltage transformation module 5, the output of voltage transformation module 5 is connected with the input of rectification module 6, the output of rectification module 6 is connected with the input of filter module 7, the output of filter module 7 is connected with the input of voltage stabilization module 8, the output of voltage stabilization module 8 is connected with discernment output end VPO, discernment output end VPO is connected with residual voltage signal input end VP1 of residual voltage memory circuit 11.
It should be noted that the residual voltage identification circuit 11 receives a residual voltage signal of the primary incoming line PT9 through the a-phase voltage input terminal Va, the B-phase voltage input terminal Vb and the C-phase voltage input terminal Vc, the received residual voltage signal is subjected to voltage division processing by the voltage division module 4, voltage transformation processing is performed by the voltage transformation module 5, rectification processing is performed by the rectification module 6, filtering processing is performed by the filtering module 7, the voltage is stabilized by the voltage stabilization module 8 and then output to the residual voltage memory circuit 12 through the identification output terminal VPO, the residual voltage memory circuit 12 memorizes the residual voltage signal through the trigger module 1 driven by low voltage, the reset module 2 of the residual voltage memory circuit 12 sends a clear signal to the trigger module 1 after the feeder terminal 10 receives the high-level residual voltage signal, and clears the residual voltage signal, so that power consumption is low and energy is saved.
Referring to fig. 3, fig. 3 is a schematic circuit diagram of an embodiment of a residual voltage identification circuit of a first residual voltage detection device provided in the present invention, as shown in fig. 3, a voltage transformation module 5 includes a first voltage transformer PT11, a second voltage transformer PT12, a tenth resistor RT1, and an eleventh resistor RT 2;
the first output end of the first voltage transformer PT11 is connected with the first end of the tenth resistor RT1, the second output end of the first voltage transformer PT11 is connected with the second end of the tenth resistor RT1, the first output end of the second voltage transformer PT12 is connected with the first end of the eleventh resistor RT2, and the second output end of the second voltage transformer PT12 is connected with the second end of the eleventh resistor RT 2.
Further, the voltage division module 4 includes a twelfth resistor RL49, a thirteenth resistor RL56, a fourteenth resistor RL57 and a fifteenth resistor RL 64;
a first end of a twelfth resistor RL49 is connected to the a-phase voltage input end Va, a second end of the twelfth resistor RL49 is connected to a first input end of a first voltage transformer PT11, a second input end of the first voltage transformer PT11 is connected to a first end of a thirteenth resistor RL56, a second end of a thirteenth resistor RL56 is connected to the B-phase voltage input end Vb and a first end of a fourteenth resistor RL57, a second end of the fourteenth resistor RL57 is connected to a first input end of a second voltage transformer PT12, a second input end of a second voltage transformer PT12 is connected to a first end of a fifteenth resistor RL64, and a second end of a fifteenth resistor RL64 is connected to the C-phase voltage input end Vc.
Further, the rectifier module 6 includes a first rectifier chip B1 and a second rectifier chip B2, and the first rectifier chip B1 and the second rectifier chip B2 employ a chip MB 8F;
the first end of a tenth resistor RT1 is connected with the first input end of the first rectifying chip B1, the second end of the tenth resistor RT1 is connected with the second input end of the first rectifying chip B1, the first end of an eleventh resistor RT2 is connected with the first input end of the second rectifying chip B2, the second end of an eleventh resistor RT2 is connected with the second input end of the second rectifying chip B2, the positive output end of the first rectifying chip B1 and the positive output end of the second rectifying chip B2 are both connected with the filtering module 7, and the negative output end of the first rectifying chip B1 and the negative output end of the second rectifying chip B2 are grounded.
Further, the filtering module 7 includes a sixteenth resistor RA11 and a third capacitor CA 11;
a first end of the sixteenth resistor RA11 is connected to the negative output terminal of the first rectifying chip B1 and the positive output terminal of the second rectifying chip B2, respectively, and a second end of the sixteenth resistor RA11 is grounded through the third capacitor CA 11.
Further, the voltage stabilizing module 8 includes a TVS transistor TVS1, and input terminals of the TVS transistor TVS1 are respectively connected to the first terminal of the third capacitor CA11 and the identification output terminal VPO.
It should be noted that the twelfth resistor RL49, the thirteenth resistor RL56, the fourteenth resistor RL57 and the fifteenth resistor RL64 play a role in voltage division, the first voltage transformer PT11 and the second voltage transformer PT12 are responsible for converting a high voltage into a standard secondary voltage with a lower level according to a proportional relationship, the tenth resistor RT1 and the eleventh resistor RT2 are used for adjusting a transformation ratio of the voltage transformers, the first rectifying chip B1 and the second rectifying chip B2 play a role in rectification, the sixteenth resistor RA11 plays a role in voltage division, a protection circuit is not damaged, the third capacitor CA11 plays a role in filtering, and the TVS tube TVS1 plays a role in voltage clamping.
Referring to fig. 4, it is a circuit block diagram of a second residual voltage detection apparatus provided in the present invention.
The utility model provides a residual voltage detection device, which comprises two residual voltage identification circuits (111,211), two trigger modules (112,212), a reset module 113, a power supply module 114 and a seventeenth resistor RC 8;
the two residual voltage identification circuits (111,211) are the residual voltage identification circuits of the previous embodiments, the two trigger modules (112,212) are the trigger modules of the previous embodiments, the reset module 113 is the reset module of the previous embodiments, and the power module 114 is the power module of the previous embodiments;
an A-phase voltage input end Va1, a B-phase voltage input end Vb1 and a C-phase voltage input end Vc1 of the residual voltage identification circuit 111 are connected to a primary incoming line PT19, an A-phase voltage input end Va2, a B-phase voltage input end Vb2 and a C-phase voltage input end Vc2 of the residual voltage identification circuit 211 are connected to a bus line PT29, and identification output ends (VPO1 and VPO2) of the two residual voltage identification circuits (111 and 211) are respectively connected with trigger signal input ends (a1 and a2) of the two trigger modules (112 and 212);
the power supply terminals (VI1, VI2) of the two flip-flop modules (112,212) are both connected with the power supply module 114, the reset terminals (CY _ RST1, CY _ RST2) of the two flip-flop modules (112,212) are both connected with the reset module 113, the reset terminal CY _ RST2 of the flip-flop module 212 is grounded through a seventeenth resistor RC8, and the trigger signal output terminals (b1, b2) of the two flip-flop modules (112,212) are both connected to the feeder terminal 101.
In specific implementation, the residual voltage identification circuit 111 receives a first residual voltage signal of a primary incoming line PT19 through an a-phase voltage input terminal Va1, a B-phase voltage input terminal Vb1 and a C-phase voltage input terminal Vc1, performs voltage division processing on the received first residual voltage signal through a voltage division module 14, performs voltage transformation processing through a voltage transformation module 15, performs rectification processing through a rectification module 16, performs filtering processing through a filtering module 17, performs voltage stabilization through a voltage stabilization module 18, outputs the voltage-stabilized signal to the trigger module 112 through an identification output terminal VPO1, receives a second residual voltage signal of the bus PT29 through an a-phase voltage input terminal Va2, a B-phase voltage input terminal Vb2 and a C-phase voltage input terminal Vc2, performs voltage division processing on the received second residual voltage signal through a voltage division module 24, performs voltage transformation processing through a voltage transformation module 25, performs rectification processing through a rectification module 26, and performs filtering processing through a filtering module 27, and after the voltage is stabilized by the voltage stabilizing module 18, the voltage is output to the trigger module 212 through the identification output end VPO2, the low-voltage-driven trigger module 112 and the trigger module 212 respectively memorize the first residual voltage signal and the second residual voltage signal, and after the feeder line terminal 101 receives the first residual voltage signal and the second residual voltage signal, the reset module 113 respectively sends zero clearing signals to the trigger module 112 and the trigger module 212 to clear the residual voltage signals, so that the power consumption is low, and the energy is saved.
It should be noted that, the residual voltage signals of the primary incoming line PT19 and the bus PT29 are detected by the two residual voltage identification circuits 111, if the bus has a fault, the feeder terminal 101 locks the incoming line to be switched on, and if the incoming line has a fault, the feeder terminal 101 locks the bus, and no matter which side the fault occurs, the opposite side can be switched on to supply power. The two residual voltage identification circuits (111,211) use the same voltage stabilization module 18, the TVS of the voltage stabilization module 18 uses a chip ESDA6V1L, the output terminal of the filter module 17 of the residual voltage identification circuit 111 is connected with pin 2 of the chip ESDA6V1L, and the output terminal of the filter module 27 of the residual voltage identification circuit 211 is connected with pin 1 of the chip ESDA6V 1L. The two flip-flop modules (112,212) share the reset module 113 and the power supply module 114, the chip CD4027BM is a monolithic integrated circuit including two independent J-K master-slave flip-flops, and the JK flip-flops of the two flip-flop modules (112,212) can be implemented by using the chip CD4027 BM.
When the residual voltage signal input end receives a high-level residual voltage signal, the high-level signal charges a first capacitor through a first resistor, the first input end of a JI trigger is at a high level, because a second input end of a JK trigger and a set end of the JK trigger are grounded through a fourth resistor, the low level is kept, when the first capacitor is charged, a clock input end of the JI trigger forms a rising edge signal, a same-phase output end of the JK trigger outputs a high-level signal, a first diode is cut off, and a residual voltage signal output end outputs a high-level residual voltage signal, when a feeder terminal is powered on, a power supply of the feeder terminal gradually charges the second capacitor through an eighth resistor, the time is delayed for a period of time, the feeder terminal receives the high-level residual voltage signal and then provides a high-level zero clearing signal for a zero clearing end of the JK trigger, so that the residual voltage signal is memorized through a trigger module, and then clears the residual voltage signal after the feeder terminal receives the high-level residual voltage signal, because the driving voltage of the JK trigger is small, the residual voltage signal is memorized through the trigger module driven by low voltage, the power consumption is low, and the energy is saved.
The foregoing is a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the principle of the present invention, and these improvements and decorations are also considered as the protection scope of the present invention.
Claims (10)
1. A residual voltage memory circuit is characterized by comprising a residual voltage signal input end, a residual voltage signal output end, a trigger module, a resetting module and a power supply module, wherein the residual voltage signal input end, the residual voltage signal output end, the trigger module, the resetting module and the power supply module are used for being connected with a residual voltage identification circuit;
the power supply end is connected with the power supply module, the trigger signal input end is connected with the residual voltage signal input end, the reset end is connected with the reset module, and the trigger signal output end is connected with the residual voltage signal output end;
the trigger module further comprises a JK trigger, a first diode, a second diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a first capacitor, and the resetting module comprises an eighth resistor and a second capacitor;
the power supply end of the JK trigger is connected with the power supply end, the first input end of the JK trigger is respectively connected with the trigger signal input end and the first end of the first resistor, the first end of the first resistor is grounded through the second resistor, the second end of the first resistor is respectively connected with the first end of the first capacitor and the clock input end of the JK trigger, the second end of the first capacitor is grounded, the third resistor is connected with the first capacitor in parallel, the clear end of the JK trigger is connected with the reset end, the second input end of the JK trigger and the set end of the JK trigger are grounded through the fourth resistor, the in-phase output end of the JK trigger is connected with the negative electrode of the first diode, and the positive electrode of the first diode is respectively connected with the first end of the sixth resistor and the positive electrode of the second diode through the fifth resistor, a second end of the sixth resistor is connected to a power supply, a cathode of the second diode is respectively connected with a first end of the seventh resistor and the trigger signal output end, and a second end of the seventh resistor is grounded;
the first end of the eighth resistor is connected to a feeder terminal power supply, the second end of the eighth resistor is respectively connected with the first end of the second capacitor and the reset end of the trigger module, and the second end of the second capacitor is grounded.
2. The residual voltage memory circuit according to claim 1, wherein the power supply module includes a third diode, a fourth diode, a ninth resistor, and a battery;
the anode of the third diode is connected to a feeder terminal power supply, the cathode of the third diode is respectively connected with the power supply end of the trigger module and the cathode of the fourth diode, the anode of the fourth diode is connected with the first end of the ninth resistor, the second end of the ninth resistor is connected with the anode of the battery, and the cathode of the battery is grounded.
3. The residual voltage memory circuit according to claim 1 or 2, wherein the JK flip-flop employs a chip CD4027 BM.
4. A residual voltage detection device is characterized by comprising a residual voltage identification circuit and a residual voltage memory circuit, wherein the residual voltage identification circuit comprises an A-phase voltage input end, a B-phase voltage input end, a C-phase voltage input end, a voltage division module, a voltage transformation module, a rectification module, a filtering module, a voltage stabilization module and an identification output end;
the residual voltage memory circuit is the residual voltage memory circuit according to any one of claims 1 to 3;
the voltage input end of the A phase, the voltage input end of the B phase and the voltage input end of the C phase are connected with the input end of the voltage dividing module, the output end of the voltage dividing module is connected with the input end of the voltage transforming module, the output end of the voltage transforming module is connected with the input end of the rectifying module, the output end of the rectifying module is connected with the input end of the filtering module, the output end of the filtering module is connected with the input end of the voltage stabilizing module, the output end of the voltage stabilizing module is connected with the identification output end, and the identification output end is connected with the residual voltage signal input end of the residual voltage memory circuit.
5. The residual voltage detection device according to claim 4, wherein the transforming module comprises a first voltage transformer, a second voltage transformer, a tenth resistor and an eleventh resistor;
the first output end of the first voltage transformer is connected with the first end of the tenth resistor, the second output end of the first voltage transformer is connected with the second end of the tenth resistor, the first output end of the second voltage transformer is connected with the first end of the eleventh resistor, and the second output end of the second voltage transformer is connected with the second end of the eleventh resistor.
6. The residual voltage detection device according to claim 5, wherein the voltage division module comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a fifteenth resistor;
a first end of the twelfth resistor is connected to the a-phase voltage input terminal, a second end of the twelfth resistor is connected to the first input terminal of the first voltage transformer, a second input terminal of the first voltage transformer is connected to a first end of the thirteenth resistor, a second end of the thirteenth resistor is connected to the B-phase voltage input terminal and a first end of the fourteenth resistor, a second end of the fourteenth resistor is connected to the first input terminal of the second voltage transformer, a second input terminal of the second voltage transformer is connected to a first end of the fifteenth resistor, and a second end of the fifteenth resistor is connected to the C-phase voltage input terminal.
7. The residual voltage detection device according to claim 5, wherein said rectifying module comprises a first rectifying chip and a second rectifying chip, said first rectifying chip and said second rectifying chip are implemented by a chip MB 8F;
the first end of the tenth resistor is connected with the first input end of the first rectifying chip, the second end of the tenth resistor is connected with the second input end of the first rectifying chip, the first end of the eleventh resistor is connected with the first input end of the second rectifying chip, the second end of the eleventh resistor is connected with the second input end of the second rectifying chip, the positive output end of the first rectifying chip and the positive output end of the second rectifying chip are both connected with the filtering module, and the negative output end of the first rectifying chip and the negative output end of the second rectifying chip are grounded.
8. The residual voltage detection device according to claim 7, wherein said filter module comprises a sixteenth resistor and a third capacitor;
and the first end of the sixteenth resistor is respectively connected with the negative output end of the first rectifying chip and the positive output end of the second rectifying chip, and the second end of the sixteenth resistor is grounded through the third capacitor.
9. The residual voltage detection device according to claim 8, wherein the voltage stabilization module comprises a TVS tube, and input terminals of the TVS tube are respectively connected to the first terminal of the third capacitor and the identification output terminal.
10. A residual voltage detection device is characterized by comprising two residual voltage identification circuits, two trigger modules, a reset module, a power supply module and a seventeenth resistor;
the two residual voltage identification circuits are the residual voltage identification circuit according to any one of claims 4 to 9, the two flip-flop modules are the flip-flop modules according to any one of claims 1 to 3, the reset module is the reset module according to any one of claims 1 to 3, and the power supply module is the power supply module according to any one of claims 1 to 3;
the A phase voltage input end, the B phase voltage input end and the C phase voltage input end of one residual voltage identification circuit of the two residual voltage identification circuits are connected to a primary incoming line PT, the A phase voltage input end, the B phase voltage input end and the C phase voltage input end of the other residual voltage identification circuit of the two residual voltage identification circuits are connected to a bus PT, and the identification output ends of the two residual voltage identification circuits are respectively connected with the trigger signal input ends of the two trigger modules;
the power supply ends of the two trigger modules are connected with the power supply module, the resetting ends of the two trigger modules are connected with the resetting module, the resetting end of one trigger module of the two trigger modules is grounded through the seventeenth resistor, and the trigger signal output ends of the two trigger modules are connected to a feeder line terminal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114156844A (en) * | 2021-10-29 | 2022-03-08 | 山东电工电气集团新能科技有限公司 | On-site reclosing type feeder automatic protection device with residual voltage locking function |
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2019
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114156844A (en) * | 2021-10-29 | 2022-03-08 | 山东电工电气集团新能科技有限公司 | On-site reclosing type feeder automatic protection device with residual voltage locking function |
| CN114156844B (en) * | 2021-10-29 | 2024-03-22 | 山东电工电气集团新能科技有限公司 | In-situ coincident feeder line automatic protection device with residual voltage locking function |
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