CN211480026U - Nonvolatile memory structure - Google Patents

Abstract

The utility model discloses a nonvolatile memory structure belongs to integrated circuit technical field. The utility model discloses a memory structure includes: a substrate; at least two isolation structures, one end of each isolation structure extending into the substrate to expose sidewalls of the substrate; a recess is formed between each of the isolation structure sidewalls and an adjacent substrate sidewall, a portion of the recess having an inclined rectilinear cross-sectional shape and another portion of the recess having an arcuate curvilinear cross-sectional shape; the tunneling oxide layer is formed on one side of the substrate and covers the surface and the side wall of the substrate; the floating gate layer is formed on one side, away from the substrate, of the tunneling oxide layer and covers the tunneling oxide layer, the concave part and the isolation structure; the gate is formed between the floating gate layer and the tunneling oxide layer, and includes a plurality of current tunneling channel control surfaces. The utility model discloses the effectual gate that has improved reduces the electric leakage to the control of electric current tunneling passageway.

Description

Nonvolatile memory structure

Technical Field

The utility model belongs to the technical field of integrated circuit, especially, relate to a nonvolatile memory structure.

Background

Non-Volatile Memory (NVM) is all forms of solid-state Memory that does not require periodic refreshing of data stored in the Memory. Non-volatile memory includes all forms of read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (EEPROM), and Flash memory (Flash), as well as battery-powered Random Access Memory (RAM). As device feature sizes continue to shrink and integration continues to increase, conventional non-volatile memories based on charge storage face physical and technological limits. As the process size of the nonvolatile memory is continuously reduced, the short channel effect sce (short channel effect) is greatly affected, which results in the decrease of the control capability of the gate to the current channel and the increase of the leakage current.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a nonvolatile memory structure has solved the problem that the grid is weak to the controllability of electric current tunneling passageway among the current nonvolatile memory.

In order to solve the technical problem, the utility model discloses a realize through following technical scheme:

the utility model provides a nonvolatile memory structure, it includes:

a substrate;

at least two isolation structures, one end of each isolation structure extending into the substrate;

a recess formed between each of the isolation structure sidewalls and an adjacent substrate sidewall, a portion of the recess having an inclined straight-line cross-sectional shape and another portion of the recess having an arcuate curved cross-sectional shape;

a tunneling oxide layer formed on the surface and the sidewall of the substrate;

the floating gate layer is formed on one side, away from the substrate, of the tunneling oxide layer and covers the tunneling oxide layer, the concave part and the isolation structure;

a gate formed between the floating gate layer and the tunneling oxide layer, the gate including a plurality of current tunneling channel control surfaces.

In an embodiment of the present invention, an outline of the intersection of the concave portion and the substrate side wall is the inclined straight sectional shape.

In an embodiment of the present invention, an outline of the intersection of the concave portion and the sidewall of the isolation structure is the arc-shaped curved section shape.

In an embodiment of the present invention, the current tunneling channel control surface includes a surface formed by an upper surface of the substrate and sidewalls of two inclined linear cross-sectional shapes of the substrate.

In an embodiment of the present invention, the memory structure further includes a control gate layer formed on a side of the floating gate layer away from the substrate.

In an embodiment of the present invention, the memory structure further includes a dielectric layer formed on one side of the floating gate layer away from the substrate and located between the floating gate layer and the control gate layer.

In one embodiment of the present invention, the dielectric layer includes a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

In one embodiment of the present invention, the floating gate layer comprises polysilicon.

In an embodiment of the present invention, the isolation structure is an inverted trapezoid.

In one embodiment of the present invention, the tunneling oxide layer comprises silicon oxide.

The utility model discloses form the grid gate structure that has a plurality of electric current tunneling passageway control surfaces in nonvolatile memory structure, the grid gate passes through a plurality of electric current tunneling passageway control surfaces, can effectually increase the controllability of grid to electric current tunneling passageway, has reduced the electric leakage. In addition, the gate structure with a plurality of current tunneling channel control surfaces can increase the width of an effective current tunneling channel, so that the saturation current of the nonvolatile memory is improved, and the charge acquisition capacity is improved in practical application. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Of course, it is not necessary for any particular product to achieve all of the above-described advantages at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic diagram of a non-volatile memory structure according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for fabricating a non-volatile memory structure according to another embodiment of the present invention;

fig. 3-6 are schematic structural diagrams corresponding to step S2 in fig. 2;

fig. 7 is a schematic structural diagram corresponding to step S3 in fig. 2;

fig. 8 is a schematic structural diagram corresponding to step S4 in fig. 2;

fig. 9 is a schematic structural diagram corresponding to step S5 in fig. 2;

FIG. 10 is a schematic structural diagram corresponding to the steps S6-S7 in FIG. 2;

fig. 11-17 are schematic structural diagrams corresponding to a method for manufacturing a non-volatile memory structure according to another embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

Referring to fig. 1, the present invention provides a non-volatile memory structure, which in one embodiment may include a plurality of memory cells, each memory cell including a substrate 100, a source 200, a drain 300, and a gate 400 structure between the source/drain 300, wherein the substrate 100 may include, but is not limited to, a single crystal or polycrystalline semiconductor material, and the substrate 100 may further include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, which may be a P-type substrate or an N-type substrate, and in this embodiment, only the first doping type is a P-type substrate, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material. On the substrate 100, through technologies such as chemical vapor deposition, physical vapor deposition, photoetching and form grid 400 structure on substrate 100, the rethread ion implantation is in the both sides of grid 400 structure form source/drain electrode respectively, thereby obtain memory cell connects a plurality of memory cell and obtains the utility model discloses a nonvolatile memory in an embodiment of the utility model, a plurality of memory cell can form on a substrate 100 simultaneously.

Referring to fig. 1, in one embodiment of the present invention, the following process steps may be considered to have been completed on a substrate 100, but are not limited to: a well implant is performed on the substrate 100 in a region corresponding to the memory cell. In addition, only one complete gate 400 structure and two adjacent partial gate 400 structures are shown, but it should be understood by those skilled in the art that the devices and structures of the memory partial memory cell region are shown in the schematic diagram form only in order to clearly express the core idea of the present application, but this does not represent that the memory process related to the present invention only includes these parts, and well-known memory structures and process steps can also be included therein.

Referring to fig. 1, the gate 400 in this embodiment may be a stacked gate structure, and specifically includes a tunnel oxide layer 410, a floating gate layer 411, and a control gate layer 417 sequentially stacked on the surface of the substrate 100, where the control gate layer 417 and the floating gate layer 411 may be made of polysilicon, and data can be written and erased by a tunneling effect. A gate may be further disposed between the tunnel oxide layer 410 and the floating gate layer 411 to control a tunnel current path from the floating gate layer 411 to the substrate 100, and if the number of the gate gates is increased, the control force for the tunnel current path from the floating gate layer 411 to the substrate 100 is stronger, thereby reducing the leakage. In some embodiments, the structure of the non-volatile memory may further include a dielectric layer 419, the dielectric layer 419 being formed between the floating gate layer 411 and the control gate layer 417, the dielectric layer 419 separating the control gate layer 417 from the floating gate layer 411 without direct electrical connection.

Referring to fig. 1, in the structure of the non-volatile memory of the present embodiment, the floating gate layer 411 is electrically isolated, so that electrons reaching the gate 400 are captured even after the voltage is removed, which is the principle of the non-volatility of the non-volatile memory. The threshold voltage of the nonvolatile memory structure in this embodiment depends on the amount of charge stored in the floating gate layer 411, and the more the charge, the higher the threshold voltage. When the voltage applied to the control gate layer 417 is higher than the threshold voltage, the nonvolatile memory structure starts to be turned on. Thus, by measuring its threshold voltage and comparing it to a fixed voltage level to identify the information stored in the non-volatile memory structure, referred to as a read operation of the non-volatile memory structure, electrons can be placed in the floating gate layer 411 using fowler-nordheim tunneling, for which a strong electric field is applied between the negatively charged source 200 and the positively charged control gate layer 417, which causes electrons from the source 200 to tunnel through the tunnel oxide layer 410 and to the floating gate layer 411, the voltage required for tunneling depending on the thickness of the tunnel oxide layer. By applying a strong negative voltage on the control gate layer 417 and a strong positive voltage on the source 200 and drain 300 terminals, electrons can be removed from the floating gate layer 411 using fowler-nordheim tunneling, which will cause the trapped electrons to return to the tunnel through the tunnel oxide layer 410. In a non-volatile memory structure, placing electrons in the floating gate layer 411 is considered a program/write operation, and removing electrons is considered an erase operation.

Referring to fig. 17, in another embodiment of the present invention, the nonvolatile memory includes a plurality of memory cells, each of the memory cells includes: the semiconductor device includes a substrate 100, at least two isolation structures 500, a recess 600, a tunnel oxide layer 410, a floating gate layer 411, and a gate 700.

Referring to fig. 17, the memory cell substrate 100 material may include, but is not limited to, single crystal or polycrystalline semiconductor material, and the substrate 100 may also include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, which may be a P-type substrate or an N-type substrate, and in this embodiment, only the first doping type is a P-type substrate, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.

Referring to fig. 17, at least two isolation structures 500, one end of each isolation structure 500 extends into the substrate 100, in some embodiments, a plurality of isolation structures 500 may be further formed in the nonvolatile memory, the nonvolatile memory is divided into a plurality of memory cells by the plurality of isolation structures 500, and the plurality of memory cells may be distributed in parallel at intervals or may be randomly arranged according to a semiconductor structure. In this embodiment, the adjacent isolation structures 500 and the region of the substrate 100 therebetween form a high voltage device memory cell region or a low voltage device memory cell region.

Referring to fig. 17, in the present embodiment, the isolation structure 500 is, for example, a shallow trench isolation structure 500, the isolation structure 500 is an inverted trapezoid, and since the isolation structure 500 is an inverted trapezoid structure and one end of the isolation structure 500 extends into the substrate 100, an inclined sidewall is formed at a joint of the substrate 100 and the isolation structure 500, a material used for the isolation structure 500 may be, for example, silicon oxide, silicon nitride or silicon oxynitride, and a width of the isolation structure 500 may be set according to design requirements of a semiconductor structure.

Referring to fig. 17, a recess 600 is formed between two sidewalls of the isolation structure 500 and the adjacent sidewall of the substrate 100, a part of the contour of the recess 600 is in a shape of an inclined straight line cross section, another part of the contour of the recess 600 is in a shape of an arc-shaped curved cross section, specifically, a part of the contour of the recess 600 intersecting the sidewall of the substrate 100 is in a shape of an inclined straight line cross section, and a part of the contour of the recess 600 intersecting the sidewall of the isolation structure 500 is in a shape of an arc-shaped curved cross section.

Referring to fig. 17, a tunnel oxide layer 410 is formed on one side of the substrate 100, the tunnel oxide layer 410 covers the surface of the substrate 100 and the sidewall of the substrate 100, the tunnel oxide layer 410 may be made of silicon oxide, for example, in the present embodiment, the tunnel oxide layer 410 made of silicon oxide may be formed by furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods.

Referring to fig. 17, a floating gate layer 411 is formed on a side of the tunnel oxide layer 410 away from the substrate 100, the floating gate layer 411 covers the tunnel oxide layer 410, the recess 600 and the isolation structure 500, the floating gate layer 411 may be made of doped polysilicon, or polysilicon may be deposited in an undoped form, and then implanted to form doped polysilicon. In other embodiments, other suitable conductive materials may be used in place of doped polysilicon.

Referring to fig. 17, a gate 700 is formed between the floating gate layer 411 and the tunnel oxide layer 410, wherein the gate 700 includes a plurality of current tunneling control surfaces, for example, three current tunneling control surfaces in the present embodiment, and the three current tunneling control surfaces include the upper surface of the substrate 100 and the surfaces formed by the sidewalls of the substrate 100 with the inclined linear cross-section shapes at the two sides. The gate 700 can control the charges that enter the floating gate from the tunnel oxide layer 410, and as the number of gate gates 700 increases, the control force for the current tunneling path from the floating gate layer 411 to the substrate 100 is stronger. The utility model discloses the effectual quantity that increases grid gate 700 of concave part 600 that forms between well isolation structure 500 lateral wall and the both sides substrate 100 lateral wall for grid gate 700 further strengthens the controllability of electric current tunneling passageway. In addition, the three-sided gate 700 structure can increase the width of an effective current tunneling channel, so that the saturation current of the nonvolatile memory is improved, and the charge acquisition capacity is improved in practical application. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Referring to fig. 17, each individual floating gate layer 411 is electrically isolated from the substrate 100 by a tunnel oxide layer 410, such electrical isolation allows the floating gate layer 411 to function as a charge storage unit, the tunnel oxide layer 410 allows charge to enter the floating gate layer 411 under certain conditions, the charge level in the floating gate layer 411 can correspond to a logic level, and thus data can be stored in the memory cell. A gate 700 is disposed between the tunnel oxide layer 410 and the floating gate layer 411, so that the current tunneling channel from the tunnel oxide layer 410 to the floating gate can be controlled, and the control force of the current tunneling channel from the floating gate layer 411 to the substrate 100 is stronger when the number of the gate gates 700 is increased. The utility model discloses the effectual quantity that has increased gate 700 of concave part 600 that forms between isolation structure 500 lateral wall and substrate 100 lateral wall for gate 700 further strengthens the controllability of electric current tunneling passageway, for example, forms the gate 700 structure that has three electric current tunneling passageway control surface and can increase the width of effective current tunneling passageway, thereby has improved the saturation current of nonvolatile memory, in practical application, has increased the acquireability to the electric charge. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Referring to fig. 17, in another embodiment of the present invention, the structure of the non-volatile memory may further include a control gate layer 417, the control gate layer 417 is formed on a side of the floating gate layer 411 facing away from the substrate 100, the control gate layer 417 may be a conductive gate 400 formed of doped polysilicon, electrons may be removed from the floating gate layer 411 using fowler-nordheim tunneling by applying a strong negative voltage on the control gate layer 417 and a strong positive voltage on the source 200 and drain 300 terminals, which will cause electrons trapped in the floating gate layer 411 to return to the tunnel through the tunnel oxide layer 410, and this process of removing electrons is considered as an operation of erasing the non-volatile memory.

Referring to fig. 1 and 17, in another embodiment of the present invention, the structure of the non-volatile memory may further include a dielectric layer 419, the dielectric layer 419 is formed between the floating gate layer 411 and the control gate layer 417, the dielectric layer 419 separates the control gate layer 417 from the floating gate layer 411 and cannot be directly electrically connected to the floating gate layer, the dielectric layer 419 may include a silicon oxide layer and a silicon nitride layer sequentially formed on the surface of the floating gate layer 411, wherein the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide, specifically, the silicon oxide layer covers the exposed surfaces of the floating gate layer 411 and the isolation structure 500, and the silicon nitride layer is stacked on the surface of the silicon oxide layer. In some embodiments, the dielectric layer 419 may further include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 sequentially formed on the surface of the floating gate layer 411. In this embodiment, the silicon oxide layer and the silicon nitride layer 413 may be formed by a chemical vapor deposition process. In this embodiment, the thickness of each layer of the dielectric layer may be set by using the existing process, and specifically, may include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414, which are formed on the surface of the floating gate layer 411 in sequence and have a conventional thickness.

Referring to fig. 2, the present invention provides a method for manufacturing a non-volatile memory, which at least includes the following steps:

s1, providing a substrate 100;

s2, forming at least two isolation structures 500 on the substrate 100, wherein one end of each isolation structure 500 extends into the substrate 100 and exposes the side wall of the substrate 100;

s3, forming a patterned light resistance layer on the isolation structure 500;

s4, using the patterned photoresist layer as a mask, carrying out dry etching on the part except the part shielded by the patterned photoresist layer, and forming a concave part 600 between the side wall of the isolation structure 500 and the side wall of the substrate 100, wherein part of the contour line of the concave part 600 is in an inclined straight line section shape, and part of the contour line of the concave part 600 is in an arc curve section shape;

s5, forming a tunneling oxide layer 410 on the surface of the substrate 100 and the side wall of the substrate 100;

s6, forming a floating gate layer 411 on one side of the tunneling oxide layer 410, which is far away from the substrate 100, wherein the floating gate layer 411 covers the tunneling oxide layer 410, the concave part 600 and the isolation structure 500;

and S7, forming a gate 700 between the floating gate layer 411 and the tunneling oxide layer 410, wherein the gate 700 comprises a plurality of current tunneling channel control surfaces.

The following describes the method for manufacturing the non-volatile memory according to the present invention in detail with reference to fig. 2 to 17.

Referring to fig. 2, in the present embodiment, for preparing a memory cell as an example, specifically, in step S1, a substrate 100 is first provided, the material of the substrate 100 may include, but is not limited to, a single crystal or polycrystalline semiconductor material, and the substrate 100 may further include an intrinsic single crystal silicon substrate 100 or a doped silicon substrate 100. The substrate 100 includes a substrate 100 of a first doping type, which may be a P-type substrate or an N-type substrate, and in this embodiment, only the first doping type is a P-type substrate, that is, in this embodiment, the substrate 100 only exemplifies a P-type substrate 100, for example, a P-type silicon substrate 100. In some embodiments, the substrate 100 may also be a single crystal silicon substrate 100, a Ge substrate 100, a SiGe substrate 100, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the substrate 100 according to the actual requirements of the device, which is not limited herein. In some embodiments, the substrate 100 may also be composed of a compound semiconductor material, such as a III-V semiconductor material or a II-VI semiconductor material.

Referring to fig. 3, in step S2, a pad oxide layer 401 is formed on one side of the substrate 100, the pad oxide layer 401 may be made of, for example, silicon oxide or silicon oxynitride, and the pad oxide layer 401 may be formed by, for example, furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods, and a nitridation process may be performed on the silicon oxide to form silicon oxynitride, wherein the nitridation process may be a high temperature nitridation furnace, rapid thermal annealing nitridation, plasma nitridation or other nitridation processes.

Referring to fig. 3, in step S2, a barrier layer 402 is formed on a side of the pad oxide layer 401 away from the substrate 100, the pad oxide layer 401 is used for reducing stress between the substrate 100 and the barrier layer 402, and the barrier layer 402 is used for protecting an active region in a subsequent etching process, in this embodiment, the barrier layer 402 may be made of, for example, silicon nitride, and the barrier layer 402 may be formed by, for example, a chemical vapor deposition technique, which may be a low pressure chemical vapor deposition method or a plasma enhanced chemical vapor deposition method.

Referring to fig. 3, in other embodiments, the carbon layer 403 and/or the antireflective layer 404 may also be formed on the barrier layer 402 by physical vapor deposition or chemical vapor deposition.

Referring to fig. 4 to 6, in step S2, at least two isolation structures 500 are formed on the substrate 100, the two isolation structures 500 are used to separate the adjacent gate structures 400 formed later, and the isolation structures 500 may be, for example, shallow trench isolation structures 500. In some embodiments, a plurality of isolation structures 500 may also be formed in the substrate 100, the plurality of isolation structures 500 divides the substrate 100 into a plurality of regions, and the plurality of regions may be distributed in parallel at intervals, or may be arbitrarily arranged according to the semiconductor structure. In this embodiment, the region of the substrate 100 between adjacent isolation structures 500 constitutes a high voltage device region or a low voltage device region.

Referring to fig. 4 to fig. 6, in step S2, in the present embodiment, the isolation structure 500 includes: a first patterned photoresist layer 405 is formed on the barrier layer 402, wherein the first patterned photoresist layer 405 exposes a portion of the barrier layer 402, and the locations of the isolation structures 500 are defined by the first patterned photoresist layer 405. In this embodiment, for example, the barrier layer 402 and the pad oxide layer 401 may be sequentially etched by using a reactive ion etching or plasma etching process to expose a surface material of the substrate 100, and then the substrate 100 may be etched by using a fluorine-containing etching gas and using the barrier layer 402 and the pad oxide layer 401 as masks, so as to form the first trench 501 extending into the substrate 100.

Referring to fig. 4 to 6, in step S2, in some embodiments, a photoresist layer may be formed on the barrier layer 402, for example, by a spin-coating method, an opening is formed in the photoresist layer through exposure and development processes, a first patterned photoresist layer 405 is obtained, and the barrier layer 402 and the pad oxide layer 401 under the opening pattern are removed by using the first patterned photoresist layer 405 as a mask until the substrate 100 is exposed. Then, the photoresist layer may be removed by ashing, and the substrate 100 is etched by dry etching using the barrier layer 402 and the pad oxide layer 401 as masks, thereby forming the first trench 501. The first trench 501 penetrates through the pad oxide layer 401 and the barrier layer 402 and extends into the substrate 100, and in some embodiments, an antireflection layer 404 may be further disposed on the barrier layer 402, so that the first trench 501 forms an inverted trapezoid shape during etching through an antireflection effect of the antireflection layer 404 on an etching beam. The first trench 501 region will form an isolation structure 500 in the subsequent manufacturing process, one end of the isolation structure 500 extends into the substrate 100, and the substrate 100 covered by the barrier layer 402 and the pad oxide layer 401 is used as an active region for forming a semiconductor device.

Referring to fig. 4 to 6, in step S2, the specific steps of obtaining the isolation structure 500 include: first, a first oxide layer 406 is formed on the bottom surface and the sidewall of the first trench 501 by a chemical vapor deposition method, then an insulating material is deposited on the first oxide layer 406 and the barrier layer 402 by a high density plasma chemical vapor deposition method to fill the first trench 501, and then the upper surface of the insulating material in the first trench 501 is leveled with the upper surface of the barrier layer 402 by, for example, a chemical mechanical polishing method, so as to form the isolation structure 500. In the present embodiment, the material of the first oxide layer 406 may be, for example, silicon oxide or silicon oxynitride, the insulating material may be, for example, silicon oxide, silicon nitride or silicon oxynitride, and the width of the isolation structure 500 may be set according to the design requirements of the semiconductor structure.

Referring to fig. 4 to 6, in step S3 and step S4, the barrier layer 402 is removed by dry etching or wet etching to expose the pad oxide layer 401, in this embodiment, the barrier layer 402 is removed by wet etching, for example, using phosphoric acid or hydrofluoric acid as a reagent for wet etching.

Referring to fig. 4 to 6, in steps S3 and S4, after the barrier layer 402 is removed, an ion implantation is performed on a region of the substrate 100 between adjacent isolation structures 500, for example, a P-well 407 or an N-well 408 is formed in the corresponding region of the substrate 100, and the ion implantation source is preferably a phosphorus source, a boron source or a fluorine source.

Referring to fig. 7 to 8, in steps S3 and S4, the step of forming a recess 600 between the sidewall of the isolation structure 500 and the sidewall of the substrate 100 includes: first, a second patterned photoresist layer 409 is formed on the upper surface of the isolation structure 500, the second patterned photoresist layer 409 exposes a portion of the upper surface of the isolation structure 500, and the second patterned photoresist layer 409 defines the position of the recess 600. In this embodiment, the second patterned photoresist layer 409 may be obtained by the same method for obtaining the first patterned photoresist layer 405, which is not described herein again. In this embodiment, for example, a reactive ion etching or plasma etching process may be used to perform etching, that is, the pad oxide layer 401 is first removed by the reactive ion etching or plasma etching process, and meanwhile, a dry etching is performed on the portion of the upper surface of the isolation structure 500 except the portion blocked by the second patterned photoresist layer 409 to perform a downward etching, so that arc-shaped sidewalls are formed on both sides of the isolation structure 500 and the sidewalls of the substrate 100 are exposed. In this embodiment, the isolation structure 500 is made of, for example, silicon dioxide, the substrate 100 is made of, for example, silicon, and the dry etching is, for example, a plasma etching method, since the plasma etching of silicon dioxide can be performed by using a gas containing a fluorocarbon, the etching gas used can be carbon tetrafluoride (CF4), octafluoropropane, or trifluoromethane, and the like, in this embodiment, carbon tetrafluoride is taken as an example of the etching gas, wherein a reaction rate of fluorine atoms and silicon is very fast, for example, 10 to 1000 times that of silicon dioxide, and a higher etching selectivity ratio of silicon dioxide to silicon can be obtained. It is believed that the higher the proportion of carbon atoms in the fluorocarbon gas, the more polymer formed, which results in a high etch selectivity ratio, and in some embodiments, the silicon dioxide to silicon etch selectivity ratio may be increased by increasing the silicon source, such as silicon tetrafluoride, to increase the fluorine atoms to change the fluorine to carbon atomic ratio. In some embodiments, oxygen may be added to the reaction gas, for example, at a concentration of 20% to 40%, and the oxygen reacts with the fluorocarbon to release fluorine atoms and consume a portion of the carbon, thereby changing the atomic ratio of fluorine to carbon, so as to increase the etching selectivity of silicon dioxide to silicon, but when the oxygen concentration is greater than 40%, the etching selectivity decreases. In some embodiments, hydrogen may be added to the etching gas to reduce the etching rate of silicon, and when the concentration of hydrogen is, for example, 40%, the etching rate of silicon is approximately equal to 0, which may be considered as etching only silicon dioxide but not silicon.

Referring to fig. 7 to 8, in steps S3 and S4, the second patterned photoresist layer 409 is removed after the recess 600 is formed, and the method used may be the same as the method for removing the first patterned photoresist layer 405, which is not described herein again.

Referring to fig. 9, in step S5, a tunnel oxide layer 410 is formed on the exposed surface of the substrate 100 and the sidewalls of the substrate 100 located in the recesses 600 at two sides, the tunnel oxide layer 410 may be made of silicon oxide, and in the present embodiment, the tunnel oxide layer 410 made of silicon oxide may be formed by, for example, furnace oxidation, rapid thermal annealing oxidation, in-situ steam oxidation or other thermal oxidation methods.

Referring to fig. 10, in step S6, a floating gate layer 411 is formed on a side of the tunnel oxide layer 410 away from the substrate 100, wherein the floating gate layer 411 may be made of doped polysilicon, or polysilicon may be deposited in an undoped form, and then implanted to form doped polysilicon. In other embodiments, other suitable conductive materials may be used in place of doped polysilicon.

Referring to fig. 10 and 11, in step S6, the specific step of forming the floating gate layer 411 on the tunnel oxide layer 410 includes: and depositing polysilicon on the surface of the tunneling oxide layer 410, the surface of the recess 600 and the surface of the isolation structure 500, and planarizing the deposited polysilicon until the surface of the isolation structure 500 is exposed, thereby obtaining the floating gate layer 411. The deposition and planarization processes described above are preferably performed using techniques conventional in the art, such as chemical mechanical planarization to planarize the polysilicon. In this embodiment, the floating gate layer 411 is used to store charges to set the threshold voltage characteristics of the memory cell, wherein the thermally induced grain size growth of the poly structure is reduced and the threshold voltage characteristics of the gate 400 structure are maintained by interacting with the poly structure through an impurity layer, such as impurities implanted into the poly structure of the poly floating gate.

Referring to fig. 10 and 11, in step S7, a gate 700 is formed between the floating gate layer 411 and the tunnel oxide layer 410, wherein the gate 700 includes a plurality of current tunneling control surfaces, for example, three current tunneling control surfaces in the present embodiment, and the three current tunneling control surfaces include the upper surface of the substrate 100 and the surfaces formed by the inclined linear sidewalls of the two sides of the substrate 100. The gate 700 can control the current tunneling path from the tunneling oxide layer 410 to the floating gate, and the greater the number of gate gates 700, the stronger the control force for the current tunneling path from the floating gate layer 411 to the substrate 100. The utility model discloses the effectual quantity that has increased grid gate 700 of concave part 600 that forms between well isolation structure 500 lateral wall and the both sides substrate 100 lateral wall for grid gate 700 further strengthens the controllability of electric current tunneling passageway, has the grid gate 700 structure of a plurality of electric current tunneling passageway control faces in addition, can increase the width of effective current tunneling passageway, thereby has improved the saturation current of non-volatile memory, in practical application, has increased the acquireability to the electric charge. Due to the increase of the width of the effective current tunneling channel, the device can be miniaturized to a certain extent in the horizontal direction while the original performance is kept, so that the device achieves a higher integration level.

Referring to fig. 12, in another embodiment, a dielectric layer 419 may be further formed on a side of the floating gate layer 411 away from the tunnel oxide layer 410, the dielectric layer 419 covers the exposed surfaces of the floating gate layer 411 and the isolation structure 500, the dielectric layer 419 may include a silicon oxide layer and a silicon nitride layer 413 sequentially formed on the surface of the floating gate layer 411, where the silicon oxide layer may be, for example, silicon oxynitride or silicon dioxide, specifically, the silicon oxide layer covers the exposed surfaces of the floating gate layer 411 and the isolation structure 500, and the silicon nitride layer 413 is formed on the surface of the silicon oxide layer in an overlapping manner. In some embodiments, the dielectric layer 419 may further include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414 sequentially formed on the surface of the floating gate layer 411. In this embodiment, the silicon oxide layer and the silicon nitride layer 413 may be formed by a chemical vapor deposition process. In this embodiment, the thickness of each layer of the dielectric layer 419 may be set by using the existing process, and specifically, may include a first silicon oxide layer 412, a silicon nitride layer 413, and a second silicon oxide layer 414, which are sequentially formed on the surface of the floating gate layer 411 and have a conventional thickness.

Referring to fig. 13 and 14, in some embodiments, a third patterned photoresist layer 415 is formed on a side of the dielectric layer 419 away from the floating gate layer 411, the third patterned photoresist layer 415 exposes a surface of the dielectric layer 419 corresponding to the first trench 501, and the position of the second trench 416 is defined by the third patterned photoresist layer 415. In this embodiment, the etching process may be performed, for example, by using a reactive ion etching or plasma etching process, that is, the etching process is performed downwards along the surface of the dielectric layer 419 except the portion shielded by the third patterned photoresist layer 415 through the reactive ion etching or plasma etching process until the etching is stopped when the upper surface of the isolation structure 500 is exposed, so as to form the second trench 416 penetrating through the dielectric layer 419 in the dielectric layer 419. The width of the second trench 416 may be equal to the width of the upper surface of the isolation structure 500, and in other embodiments, the width of the second trench 416 may be greater than the width of the upper surface of the isolation structure 500. After forming the second trench 416, the third patterned photoresist layer 415 is removed by a method similar to that of the first patterned photoresist layer 405, which is not described herein again.

Referring to fig. 15, in another embodiment, a control gate layer 417 is formed on a side of the dielectric layer 419 away from the floating gate layer 411, and the control gate layer 417 covers the dielectric layer 419 and fills the second trench 416. Dielectric layer 419 separates control gate layer 417 from floating gate layer 411 from direct electrical connection. Each individual floating gate layer 411 is electrically isolated from the substrate 100 by a tunnel oxide layer 410, which allows the floating gate layer 411 to act as a charge storage cell, the tunnel oxide layer 410 allowing charge to enter the floating gate under certain conditions, the charge level in the floating gate may correspond to a logic level, and thus data may be stored in the cell. A gate 700 is disposed between the tunnel oxide layer 410 and the floating gate layer 411 to control charges entering the floating gate from the tunnel oxide layer 410, and the control force of the tunnel charges from the floating gate layer 411 to the substrate 100 is stronger when the number of the gate gates 700 is increased. The utility model discloses the effectual length that increases gate 700 of concave part 600 that forms between isolation structure 500 lateral wall and substrate 100 lateral wall for gate 700 further strengthens tunneling charge's controllability.

Referring to fig. 16 and fig. 17, a fourth patterned photoresist layer 418 is formed on a side of the control gate layer 417 away from the dielectric layer 419, the fourth patterned photoresist layer 418 exposes a surface of the control gate layer 417 corresponding to the second trench 416, in this embodiment, a reactive ion etching or plasma etching process may be used to etch the fourth patterned photoresist layer 417, that is, the reactive ion etching or plasma etching process etches the fourth patterned photoresist layer 417 downward along the surface of the control gate layer 417 except the portion shielded by the fourth patterned photoresist layer 418, and after the etching process penetrates through the control gate layer 417, the material of the control gate layer 417 filled in the second trench 416 is etched together until the upper surface of the isolation structure 500 is exposed, so as to obtain the memory cell of the present invention, and then obtain the nonvolatile memory of the present invention.

The selected embodiments of the present invention disclosed above are merely provided to help illustrate the present invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A non-volatile memory structure, comprising:

a substrate;

at least two isolation structures, one end of each isolation structure extending into the substrate;

a recess formed between each of the isolation structure sidewalls and an adjacent substrate sidewall, a portion of the recess having an inclined straight-line cross-sectional shape and another portion of the recess having an arcuate curved cross-sectional shape;

a tunneling oxide layer formed on the surface and the sidewall of the substrate;

the floating gate layer is formed on one side, away from the substrate, of the tunneling oxide layer and covers the tunneling oxide layer, the concave part and the isolation structure;

a gate formed between the floating gate layer and the tunneling oxide layer, the gate including a plurality of current tunneling channel control surfaces.

2. The structure of claim 1, wherein a contour line of the recess intersecting the substrate sidewall is in the shape of the inclined straight-line cross-section.

3. The structure of claim 1, wherein a contour line of the recess intersecting the sidewall of the isolation structure has the shape of the curved cross-section.

4. The structure of claim 1, wherein the current tunneling channel control surface comprises a top surface of the substrate and a surface formed by two side walls of the substrate with an inclined straight-line cross-sectional shape.

5. The structure of claim 1, further comprising a control gate layer formed on a side of the floating gate layer facing away from the substrate.

6. The structure of claim 5, further comprising a dielectric layer formed between the floating gate layer and the control gate layer on a side of the floating gate layer facing away from the substrate.

7. The structure of claim 6, wherein the dielectric layer comprises a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

8. The structure of claim 1, wherein the floating gate layer comprises polysilicon.

9. The structure of claim 1, wherein the isolation structure has an inverted trapezoid shape.

10. The structure of claim 1, wherein the tunneling oxide layer comprises silicon oxide.

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