CN211427341U

CN211427341U - Data destruction circuit

Info

Publication number: CN211427341U
Application number: CN202020089111.5U
Authority: CN
Inventors: 李华
Original assignee: Hefei Zhuoyi Hengtong Information Security Co Ltd
Current assignee: Hefei Zhuoyi Hengtong Information Security Co Ltd
Priority date: 2020-01-14
Filing date: 2020-01-14
Publication date: 2020-09-04
Anticipated expiration: 2030-01-14

Abstract

The utility model provides a data destruction circuit. The data destruction circuit is applied to data storage equipment and comprises: the device comprises a key triggering module, an enabling signal generating module electrically connected with the key triggering module, a destroying signal generating module electrically connected with the enabling signal generating module and a destroying module electrically connected with the destroying signal generating module; the key trigger module comprises a key switch and is used for outputting a first trigger signal to the enabling signal generating module under the control of the key switch; the enabling signal generating module is used for outputting an enabling signal to the destroying signal generating module under the control of the first triggering signal; the destruction signal generation module is used for outputting a destruction signal to the destruction module under the control of the enabling signal; the destroying module is used for destroying the data in the data storage device under the control of the destroying signal. The utility model discloses can simplify the complexity of data destruction circuit, reduce the cost of data destruction circuit, promote the control flexibility of data destruction circuit.

Description

Data destruction circuit

Technical Field

The utility model relates to a computer technology field especially relates to a data destruction circuit.

Background

With the development of science and technology, computer devices such as notebook computers and all-in-one computers have been widely popularized and widely applied in various fields, and users can use the computer devices to store, transmit and process data.

Meanwhile, as the awareness of users on network security, system data security and personal information security is increased, the data security requirements of users on computer devices are higher and higher, and therefore, encryption chips and encryption systems are embedded in many computer products provided for users at present to meet the requirements of users on data security.

At present, unsafe factors of the network are increased, for example, hacker intruders steal important data contents of users through a network remote intrusion system by means of system bugs, supervision incapability and the like, or equipment is infected with viruses to cause data leakage and cause great economic loss. Security of data becomes increasingly important.

The demand of specific customer groups on encryption type data storage processing equipment (such as encryption type computers and tablet equipment) is becoming obvious, and at present, aiming at the encryption type data storage processing equipment, on one hand, an encryption chip and an encryption system are implanted to encrypt a data communication link so as to prevent data from being stolen in a transmission process, and on the other hand, complete substrate destruction on the data stored in the encryption type data storage processing equipment under a specific scene is realized so as to ensure that the data cannot be copied.

In the prior art, a data destruction circuit in an encryption type data storage device is designed by adopting a microcontroller, so that the circuit cost is high, and a large amount of wiring area of a Printed Circuit Board (PCB) is occupied; meanwhile, the data destruction circuit designed by the microcontroller also needs to be programmed to realize the software function, so that the design cost is high; furthermore, the data destruction circuit designed by the microcontroller has high power consumption and can have certain influence on battery endurance; the circuit is complex and the stability of the procedure is also compromised.

Therefore, a new data destruction circuit is needed, which can simplify the complexity of the data destruction circuit, reduce the cost of the data destruction circuit, and improve the control flexibility of the data destruction circuit.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a data destruction circuit can simplify data destruction circuit's complexity, reduces data destruction circuit's cost, promotes data destruction circuit's control flexibility.

In order to achieve the above object, the utility model provides a data destruction circuit is applied to data storage device, include: the device comprises a key triggering module, an enabling signal generating module electrically connected with the key triggering module, a destroying signal generating module electrically connected with the enabling signal generating module and a destroying module electrically connected with the destroying signal generating module;

the key trigger module comprises a key switch and is used for outputting a first trigger signal to the enabling signal generating module under the control of the key switch;

the enabling signal generating module is used for receiving a first triggering signal and outputting an enabling signal to the destroying signal generating module under the control of the first triggering signal;

the destruction signal generation module is used for receiving an enabling signal and outputting a destruction signal to the destruction module under the control of the enabling signal;

the destruction module is used for receiving a destruction signal and destroying the data in the data storage device under the control of the destruction signal.

The enable signal generation module includes: the circuit comprises a first resistor, a second resistor, a first capacitor, a second capacitor and a first MOS (metal oxide semiconductor) tube;

one end of the first resistor receives power supply voltage, and the other end of the first resistor is electrically connected with the source electrode of the first MOS tube;

one end of the second resistor outputs an enable signal, and the other end of the second resistor is grounded;

one end of the first capacitor is electrically connected with the drain electrode of the first MOS tube, and the other end of the first capacitor is grounded;

one end of the second capacitor is electrically connected with the drain electrode of the first MOS tube, and the other end of the second capacitor is grounded;

the grid electrode of the first MOS tube receives the first trigger signal, and the drain electrode of the first MOS tube is electrically connected with one end of the second resistor.

The key triggering module further comprises: the third resistor, the fourth resistor, the fifth resistor, the sixth resistor, the seventh resistor, the third capacitor, the fourth capacitor and the second MOS tube;

one end of the key switch receives power supply voltage, and the other end of the key switch is electrically connected with one end of the third resistor;

the other end of the third resistor is electrically connected with one end of a fifth resistor;

one end of the fourth resistor is electrically connected with one end of the third resistor, and the other end of the fourth resistor is grounded;

the other end of the fifth resistor is electrically connected with the grid electrode of the second MOS tube;

one end of the sixth resistor is electrically connected with the grid electrode of the second MOS tube, and the other end of the sixth resistor is grounded;

one end of the seventh resistor receives the power supply voltage, and the other end of the seventh resistor is electrically connected with the drain electrode of the second MOS tube;

one end of the third capacitor is electrically connected with one end of the fifth resistor, and the other end of the third capacitor is grounded;

one end of the fourth capacitor is electrically connected with one end of the fifth resistor, and the other end of the fourth capacitor is grounded;

and the source electrode of the second MOS tube is grounded.

The data destruction circuit further comprises: the disassembly triggering module is used for detecting whether the data storage equipment is disassembled and outputting a second triggering signal to the enabling signal generating module when the data storage equipment is disassembled;

the enabling signal generating module is further used for receiving a second triggering signal and outputting an enabling signal to the destroying signal generating module under the control of the second triggering signal.

The trip trigger module comprises: the eighth resistor, the ninth resistor, the fifth capacitor and the double-pin elastic electrode;

one end of the eighth resistor receives power supply voltage, and the other end of the eighth resistor is electrically connected with one pin of the double-pin elastic electrode;

one end of the ninth resistor is electrically connected with the other pin of the double-pin elastic electrode, and the other end of the ninth resistor is grounded;

one end of the fifth capacitor is electrically connected with the other pin of the double-pin elastic electrode, and the other end of the fifth capacitor is grounded;

the other pin of the double-pin elastic electrode outputs a second trigger signal, two pins of the double-pin elastic electrode are arranged on the data storage equipment, are conducted when the data storage equipment is not dismounted and are separated when the data storage equipment is dismounted;

the enable signal generation module further includes: a third MOS transistor and a tenth resistor;

one end of the tenth resistor is electrically connected with the source electrode of the third MOS transistor, and the other end of the tenth resistor receives power supply voltage;

and the grid electrode of the third MOS tube receives a second trigger signal, and the drain electrode of the third MOS tube is electrically connected with one end of the second resistor.

The destruction signal generation module comprises: an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a sixth capacitor, a seventh capacitor, an eighth capacitor and a low dropout regulator;

one end of the eleventh resistor is electrically connected with an output pin of the low dropout regulator, and the other end of the eleventh resistor is electrically connected with one end of the twelfth resistor;

the other end of the twelfth resistor is grounded;

one end of the thirteenth resistor is electrically connected with an output pin of the low dropout linear regulator, and the other end of the thirteenth resistor is grounded;

one end of the fourteenth resistor is electrically connected with an output pin of the low dropout linear regulator, and the other end of the fourteenth resistor outputs a destruction signal to the destruction module;

one end of the sixth capacitor receives power supply voltage, and the other end of the sixth capacitor is grounded;

one end of the seventh capacitor receives power supply voltage, and the other end of the seventh capacitor is grounded;

one end of the eighth capacitor is electrically connected with an output pin of the low dropout linear regulator, and the other end of the eighth capacitor is grounded;

and an input pin of the low dropout linear regulator is electrically connected with one end of the seventh capacitor, the enable pin receives an enable signal, the grounding pin is grounded, and the adjustable voltage pin is electrically connected with the other end of the eleventh resistor.

The first MOS tube is an N-type MOS tube, and the second MOS tube and the third MOS tube are P-type MOS tubes.

The time length of each time of output of the destruction signal is more than 30 seconds.

The data storage device is a computer.

The computer adopts a Loongson processor or a Shenwei processor.

The utility model has the advantages that: the utility model provides a data destruction circuit is applied to data storage equipment, include: the device comprises a key triggering module, an enabling signal generating module electrically connected with the key triggering module, a destroying signal generating module electrically connected with the enabling signal generating module and a destroying module electrically connected with the destroying signal generating module; the key trigger module comprises a key switch and is used for outputting a first trigger signal to the enabling signal generating module under the control of the key switch; the enabling signal generating module is used for receiving a first triggering signal and outputting an enabling signal to the destroying signal generating module under the control of the first triggering signal; the destruction signal generation module is used for receiving an enabling signal and outputting a destruction signal to the destruction module under the control of the enabling signal; the destruction module is used for receiving the destruction signal and destroying the data in the data storage device under the control of the destruction signal, so that the complexity of the data destruction circuit can be simplified, the cost of the data destruction circuit is reduced, and the control flexibility of the data destruction circuit is improved.

Drawings

For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the present invention and accompanying drawings, which are provided for the purpose of illustration and description and are not intended to limit the present invention.

In the drawings, there is shown in the drawings,

fig. 1 is a schematic block diagram of a data destruction circuit according to the present invention;

fig. 2 is a circuit diagram of the data destruction circuit of the present invention.

Detailed Description

To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.

Referring to fig. 1, the present invention provides a data destruction circuit applied to a data storage device, including: the device comprises a key triggering module 10, an enabling signal generating module 20 electrically connected with the key triggering module 10, a destruction signal generating module 30 electrically connected with the enabling signal generating module 20, and a destruction module 40 electrically connected with the destruction signal generating module 30;

the key triggering module 10 includes a key switch K1 for outputting a first triggering signal CF1 to the enabling signal generating module 20 under the control of a key switch K1;

the enable signal generation module 20 is configured to receive a first trigger signal CF1, and output an enable signal EN to the destruction signal generation module 30 under the control of the first trigger signal CF 1;

the destruction signal generation module 30 is configured to receive an enable signal EN and output a destruction signal DES to the destruction module 40 under the control of the enable signal EN;

the destruction module 40 is configured to receive a destruction signal DES, and destroy the data in the data storage device under the control of the destruction signal DES.

Further, in some embodiments of the present invention, the data destruction circuit further comprises: a disassembly trigger module 50, where the disassembly trigger module 50 is configured to detect whether the data storage device is disassembled, and when the data storage device is disassembled, output a second trigger signal CF2 to the enable signal generation module 20;

the enable signal generating module 20 is further configured to receive a second trigger signal CF2, and output an enable signal EN to the destruction signal generating module 30 under the control of the second trigger signal CF 2.

Specifically, the enable signal generating module 20 includes: the circuit comprises a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2 and a first MOS transistor Q1;

one end of the first resistor R1 receives a power voltage VBAT, and the other end is electrically connected to the source of the first MOS transistor Q1;

one end of the second resistor R2 outputs an enable signal EN, and the other end is grounded;

one end of the first capacitor C1 is electrically connected to the drain of the first MOS transistor Q1, and the other end is grounded;

one end of the second capacitor C2 is electrically connected to the drain of the first MOS transistor Q1, and the other end is grounded;

the gate of the first MOS transistor Q1 receives the first trigger signal CF1, and the drain is electrically connected to one end of the second resistor R2.

Specifically, the key triggering module 10 further includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a third capacitor C3, a fourth capacitor C4 and a second MOS transistor Q2;

one end of the key switch K1 receives a power supply voltage VBAT, and the other end of the key switch K1 is electrically connected with one end of a third resistor R3;

the other end of the third resistor R3 is electrically connected with one end of a fifth resistor R5;

one end of the fourth resistor R4 is electrically connected with one end of the third resistor R3, and the other end of the fourth resistor R4 is grounded;

the other end of the fifth resistor R5 is electrically connected with the gate of the second MOS transistor Q2;

one end of the sixth resistor R6 is electrically connected with the gate of the second MOS transistor Q2, and the other end is grounded;

one end of the seventh resistor R7 receives the power voltage VBAT, and the other end is electrically connected to the drain of the second MOS transistor Q2;

one end of the third capacitor C3 is electrically connected to one end of the fifth resistor R5, and the other end is grounded;

one end of the fourth capacitor C4 is electrically connected to one end of the fifth resistor R5, and the other end is grounded;

the source of the second MOS transistor Q2 is grounded.

Specifically, the dismantling trigger module 50 includes: an eighth resistor R8, a ninth resistor R9, a fifth capacitor C5 and a dual-pin elastic electrode X1;

one end of the eighth resistor R8 receives a power voltage VBAT, and the other end of the eighth resistor R8 is electrically connected with one pin of the double-pin elastic electrode X1;

one end of the ninth resistor R9 is electrically connected with the other pin of the double-pin elastic electrode X1, and the other end is grounded;

one end of the fifth capacitor C5 is electrically connected with the other pin of the double-pin elastic electrode X1, and the other end is grounded;

the other pin of the double-pin elastic electrode X1 outputs a second trigger signal CF2, two pins of the double-pin elastic electrode X1 are installed on the data storage device and are conducted when the data storage device is not dismounted, and are separated when the data storage device is dismounted;

the enable signal generating module 20 further includes: a third MOS transistor Q3 and a tenth resistor R10;

one end of the tenth resistor R10 is electrically connected to the source of the third MOS transistor Q3, and the other end receives a power supply voltage VBAT;

the gate of the third MOS transistor Q3 receives the second trigger signal CF2, and the drain is electrically connected to one end of the second resistor R2.

Specifically, the destruction signal generation module 30 includes: an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8 and a low dropout regulator LDO;

one end of the eleventh resistor R11 is electrically connected to an output pin of the low dropout regulator LDO, and the other end of the eleventh resistor R11 is electrically connected to one end of the twelfth resistor R12;

the other end of the twelfth resistor R12 is grounded;

one end of the thirteenth resistor R13 is electrically connected to an output pin of the low dropout regulator LDO, and the other end is grounded;

one end of the fourteenth resistor R14 is electrically connected to an output pin of the low dropout regulator LDO, and the other end outputs a destruction signal DES to the destruction module 40;

one end of the sixth capacitor C6 receives the power voltage VBAT, and the other end is grounded;

one end of the seventh capacitor C7 receives the power voltage VBAT, and the other end is grounded;

one end of the eighth capacitor C8 is electrically connected to an output pin of the low dropout regulator LDO, and the other end is grounded;

an input pin of the low dropout regulator LDO is electrically connected to one end of the seventh capacitor C7, an enable pin receives an enable signal EN, a ground pin is grounded, and an adjustable voltage pin is electrically connected to the other end of the eleventh resistor R11.

The first MOS transistor Q1 is an N-type MOS transistor, and the second MOS transistor Q2 and the third MOS transistor Q3 are P-type MOS transistors.

It should be noted that, the utility model discloses a specific working process of data destruction circuit does: the long-press time duration can be adjusted as required by long-press of the key switch K1, and a typical time duration is, for example, 3 seconds to 5 seconds, the first trigger signal CF1 changes from a high level to a low level, so that the enable signal EN changes from the low level to the high level, so that the high-level destruction signal DES is output to the destruction module 40, the high-level destruction signal DES is maintained for a certain time duration, usually, the time duration of maintaining the high-level destruction signal DES is greater than 30 seconds, the destruction module 40 destroys data in the data storage device when the high-level destruction signal DES is maintained, and after destruction is completed, the circuit returns to an initial state, that is, the first trigger signal CF1, the enable signal EN, and the destruction signal DES are all at the low level.

Further, the utility model discloses a concrete working process of data destruction circuit still includes: two pins of a double-Pin (2Pin) elastic electrode X1 are respectively mounted on a data storage device, specifically, a casing of the data storage device, and when the casing of the data storage device is in a normal mounting position and is not dismounted, the two pins are in a short-circuit state, the second trigger signal CF2 is at a high level, and when the casing of the data storage device is dismounted, the two pins are separated accordingly, the second trigger signal CF2 is changed into a low level, so that the enable signal EN is changed from the low level to the high level, so that the high-level destruction signal DES is output to the destruction module 40, the high-level destruction signal DES is maintained for a certain time, generally, the time for maintaining the high-level destruction signal DES is longer than 30 seconds, and the destruction module 40 destroys data in the data storage device when the high-level destruction signal DES is maintained.

The following combines the utility model discloses a circuit diagram of data destruction circuit explains in detail the utility model discloses a data destruction circuit's working process:

when the key switch K1 is pressed, the power supply voltage VBAT charges the third capacitor C3 and the fourth capacitor C4 through the third resistor R3 via the key switch K1, when the voltages of the third capacitor C3 and the fourth capacitor C4 are charged to about 3.2V, after the voltage division is performed through the fifth resistor R5 and the sixth resistor R6, the voltage of the gate of the second MOS transistor Q2 reaches the turn-on voltage of 1.6V, at this time, the second MOS transistor Q2 is turned on, the drain of the second MOS transistor Q2 is turned low from high, that is, the first trigger signal CF1 is turned low from high, so that the first MOS transistor Q1 is turned on, when the first MOS transistor Q1 is turned on, the first capacitor C1 and the second capacitor C2 are rapidly charged to the power supply voltage vblevel through the first resistor R1, even if the enable signal EN is changed from low level to high level, so that the low-dropout linear regulator starts to operate and outputs a low-dropout regulator, the low-voltage LDO signal is destroyed as a seventh low-drop-out linear regulator 6, the input current of the LDO, the LDO regulator and the third linear regulator 6, the input capacitor C6, the first eleventh resistor R11 and the twelfth resistor R12 are resistors provided for an output voltage of the low dropout regulator LDO, and the voltage value of the output voltage of the low dropout regulator LDO, such as 3.3V or 1.8V, can be adjusted by setting resistance values of the first eleventh resistor R11 and the twelfth resistor R12, the load resistor of the thirteenth resistor R13, and the fourteenth resistor R14 are series resistors.

Further, in the data destruction circuit of the present invention, the resistance value of the third resistor R3, the capacitance values of the third capacitor C3 and the fourth capacitor C4 are adjusted, so that the time for triggering the key switch K1 can be adjusted, for example, the trigger level output can be generated when the key switch K1 presses 3 seconds or 5 seconds, preferably, the embodiment of the present invention is to press 3 seconds.

Furthermore, the holding time of the enable signal EN after the key switch K1 is released can be set by adjusting the capacitance values of the first capacitor C1 and the second capacitor C2 and the resistance value of the second resistor R2, as can be known from the circuit principle, when the key switch K1 is released, the third capacitor C3 and the fourth capacitor C4 discharge to ground through the third resistor R3 and the fourth resistor R4, the second MOS transistor Q2 is turned off, simultaneously first MOS pipe Q1 will also cut off, pass through first electric capacity C1 and second electric capacity C2 this moment and discharge through second resistance R2, the electric potential of enabling signal EN is slowly become low by mains voltage VBAT, increase first electric capacity C1 and second electric capacity C2 or increase first electric capacity C1 and second electric capacity C2 and can increase the hold time of enabling signal EN, the embodiment of the utility model provides an actual measurement enable signal EN's hold time is 38 seconds, destroy signal DES's hold time and enable signal EN's hold time unanimity.

Further, X1 is a 2PIN elastic metal electrode, after the data storage device is installed, the two PINs are pressed on a casing of the data storage device and are kept in a connected state through a short-circuit metal sheet, at this time, the third MOS transistor Q3 is stopped, the enable signal EN is at a low level, the destroy signal DES is at a low level, when the casing is disassembled, the two PINs of X1 are opened, the gate of the third MOS transistor Q3 is grounded through a ninth resistor R9, the third MOS transistor Q3 is conducted, the first capacitor C1 and the second capacitor C2 are charged to a VBAT level through a tenth resistor R10 for current limiting, at this time, the enable signal EN is at a high level, the destroy signal DES is at a high level, and the destroy circuit destroys data in the data storage device.

In particular, the data storage device is a computer, and preferably, the computer adopts a Loongson processor or a Shenwei processor.

It is worth mentioning, the utility model discloses a data destruction circuit supports manual button mode and tears open and cover the compulsory mode and produce and destroy the signal and carry out data destruction, the length is kept with destroying the signal and is adjusted in a flexible way through adjusting the device parameter value when the button is long, whole circuit adopts independent components and parts such as common conventional resistance, electric capacity and MOS pipe, and is with low costs, need not to use complicated chip and programming, and the specific extremely low consumption (electric current uA level) of circuit, do not influence the continuation of the journey of complete machine, it can maintain certain time (not less than 30 seconds) and be used for making and enable to destroy module work and destroy data, can close signal output by oneself after maintaining the certain time, and can repeatedly trigger, can extensively be used for in the recreation notebook of encryption type, the official working book, among the data storage facilities such as panel computer.

To sum up, the utility model provides a data destruction circuit is applied to data storage equipment, include: the device comprises a key triggering module, an enabling signal generating module electrically connected with the key triggering module, a destroying signal generating module electrically connected with the enabling signal generating module and a destroying module electrically connected with the destroying signal generating module; the key trigger module comprises a key switch and is used for outputting a first trigger signal to the enabling signal generating module under the control of the key switch; the enabling signal generating module is used for receiving a first triggering signal and outputting an enabling signal to the destroying signal generating module under the control of the first triggering signal; the destruction signal generation module is used for receiving an enabling signal and outputting a destruction signal to the destruction module under the control of the enabling signal; the destruction module is used for receiving the destruction signal and destroying the data in the data storage device under the control of the destruction signal, so that the complexity of the data destruction circuit can be simplified, the cost of the data destruction circuit is reduced, and the control flexibility of the data destruction circuit is improved.

From the above, it is obvious to those skilled in the art that various other changes and modifications can be made according to the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protection scope of the claims of the present invention.

Claims

1. A data destruction circuit, applied to a data storage device, comprising: the device comprises a key triggering module (10), an enabling signal generating module (20) electrically connected with the key triggering module (10), a destruction signal generating module (30) electrically connected with the enabling signal generating module (20), and a destruction module (40) electrically connected with the destruction signal generating module (30);

the key trigger module (10) comprises a key switch (K1) for outputting a first trigger signal (CF1) to the enable signal generation module (20) under the control of the key switch (K1);

the enabling signal generating module (20) is used for receiving a first trigger signal (CF1) and outputting an enabling signal (EN) to the destruction signal generating module (30) under the control of the first trigger signal (CF 1);

the destruction signal generation module (30) is used for receiving an enable signal (EN) and outputting a destruction signal (DES) to the destruction module (40) under the control of the enable signal (EN);

the destruction module (40) is used for receiving a destruction signal (DES) and destroying data in the data storage device under the control of the destruction signal (DES).

2. The data destruction circuit according to claim 1, wherein the enable signal generating means (20) comprises: the circuit comprises a first resistor (R1), a second resistor (R2), a first capacitor (C1), a second capacitor (C2) and a first MOS transistor (Q1);

one end of the first resistor (R1) receives a power supply Voltage (VBAT), and the other end of the first resistor (R1) is electrically connected with the source electrode of the first MOS transistor (Q1);

one end of the second resistor (R2) outputs an enable signal (EN), and the other end is grounded;

one end of the first capacitor (C1) is electrically connected with the drain electrode of the first MOS transistor (Q1), and the other end of the first capacitor is grounded;

one end of the second capacitor (C2) is electrically connected with the drain electrode of the first MOS tube (Q1), and the other end of the second capacitor is grounded;

the gate of the first MOS transistor (Q1) receives a first trigger signal (CF1), and the drain is electrically connected with one end of a second resistor (R2).

3. A data destruction circuit according to claim 2, characterized in that the key activation module (10) further comprises: the circuit comprises a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), a third capacitor (C3), a fourth capacitor (C4) and a second MOS transistor (Q2);

one end of the key switch (K1) receives a power supply Voltage (VBAT), and the other end of the key switch is electrically connected with one end of a third resistor (R3);

the other end of the third resistor (R3) is electrically connected with one end of a fifth resistor (R5);

one end of the fourth resistor (R4) is electrically connected with one end of the third resistor (R3), and the other end of the fourth resistor (R4) is grounded;

the other end of the fifth resistor (R5) is electrically connected with the grid electrode of the second MOS tube (Q2);

one end of the sixth resistor (R6) is electrically connected with the grid of the second MOS transistor (Q2), and the other end of the sixth resistor (R6) is grounded;

one end of the seventh resistor (R7) receives a power supply Voltage (VBAT), and the other end of the seventh resistor (R7) is electrically connected with the drain electrode of the second MOS tube (Q2);

one end of the third capacitor (C3) is electrically connected with one end of the fifth resistor (R5), and the other end of the third capacitor is grounded;

one end of the fourth capacitor (C4) is electrically connected with one end of the fifth resistor (R5), and the other end of the fourth capacitor (C4) is grounded;

the source electrode of the second MOS tube (Q2) is grounded.

4. The data destruction circuit of claim 2, further comprising: the disassembly triggering module (50), the disassembly triggering module (50) is used for detecting whether the data storage device is disassembled and outputting a second triggering signal (CF2) to the enabling signal generating module (20) when the data storage device is disassembled;

the enabling signal generating module (20) is further configured to receive a second trigger signal (CF2), and output an enabling signal (EN) to the destruction signal generating module (30) under the control of the second trigger signal (CF 2).

5. A data destruction circuit according to claim 4, characterized in that the decommissioning trigger module (50) comprises: an eighth resistor (R8), a ninth resistor (R9), a fifth capacitor (C5) and a two-pin elastic electrode (X1);

one end of the eighth resistor (R8) receives a power supply Voltage (VBAT), and the other end of the eighth resistor (R8) is electrically connected with one pin of the double-pin elastic electrode (X1);

one end of the ninth resistor (R9) is electrically connected with the other pin of the double-pin elastic electrode (X1), and the other end of the ninth resistor is grounded;

one end of the fifth capacitor (C5) is electrically connected with the other pin of the double-pin elastic electrode (X1), and the other end of the fifth capacitor is grounded;

the other pin of the double-pin elastic electrode (X1) outputs a second trigger signal (CF2), two pins of the double-pin elastic electrode (X1) are installed on the data storage device and are conducted when the data storage device is not disassembled, and the two pins are separated when the data storage device is disassembled;

the enable signal generation module (20) further comprises: a third MOS transistor (Q3) and a tenth resistor (R10);

one end of the tenth resistor (R10) is electrically connected with the source electrode of the third MOS transistor (Q3), and the other end of the tenth resistor (R10) receives a power supply Voltage (VBAT);

the gate of the third MOS transistor (Q3) receives a second trigger signal (CF2), and the drain is electrically connected with one end of a second resistor (R2).

6. A data destruction circuit according to claim 1, characterized in that the destruction signal generation module (30) comprises: an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), a fourteenth resistor (R14), a sixth capacitor (C6), a seventh capacitor (C7), an eighth capacitor (C8) and a low dropout regulator (LDO);

one end of the eleventh resistor (R11) is electrically connected with an output pin of the low dropout regulator (LDO), and the other end of the eleventh resistor (R11) is electrically connected with one end of a twelfth resistor (R12);

the other end of the twelfth resistor (R12) is grounded;

one end of the thirteenth resistor (R13) is electrically connected with an output pin of the low dropout regulator (LDO), and the other end of the thirteenth resistor is grounded;

one end of the fourteenth resistor (R14) is electrically connected with an output pin of the low dropout regulator (LDO), and the other end of the fourteenth resistor (R14) outputs a destruction signal (DES) to the destruction module (40);

one end of the sixth capacitor (C6) receives a power supply Voltage (VBAT), and the other end of the sixth capacitor is grounded;

one end of the seventh capacitor (C7) receives a power supply Voltage (VBAT), and the other end of the seventh capacitor is grounded;

one end of the eighth capacitor (C8) is electrically connected with an output pin of the low dropout regulator (LDO), and the other end of the eighth capacitor is grounded;

an input pin of the low dropout regulator (LDO) is electrically connected with one end of the seventh capacitor (C7), an enabling pin receives an enabling signal (EN), a grounding pin is grounded, and an adjustable voltage pin is electrically connected with the other end of the eleventh resistor (R11).

7. The data destruction circuit according to claim 5, wherein the first MOS transistor (Q1) is an N-type MOS transistor, and the second MOS transistor (Q2) and the third MOS transistor (Q3) are P-type MOS transistors.

8. A data destruction circuit according to claim 1, characterized in that the duration of each output of the destruction signal (DES) is longer than 30 seconds.

9. The data destruction circuit of claim 1, wherein the data storage device is a computer.

10. A data destruction circuit according to claim 9, wherein the computer employs a godson processor or a shenwei processor.