CN211402637U

CN211402637U - Test-per-clock testing device for determining dynamic reconfiguration of scan chain

Info

Publication number: CN211402637U
Application number: CN201921961808.0U
Authority: CN
Inventors: 刘铁桥; 余婷; 姚建荣
Original assignee: Zhejiang University Of Finance & Economics Dongfang College
Current assignee: Zhejiang University Of Finance & Economics Dongfang College
Priority date: 2019-11-13
Filing date: 2019-11-13
Publication date: 2020-09-01
Anticipated expiration: 2029-11-13

Abstract

The utility model discloses a definite test-per-clock testing arrangement of scan chain dynamic reconfiguration. The utility model comprises a selector, a mode controller, a response analyzer and a dynamically reconfigured scan chain group; the test device is a test-per-clock block test device based on the dynamic reconfiguration of scan chains, the scan chains are divided into SFD scan chains and DFD scan chains, and the test patterns of the scan chains are divided into shift test patterns and response compression test patterns. During circuit testing, the scan chains are dynamically reconfigured by the mode controller, and test data are input into the corresponding test mode scan chains through the selector, so that the block test of the circuit is realized. The utility model discloses test with sequential circuit generates the test of simplifying to the combined circuit and generates, and can optimize wiring spending and control complexity, stores too high, test application time overlength, test consumption too big scheduling problem for the test of solving among the super large scale circuit test and provides effective solution.

Description

Test-per-clock testing device for determining dynamic reconfiguration of scan chain

Technical Field

The utility model relates to an integrated circuit field relates to digital integrated circuit definite type test-per-clock test technique, specifically is a scan chain dynamic reconfiguration definite type test-per-clock testing arrangement.

Background

The conventional fixed test and delay test generally use a test-per-scan mode, in which test vectors are serially shifted from a scan chain during test, and after the test vectors are applied, captured test responses are serially shifted out from the scan chain, and simultaneously, the next test vector is serially shifted in, and a test vector is generated in each scan cycle. Thus, the test-per-scan test application time is the product of the length of the scan chain in the circuit and the number of test vectors. In practice, the test application (launch) time is only the number of test vectors, and most of the test time is consumed in the scan shift. As circuit scales have increased, inefficient test-per-scan techniques have become less adaptable.

The Test-per-clock Test, which applies vectors and captures responses in a parallel fashion, generates a Test vector per Test clock cycle with its response captured by a Response Analyzer (RA), is of increasing interest. Thus, the test-per-clock mode has a strong advantage in test application time compared to the test-per-scan mode. However, since each test clock needs to generate a test vector and a capture response, the area overhead and test power consumption of the test structure are higher than those of the conventional test-per-scan structure. Optimization of test structure and test power consumption has been a research hotspot of test-per-clock tests. The BILBO (built-in block observer) test structure modifies a trigger so that the trigger can be switched among a normal mode, a shift mode, a pseudo-random mode and a MISR (multiple input shift register) response compression mode. CBILBO modifies the flip-flop to double flip-flop mode. In the CBILBO structure, TPG and RA are independent, and generation of pseudo-random vectors and response compression can be performed simultaneously. The fault detection of the pseudo-random test method is difficult to achieve satisfactory coverage in a short time due to the existence of anti-pseudo-random faults. In the paper, "a built-in self-test structure based on controlled LFSR and test vector generation" by Huchen et al, a test-per-clock method for controlling LFSR to jump is provided, so that the test efficiency is effectively improved. Zhou Bin et al put forward a 2-Bit Torsion Ring Counter (TRC) based test method in the paper "A Low Power test-per-Clock BIST Scheme through selecting Activating Multi Two bits TRCs", through Selectively Activating the torsion ring counter, effectively reducing test-per-Clock test power consumption and improving fault coverage rate.

However, the above method is only for the combinational circuit test, and in the test-per-clock test of the scan sequential circuit, since the response of the pseudo-output (PPO) inside the circuit needs to be processed at each test clock, the design of the response analyzer of the test-per-clock test of the scan sequential circuit is much more complicated than the test-per-scan test. Bardell et al in the patent "US 4513418" modified the scan chain, and the compression result of the test response was used for the next test generation, so that it has the functions of vector generation and response compression. Son et al in the paper "enhanced test-per-clock BIST architecture" proposed a degenerate MISR to replace response compression, simplifying the structure of Bardell. Krasniewski et al in the paper "Circular self-test path: a low-cost BIST technology" propose a Circular self-test path (CSTP) method that modifies sequential units in a circuit into CSTP units and concatenates them into a Circular chain. The circular chain can be used as a test vector generator and a test response analyzer at the same time, so that the circular chain has the advantages of small area overhead, relatively simple control logic and the like. Aiming at the defect that the (class) pseudo-random test cannot meet the fault coverage rate in a limited time, the literal science et al realizes a definite CSTP method in a paper 'Deterministic circuit Selftest Path' by adding jump logic, and when a plurality of continuous test vectors cannot detect a new fault, the continuous test vectors jump to another definite vector to continue to run through the jump logic. But introducing too much delay would be detrimental to the delay test due to the insertion of additional hardware. Nov & k et al in the paper "Test-per-Clock Testing of the circuit with Scan" proposed a deterministic Test-per-Clock Test structure that effectively reduced the Test application time and Test data storage. But when the circuit is in the test mode, the functional flip-flop no longer receives the circuit response, but is received in parallel by the additionally designed space compactor and MISR. Although the space compactor reduces the number of inputs of the MISR, since the space compactor is composed of an xor network, the time delay of response capture is deteriorated by the multi-layer xor gate, and the space compactor cannot adapt to high-frequency tests. In addition, the space compactor makes the test structure become single in adaptability, and any structure change of the circuit (such as late-stage engineering change order) and change of the test program (such as replacement of test set) can cause the reduction of fault coverage. Rajski proposes a scan chain dynamic reconstruction method in a Patent 'United States Patent 9714981', in the method, a part of scan chains apply test excitation, a part of scan chains respond and capture, and the rest triggers are used as functional units, so that the power consumption of the traditional test-per-clock test and the hardware overhead of a response analyzer are effectively reduced, the defects are complex control and high wiring overhead, and meanwhile, because the test generation is based on a sequential circuit, compared with a full scan design circuit, the test generation is much more complex, and some faults even have the condition that a limited test period cannot be tested.

To summarize: in the aspect of test-per-clock testing, although the (class) pseudo-random test-per-clock-based testing device is simple and easy to implement, the testing efficiency is not high, the hardware cost of the testing structure of the deterministic test-per-clock-based testing device based on the traditional scan chain structure is high, the testing power consumption is too high, the test generation of the deterministic test-per-clock-based testing device based on the traditional scan chain dynamic reconfiguration structure is complex, and the wiring cost is high.

Disclosure of Invention

The utility model aims at prior art not enough, provide a scan chain developments reconfiguration definite type test-per-clock testing arrangement, accomplish under low test application time, low test storage spending and hardware logic spending, low test power consumption and detect the low expense of high quality to fixed type trouble and time delay trouble.

The utility model provides a technical scheme that its technical problem adopted as follows:

the utility model comprises a selector, a mode controller, a response analyzer and a dynamically reconfigured scan chain group; the test-per-clock test apparatus is a test-per-clock block test apparatus that is dynamically reconfigured based on scan chains whose scan cell structures are divided into SFD and DFD structures, so that scan chain types are divided into SFD scan chains and DFD scan chains, and test patterns of the scan chains are divided into shift test pattern (S) scan chains and response compression mode (C) scan chains.

The SFD scan chain is realized by connecting SFD scan units in series;

the DFD scan chain is realized by serially connecting DFD scan units;

during testing, each scan chain has two selectable working modes, namely a shift test mode (S) and a response compression mode (C); the scan chain in the shift test mode (S) forms a shift register, test data is loaded into each shift register through a selector, and a shift test vector is generated in each test clock period; the scan chains simultaneously in the response compression mode (C) constitute a response compressor, which receives and processes in parallel the test responses from the shift test mode (S) scan chain excitations; and after the test period is finished, each scan chain carries out mode reconfiguration through the mode controller and enters the next test period.

The DFD scanning unit is realized by adopting 2 triggers, and can simultaneously carry out a shift test mode (S) and a response compression mode (C);

the working modes of the DFD scanning unit and the SFD scanning unit are as follows:

when the control signal M₁M₂When the signal value of the DFD scanning unit and the SFD scanning unit is '11', the DFD scanning unit and the SFD scanning unit work in a shift test mode, and scan-in receives shift test data from a previous scanning unit and applies a test vector to a circuit through a Q end; meanwhile, the FF2 flip-flop of the DFD scanning unit can also carry out response compression simultaneously;

when the control signal M₁M₂When the signal value of the DFD scanning unit and the SFD scanning unit is '10', the DFD scanning unit and the SFD scanning unit work in a response compression mode (C) to perform response compression, and meanwhile, an output Q end is blocked;

when the control signal M₁M₂When the signal value of (1) is "01", the DFD scan unit and the SFD scan unit operate in a normal function mode.

The determination of the scan chain does not transmit the test response generated by applying the test excitation to any scan cell on the same scan chain to the scan chain cell;

the type of the scanning unit is determined according to requirements, sequential circuit test generation is simplified into combinational logic level test generation, and meanwhile wiring overhead and test mode switching times are reduced; the specific implementation process is as follows:

the determination of the scan chain, namely the grouping of the scan units, is realized based on the graph coloring theory, unrelated scan units are found out and are grouped into the same scan chain, so that test responses generated by any scan unit on the same scan chain by applying test excitation are not transmitted to the scan chain unit, but are received and processed by other scan chains;

determining the type of the scanning unit, wherein the scanning unit has two types, namely a DFD scanning unit and an SFD scanning unit, and the type of the scanning unit is determined according to the following rules:

firstly, in the test, when a certain trigger is used as a test excitation trigger and a test response trigger, the trigger is transformed into a DFD scanning unit;

secondly, the trigger can be transformed into a DFD scanning unit on the aspect of considering the optimization wiring overhead and the control complexity; when the wiring overhead of a certain scanning unit exceeds the budget, the scanning unit can be modified into a DFD scanning unit to be classified into a DFD scanning chain so as to reduce the wiring overhead; on the other hand, when the number of the units on a certain scan chain is lower than a set threshold value, the DFD scan unit can be reconstructed, so that the switching times of the test modes are reduced;

and thirdly, other triggers are transformed into the SFD scanning unit.

The scan chain test mode is determined to follow the following rules:

firstly, when a test vector is applied, as long as a definite bit of the vector exists on a scan chain, the scan chain is in a shift test mode (S);

when the test vector is applied, the response of the fault needs to be captured by at least one scanning unit, and the scanning chain where the scanning unit is located is a response compression mode (C);

and thirdly, when the test vector is applied, the irrelevant scan chain is set to respond to the compression mode (C) to block the input of the irrelevant circuit.

The utility model discloses beneficial effect as follows:

in the utility model, compared with the traditional single scan chain structure, the adopted multi-scan chain structure greatly reduces the length of the shift register, and effectively improves the test efficiency; on the other hand, compared with the traditional method in which the scanning unit is realized by double flip-flop (DFD) design, the utility model introduces single flip-flop (SFD) design, thus effectively reducing the hardware cost of the response analyzer; compare traditional scan chain reconfiguration testing arrangement, the utility model provides a DFD unit design can not only be simplified sequential circuit's test generation to combinatorial logic circuit's test generation, and can optimize wiring overhead and optimal control complexity.

Drawings

FIG. 1 is a block diagram of the scan chain reconfiguration block tester of the present invention;

FIG. 2-a is a structural diagram of a DFD scanning unit of the present invention;

FIG. 2-b is a structural diagram of the SFD scanning unit of the present invention;

FIG. 3 is a diagram of the working modes of the DFD and SFD units of the present invention;

FIG. 4 is a diagram illustrating grouping of scan units according to the present invention;

Detailed Description

The present invention will be further explained with reference to the drawings and examples.

As shown in fig. 1 to 4, a test-per-clock test apparatus for determining a dynamic reconfiguration based on a scan chain includes: test-per-clock block test device based on scan chain dynamic reconfiguration, SFD (single flip-flop-design) and DFD (double flip-flop-design) scan unit realization, scan chain and scan unit type determination, and scan chain test mode determination.

Test-per-clock block test device based on scan chain dynamic reconfiguration specifically comprises the following steps:

the block test device based on scan chain reconfiguration is shown in fig. 1 and comprises a memory 101, a selector 102, a dynamically reconfigured scan chain group 103, a mode controller 104 and a response analyzer 105. The test data stored on the memory 101 at the time of test is loaded into the corresponding scan chain through the selector 102. The scan chain has two forms, one is realized by connecting SFD (single flip-flop design) scan units in series, and the other is realized by connecting DFD (double flip-flop design) scan units in series. During testing, each scan chain has two selectable working modes, namely a shift test mode (S) and a response compression mode (C). The scan chains in S-mode constitute shift registers to which test data is loaded via selector 102, generating a shift test vector per test hour. Meanwhile, the scan chains in C-mode constitute a response compressor, which receives and processes test responses from S-mode scan chain excitations in parallel. After the test cycle is finished, each scan chain is reconfigured to enter the next test cycle through the mode controller 104. At the same time, the response analyzer 105 accepts the outputs of the scan chains in parallel for response compression.

The specific method for realizing the SFD (single flip-flop design) and DFD (double flip-flop design) scanning units comprises the following steps:

implementation of the SFD and DFD scan cell structures as shown in fig. 2-a and 2-b, respectively, the DFD scan cell includes 1 multiplexer 201, 1 xor gate 202, a first flip-flop (FF1)203, a second flip-flop (FF2)204, a first and gate 205, and a second and gate 206;

two input ends of the multiplexer 201 are respectively connected with a scan-in end and a D end; the scan-in terminal receives the shift test data from the scan-out terminal of the previous DFD scanning unit; the D end is the input end of the original function circuit trigger; the output terminal of the multiplexer 201 is connected to the input terminal of a first flip-flop (FF1) 203; the output of the first flip-flop (FF1)203 is connected to one input of a first AND gate 205, and the other input of the first AND gate 205 is connected to the signal M₂The output of the first and gate 205 is the Q terminal and applies the test vector to the circuit through the Q terminal; the output terminal scan _ out of the first flip-flop (FF1)203 is simultaneously connected to the scan _ in terminal of the next DFD scan cell; two input ends of the exclusive-or gate 202 are respectively connected with a res-in end and a D end; the res-in terminal receives circuit response data from the res-out terminal of the previous DFD scanning unit; the output terminal of the exclusive-OR gate 202 is connected to the input terminal of a second flip-flop (FF2)204, the output terminal of the second flip-flop (FF2)204 is connected to one input terminal of a second AND gate 206, and the other input terminal of the second AND gate 206 is connected to the signal M₁The output end of the second and gate 206 is a res _ out end, and is connected to the res _ in end of the next DFD scanning unit through the res _ out end; signal M₁And also to the select signal terminal of the multiplexer 201.

The SFD unit includes a second exclusive or gate 211, a second multiplexer 212, a third multiplexer 213, a third flip-flop 214, and a third and gate 215.

Two input ends of the second exclusive-or gate 211 are respectively connected with a scan-in end and a D end; the scan-in terminal receives the shift test data from the scan-out terminal of the previous SFD scanning unit; an output terminal of the second exclusive or gate 211 is connected to an input terminal of the third multiplexer 213; two input ends of the second multiplexer 212 are respectively connected with the scan-in end and the D end; the output terminal of the second multiplexer 212 is connected to another input terminal of the third multiplexer 213; the output terminal of the third multiplexer 213 is connected to the input terminal of the third flip-flop 214, the output terminal of the third flip-flop 214 is a scan _ out terminal, which is respectively connected to the scan-in terminal of the next SFD scan cell and one input terminal of the second and gate 215, and the other input terminal of the second and gate 215 is connected to the signal M₂. Select signal terminal sum signal M of the second multiplexer 212₁Connected, the selection signal terminal of the third multiplexer 213 and the signal M₂Are connected.

The DFD unit is different from the SFD unit in that it is implemented by using 2 flip-flops, and can perform shift test and response compression simultaneously.

The operation modes of the DFD unit and the SFD unit are shown in fig. 3: when M is₁M₂Signal value ofAt "11", the SFD and DFD cells operate in a shift test mode, scan-in receives the shifted test data from the previous scan cell and applies the test vector to the circuit through the Q terminal. Unlike the SFD unit, the FF2 flip-flop of the DFD unit can also respond simultaneously. When M is₁M₂When the signal value of (1) is "10", the SFD and DFD units operate in response mode, performing response compression, while the output Q terminal is blocked (blocking). When M is₁M₂Is "01", the SFD and DFD units operate in a normal functional mode.

Since the clock signal of each flip-flop can be provided by the system clock, the proposed testing apparatus can be applied to full-speed test-per-clock testing, and when the scan chain is in response mode, both SFD and DFD adopt Q-terminal blocking technique, and the irrelevant circuit blocks will be in stable state, so that the testing power consumption will be effectively reduced. The shift test adopted in the test device just accords with the LOS (latch-on-shift) test mechanism (the latter vector is obtained by shifting the forward vector), and because the test excitation (vector) loading and the response capture in the circuit are respectively acted by the triggers on different scan chains, the scheme effectively gets rid of the problem of realizing the scan-enable signal in the traditional LOS method.

The scan chain and the type of the scan unit are determined, and the specific method comprises the following steps:

the determination of scan chains, i.e. the grouping of scan cells, can be implemented based on graph coloring theory, and the basic idea is to find out irrelevant scan cells and group them into the same scan chain, so that any scan cell in the same scan chain applies test stimulus to generate a test response which is not transmitted to the scan chain cell but received and processed by other scan chains. An example circuit is given in fig. 4 (a). Fig. 4 (B) shows a corresponding directed graph of the circuit, where each vertex corresponds to a scan cell (flip-flop cell), and a directed edge between vertices a and B indicates that there is a combinational logic path from a (drive) to B (receive). In fig. 4, (c) shows an optimized undirected graph, and the grouping problem of the scan cells can be converted into the vertex coloring problem. As shown in fig. 4 (c), the scan chain of the example circuit may be organized as follows: FF1 and FF3 may be located in the same scan chain, and FF2 and FF4 are located separately in different scan chains.

The type of the scanning unit is determined, the scanning unit has two types, namely a DFD unit and an SFD unit, and the type determination follows the following rules:

during testing, when a certain trigger is to be used as a test excitation trigger and a test response trigger, the trigger is transformed into a DFD scanning unit. Like FF4 flip-flop in fig. 4, when testing for a fault at the f fault point, flip-flop FF4 is both generated as a test stimulus and received as a test response. Therefore, flip-flop FF4 should be modified to be a DFD cell to enable both test stimulus generation and test response compression. It is noted that in the united states Patent9714981, since there is no scanning unit capable of performing excitation generation and response compression simultaneously, when detecting a fault at f point, FF4 can only be used as a functional trigger to activate the fault through multiple cycles of control assignment at other inputs. Some faults may have a limited test period non-testable condition;

secondly, the trigger can be transformed into a DFD scanning unit on the aspect of considering the optimization wiring overhead and the control complexity. For example, when the wiring overhead of a certain scan cell is too large, the scan cell can be modified to include the DFD cell in the DFD scan chain to reduce the wiring overhead. On the other hand, when the number of cells in a scan chain is small, such as FF2 in fig. 4, the DFD scan cells and FF4 can be modified to belong to the same scan chain, so that the number of test mode switching times can be reduced;

and thirdly, other triggers are transformed into the SFD scanning unit.

From the above rules, the design of the DFD scan unit increases hardware overhead compared with the SFD, but can effectively reduce test generation complexity and test generation period, and simplify sequential circuit test generation into combinational logic level test generation. Meanwhile, the DFD scanning unit is not limited by position, and wiring overhead and test mode switching times can be effectively reduced by converting DFD design.

The method for determining the scan chain test mode specifically comprises the following steps:

the scan chain can be in two modes at test time, namely a shift test mode (S) and a response compression mode (C), and the mode determination follows the following rules:

The above embodiments are the present invention, and the method is an implementation manner of a test-per-clock testing apparatus based on the determination of the dynamic reconfiguration of the scan chain, but the implementation manner of the present invention is not limited by the embodiments, and any other changes, modifications, replacements, combinations, and simplifications made under the spirit and principle of the present invention should be equivalent replacement manners, and all are included in the protection scope of the present invention.

Claims

1. The fixed test-per-clock test device for dynamic reconfiguration of the scan chain comprises the following components: a selector, a mode controller, a response analyzer, and a dynamically reconfigured scan chain set; the method is characterized in that: the test-per-clock test device is a test-per-clock block test device based on scan chain dynamic reconfiguration, the scan unit structures in the scan chains are divided into SFD structures and DFD structures, the scan chain types are divided into SFD scan chains and DFD scan chains, and the test modes of the scan chains are divided into shift test mode S scan chains and response compression mode C scan chains.

2. The scan chain dynamic reconfiguration deterministic test-per-clock test apparatus of claim 1, wherein:

the test-per-clock test device is a test-per-clock block test device dynamically reconfigured based on a scan chain;

the SFD scan chain is realized by connecting SFD scan units in series;

the DFD scan chain is realized by serially connecting DFD scan units;

during testing, each scan chain has two selectable working modes, namely a shift test mode S and a response compression mode C; the scan chain in the shift test mode S forms a shift register, test data are loaded into each shift register through a selector, and each test clock period generates a shift test vector; the scan chains in the response compression mode C form a response compressor, and receive and process test responses excited by the scan chains in the shift test mode S in parallel; and after the test period is finished, each scan chain carries out mode reconfiguration through the mode controller and enters the next test period.

3. The scan chain dynamically reconfigured deterministic test-per-clock test apparatus of claim 1 or 2, characterized in that:

the DFD scanning unit is realized by adopting 2 triggers, and can simultaneously carry out a shift test mode S and a response compression mode C.

4. The scan chain dynamically reconfigured deterministic test-per-clock test apparatus of claim 1 or 2, characterized in that:

the DFD scanning unit comprises 1 multiplexer (201), 1 exclusive-OR gate (202), a first flip-flop FF1(203), a second flip-flop FF2(204), a first AND gate (205) and a second AND gate (206);

two input ends of the multiplexer (201) are respectively connected with a scan-in end and a D end; the scan-in terminal receives the shift test data from the scan-out terminal of the previous DFD scanning unit; the D end is the input end of the original function circuit trigger; the output end of the multiplexer (201) is connected with the input end of a first trigger FF1 (203); the output of the first flip-flop FF1(203) is connected to one input of a first AND-gate (205), the other input of the first AND-gate (205) being connected to the signal M₂The output of the first and gate (205) is the Q terminal and the test vector is applied to the circuit through the Q terminal; the output scan _ out of the first flip-flop FF1(203) is simultaneously clocked by the next DFD scan cellThe scan _ in ends are connected; two input ends of the exclusive-OR gate (202) are respectively connected with a res-in end and a D end; the res-in terminal receives circuit response data from the res-out terminal of the previous DFD scanning unit; the output end of the exclusive-OR gate (202) is connected with the input end of a second flip-flop FF2(204), the output end of the second flip-flop FF2(204) is connected with one input end of a second AND gate (206), and the other input end of the second AND gate (206) is connected with a signal M₁The output end of the second AND gate (206) is a res _ out end and is connected with the res _ in end of the next DFD scanning unit through the res _ out end; signal M₁And is connected to the selection signal terminal of the multiplexer (201).

5. The scan chain dynamically reconfigured deterministic test-per-clock test apparatus of claim 1 or 2, characterized in that:

the SFD unit comprises a second exclusive-OR gate (211), a second multiplexer (212), a third multiplexer (213), a third trigger (214) and a third AND gate (215);

two input ends of the second exclusive-OR gate (211) are respectively connected with a scan-in end and a D end; the scan-in terminal receives the shift test data from the scan-out terminal of the previous SFD scanning unit; the output end of the second exclusive-or gate (211) is connected with one input end of a third multiplexer (213); two input ends of the second multiplexer (212) are respectively connected with the scan-in end and the D end; the output end of the second multiplexer (212) is connected with the other input end of the third multiplexer (213); the output end of the third multiplexer (213) is connected with the input end of a third flip-flop (214), the output end of the third flip-flop (214) is a scan _ out end and is respectively connected with a scan-in end of the next SFD scanning unit and one input end of a third AND gate (215), and the other input end of the third AND gate (215) is connected with a signal M₂(ii) a A selection signal terminal of the second multiplexer (212) and a signal M₁Connected, the selection signal terminal of the third multiplexer (213) and the signal M₂Are connected.