CN211348404U

CN211348404U - Lightning current impact strength test circuit

Info

Publication number: CN211348404U
Application number: CN201922260380.3U
Authority: CN
Inventors: 喻杭斌
Original assignee: Chongqing Kingbow Instrument Industrial Co ltd
Current assignee: Chongqing Kingbow Instrument Industrial Co ltd
Priority date: 2019-12-17
Filing date: 2019-12-17
Publication date: 2020-08-25
Anticipated expiration: 2029-12-17

Abstract

The utility model discloses a lightning current impact strength test circuit, which comprises a signal acquisition unit, a signal shaping unit, a signal processing unit, a display unit, a power supply unit and a communication transmission unit; the signal processing unit obtains the intensity and the impact waveform of lightning through the voltage signal sent by the signal shaping unit, and the power supply unit is used for supplying power to each unit. The utility model discloses the setting can test the impact strength and the wave form of thunderbolt, is convenient for obtain electronic equipment or electron device's earth connection, ground connection branch line, the impact current intensity on the ground connection line that gathers, can accurately give the lightning protection plan in this area more rationally and design corresponding lightning protection measure etc. ensure the more reliable operation of system, simple structure, the practicality is strong.

Description

Lightning current impact strength test circuit

Technical Field

The utility model relates to a lightning protection test field, in particular to lightning current impact strength test circuit.

Background

With the development of computer technology, automatic control technology, information technology and the increasing application of various electronic systems, these systems have been widely used in various industries and factories with considerable scale and complexity, and because the working voltage of these electronic systems is low and the current is small, the lightning phenomenon and the complex field interference signal which are common in nature easily exceed the working voltage of these electronic systems, causing data loss and damage to the electronic systems, resulting in serious accidents of whole control system interruption and factory shutdown. In order to prevent the interference of lightning, it has become common knowledge to add surge protectors to electronic systems.

With the advance of digital, information and intelligent technologies of factories, the analysis of line surge protection efficiency, the analysis of the relation between the occurrence probability of induced lightning stroke and high-potential counterattack and the ground flash density, the analysis of the relation between the intensity of induced lightning stroke and high-potential counterattack and the ground flash intensity, the analysis of the relation between the induced lightning stroke and high-potential counterattack and the layout, height and the like of process equipment and the like are required, the real-time measurement of the intensity of surge impact current on a ground wire, a ground branch wire and a ground bus of a surge protector is required, the scientific and reasonable analysis of lightning monitoring data is required, the lightning protection plan of the area and the corresponding lightning protection measures can be more accurately and reasonably designed, and the more reliable operation of the system is ensured.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is to provide a can obtain electronic equipment or electron device's earth connection, ground connection branch line, ground connection gather the impulse current intensity on the line to in carry out scientific and reasonable's analysis's lightning current impulse intensity test circuit to thunder and lightning monitoring data.

The technical scheme of the utility model as follows:

a lightning current impact strength test circuit comprises a signal acquisition unit, a signal shaping unit, a signal processing unit, a display unit, a power supply unit and a communication transmission unit; the signal acquisition unit is electrically connected with the signal shaping unit, and the signal shaping unit, the display unit and the communication transmission unit are electrically connected with the signal processing unit; the signal processing unit obtains the intensity and the impact waveform of lightning stroke through the voltage signal sent by the signal shaping unit, and the power supply unit is used for providing required direct current voltage for the signal shaping unit, the signal processing unit, the display unit and the communication transmission unit;

the signal shaping unit comprises a rectifying circuit, a lightning intensity extraction circuit and a lightning waveform extraction circuit; the lightning intensity extraction circuit comprises a resistor R1, a resistor R42, a resistor R44, a resistor R46, a resistor R51, a capacitor C3, a capacitor C4, a capacitor C7, an operational amplifier U7A and an operational amplifier U7B;

the positive phase input end of the operational amplifier U7A is electrically connected with the rectifying circuit through a resistor R1, the positive phase input end of the operational amplifier U7A is also connected with a digital ground G _ A through a capacitor C3, the negative phase input end of the operational amplifier U7A is electrically connected with the output end thereof, and the output end of the operational amplifier U7A is electrically connected with the positive phase input end of the operational amplifier U7B through a resistor R42; the positive phase input end of the operational amplifier U7B is connected with a digital ground G _ A through a capacitor C4, the positive phase input end of the operational amplifier U7B is further connected with the digital ground G _ A through a resistor R44 and a resistor R46 in sequence, the negative phase input end of the operational amplifier U7B is electrically connected with the output end of the operational amplifier U7B, the output end of the operational amplifier U7B is electrically connected with a first end of the capacitor C7 through a resistor R51, the first end of the capacitor C7 is electrically connected with the signal processing unit, and the second end of the capacitor C7 is connected with the digital ground G _ A;

the lightning waveform extraction circuit comprises a resistor R14, a resistor R15, a resistor R40, a resistor R48, a resistor R52, an operational amplifier U8A and an operational amplifier U8B; the positive phase input end of the operational amplifier U8A is electrically connected with the rectifying circuit through a resistor R14, the negative phase input end of the operational amplifier U8A is electrically connected with the output end thereof, and the output end of the operational amplifier U8A is electrically connected with the positive phase input end of the operational amplifier U8B through a resistor R15; the positive phase input end of the operational amplifier U8B is connected with a digital ground G _ A sequentially through a resistor R40 and a resistor R48, the negative phase input end of the operational amplifier U8B is electrically connected with the output end of the operational amplifier U8B, and the output end of the operational amplifier U8B is electrically connected with the signal processing unit through a resistor R52.

Further, the operational amplifier U7A and the operational amplifier U7B are integrated in a chip U7, a power supply terminal of the chip U7 is connected to a voltage of 5V through a resistor R8, a power supply terminal of the chip U7 is further connected to a digital ground G _ a through a capacitor C6, and a ground terminal of the chip U7 is connected to the digital ground G _ a; the operational amplifier U8A and the operational amplifier U8B are integrated in a chip U8, a power supply terminal of the chip U8 is connected with 5V voltage through a resistor R12, a power supply terminal of the chip U8 is also connected with a digital ground G _ A through a capacitor C36, and a ground terminal of the chip U8 is connected with the digital ground G _ A.

Further, the rectifying circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R10, a resistor R11, a bidirectional transient suppression diode D3, a bidirectional transient suppression diode D4 and a first rectifying bridge; the two ends of the resistor R3 are electrically connected with the signal acquisition unit through an interface A1 and an interface A2 respectively, the resistor R4, the resistor R5, the resistor R6 and the bidirectional transient suppression diode D4 are all connected with the resistor R3 in parallel, the two ends of the bidirectional transient suppression diode D4 are also electrically connected with two input ends of a first rectifier bridge respectively, the positive output end of the first rectifier bridge is connected with a digital ground G _ A through a resistor R10, the resistor R11 and the bidirectional transient suppression diode D3 are connected with the resistor R10 in parallel, and the negative output end of the first rectifier bridge is connected with the digital ground G _ A.

Further, the power supply unit comprises a chip U2, a chip P2, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R30, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, an inductor L1, a diode D15 and a diode D16;

the positive end of the diode D15 is electrically connected with the interface A4, and the power ground GG is electrically connected with the interface A5; the negative terminal of the diode D15 is electrically connected with the VIN pin of a chip U2, the VIN pin of the chip U2 is connected with a power ground GG through a capacitor C18, the capacitor C19 is connected with a capacitor C18 in parallel, the VIN pin of the chip U2 is further electrically connected with the EN pin thereof through a resistor R22, the EN pin of the chip U2 is connected with the power ground GG through a resistor R26, the SS/TR pin of the chip U2 is connected with the power ground GG through a capacitor C16, the RT pin of the chip U2 is connected with the power ground GG through a resistor R29 and a resistor R28 in sequence, the GND pin of the chip U2 is connected with the power ground GG, the COMP pin of the chip U2 is connected with the power ground GG through a capacitor C17, the COMP pin of the chip U2 is further connected with the power ground GG through a resistor R25 and a capacitor C20 in sequence, the BOOT pin of the chip U2 is electrically connected with the PH pin thereof through a capacitor C11, the positive end of the diode D16 is connected with a power ground GG, the negative end of the diode D16 is electrically connected with the first end of an inductor L1, the second end of the inductor L1 outputs 15V voltage, the second end of the inductor L1 is further electrically connected with a VSNS pin of a chip U2 through a resistor R23 and a resistor R27 in sequence, and the VSNS pin of the chip U2 is connected with the power ground GG through a resistor R30;

the second end of the inductor L1 is connected with a power ground GG through a capacitor C14, the capacitor C15 is connected with a capacitor C14 in parallel, the second end of the inductor L1 is also electrically connected with a VDD pin of a chip P2 through a resistor R21, the VDD pin of the chip P2 is connected with the power ground GG through a capacitor C12, the C pin of the chip P2 is electrically connected with an RC COMMON pin thereof through a capacitor C13, the R pin of the chip P2 is electrically connected with an RC COMMON pin thereof through a capacitor C13, and the-ASTABLE pin, the + ASTABLE pin, the TRIGGER pin, the Vss, the + TRIGGER pin, the EXT Reset pin and the RETRIGGER pin of the chip P2 are all connected with the power ground GG;

the power supply unit further comprises a chip Q1, a chip U4, a chip U5, a chip U9, a transformer T3, a second rectifier bridge, a third rectifier bridge, a resistor R36, a resistor R39, a resistor R50, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C34, a capacitor C35, a capacitor C40, a capacitor C41 and a light emitting diode D23;

the OSC OUT pin of the chip P2 is electrically connected with a grid G1 of a P-channel field effect transistor in a chip Q1 through a capacitor C25, a grid G1 of the P-channel field effect transistor in the chip Q1 is connected with 15V voltage through a resistor R36, and a source S1 of the P-channel field effect transistor in the chip Q1 is connected with 15V voltage; the OSC OUT pin of the chip P2 is further electrically connected to a gate G2 of an N-channel fet in a chip Q1 through a capacitor C27, a gate G2 of the N-channel fet in the chip Q1 is connected to a power ground GG through a resistor R39, a source S2 of the P-channel fet in the chip Q1 is connected to the power ground GG, a drain D1 of the P-channel fet in the chip Q1 and a drain D2 of the N-channel fet are both electrically connected to a first input terminal of a transformer T3, a second input terminal of the transformer T3 is connected to a 15V voltage through a capacitor C28, and a second input terminal of the transformer T3 is further connected to the power ground GG through a capacitor C31;

a first output end and a second output end of the transformer T3 are respectively and electrically connected with two input ends of a second rectifier bridge, a positive output end of the second rectifier bridge is electrically connected with a Vin pin of the chip U4, and a negative output end of the second rectifier bridge is connected with an analog ground G; the Vin pin of the chip U4 is connected with an analog ground G through a capacitor C31, the Vin pin of the chip U4 is also electrically connected with the positive terminal of a light-emitting diode D23 through a resistor R50, and the negative terminal of the light-emitting diode D23 is connected with the analog ground G; the GND pin of the chip U4 is connected with an analog ground G, the Vout pin of the chip U4 outputs an analog 3.3V voltage, the Vout pin of the chip U4 is also connected with an analog third rectifier bridge ground G through a capacitor C26, and the capacitor C29 is connected with a capacitor C26 in parallel;

a third output end and a fourth output end of the transformer T3 are respectively and electrically connected with two input ends of a third rectifier bridge, the positive output end outputs 5V voltage, and the negative output end is connected with a digital ground G _ A; the positive output end of the third rectifier bridge is electrically connected with a Vin pin of a chip U9, and the Vin pin of the chip U9 is connected with a digital ground G _ A through a capacitor C35; the GND pin of the chip U9 is connected with a digital ground G _ A, the Vout pin of the chip U9 outputs a digital 3.3V voltage, the Vout pin of the chip U9 is also connected with the digital ground G _ A through a capacitor C32, and the capacitor C34 is connected with a capacitor C32 in parallel; the Vout pin of the chip U9 is also electrically connected with the Vin pin of the chip U5, the GND pin of the chip U5 is connected with a digital ground G _ A, the Vout pin of the chip U5 outputs 2.5V voltage, the Vout pin of the chip U5 is also connected with the digital ground G _ A through a capacitor C40, and the capacitor C41 is connected with a capacitor C40 in parallel.

Further, the signal processing unit comprises a chip U1, a resistor R9, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C1, a capacitor C2, a capacitor C5, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C43, a capacitor C44 and a crystal Y1;

the VDD1 pin, the VDD2 pin and the VDD3 pin of the chip U1 are all connected with analog 3.3V voltage, the VDD1 pin of the chip U1 is also connected with analog ground G through a capacitor C8, the capacitor C9 and the capacitor C10 are both connected with a capacitor C8 in parallel, the NRST pin of the chip U1 is connected with analog 3.3V voltage through a resistor R9, and the NRST pin of the chip U1 is also connected with analog ground G through a capacitor C5; the VDDA pin of the chip U1 is connected with a digital 3.3V voltage, the VDDA pin of the chip U1 is also connected with an analog ground G through a capacitor C43, and the capacitor C44 is connected with a capacitor C43 in parallel; the VSS1 pin, the VSS2 pin and the VSS3 pin of the chip U1 are all connected with an analog ground G, and the VSSA pin of the chip U1 is connected with a digital ground G _ A;

the OSC _ IN pin of the chip U1 is connected with an analog ground G through a capacitor C1, the OSC _ IN pin of the chip U1 is also electrically connected with the OSC _ OUT pin through a crystal Y1, and the OSC _ OUT pin of the chip U1 is connected with the analog ground G through a capacitor C2; the PA5 pin of the chip U1 is electrically connected with a first end of a capacitor C7, and the PA6 pin of the chip U1 is electrically connected with a first end of a capacitor C39; the PA8 pin, the PB5 pin, the PB6 pin, the PB7 pin, the PB8 pin and the PB9 pin of the chip U1 are respectively and electrically connected with corresponding positions of the display unit, and the PA2 pin, the PA3 pin and the PB12 pin of the chip U1 are respectively and electrically connected with corresponding positions of the communication transmission unit.

Further, the display unit comprises a chip U3, a chip LC1, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R37, a resistor R38, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, an inductor L2 and a diode D17;

the IN pin of the chip U3 is connected with an analog 3.3V voltage through a resistor R31, the IN pin of the chip U3 is also connected with an analog ground G through a capacitor C23, the EN pin of the chip U3 is electrically connected with the PA8 pin of the chip U1, the OC pin of the chip U3 is connected with the analog ground G through a resistor R35, the IN pin of the chip U3 is also electrically connected with the LX pin thereof through an inductor L2, the LX pin of the chip U3 is electrically connected with the positive terminal of a diode D17, the negative terminal of the diode D17 is electrically connected with the FB pin thereof through a resistor R32, the FB pin of the chip U3 is connected with the analog ground G through a resistor R34, and the GND pin of the chip U3 is connected with the analog ground G;

the negative end of the diode D17 is electrically connected with the COM0 pin of the chip LC1, the COM0 pin of the chip LC1 is connected with the analog ground G through the capacitor C21, the capacitor C22 is connected in parallel with the capacitor C21, the COM1 pin of the chip LC1 is connected with the analog ground G through the capacitor C24, the COM2 pin of the chip LC1 is connected, the COM3 pin of the chip LC1 is connected with an analog ground G, the SEG0 pin of the chip LC1 is connected with an analog ground G through a resistor R33, the SEG1 pin of the chip LC1 is electrically connected with the PB7 pin of the chip U1, the SEG2 pin of the chip LC1 is electrically connected with the PB6 pin of the chip U1, the SEG3 pin of the chip LC1 is electrically connected with the PB5 pin of the chip U1, the SEG4 pin of the chip LC1 is electrically connected with the PB9 pin of the chip U1, the SEG4 pin of the chip LC1 is also connected with an analog 3.3V voltage through a resistor R37, the SEG5 pin of the chip LC1 is electrically connected with the PB8 pin of the chip U1, and the SEG5 pin of the chip LC1 is also connected with an analog 3.3V voltage through a resistor R38.

Further, the communication transmission unit comprises a chip U6, a resistor R41, a resistor R43, a resistor R45, a resistor R47, a resistor R49, a capacitor C33, a capacitor C38 and a bidirectional transient suppression diode D22;

the RO pin of the chip U6 is electrically connected to the PA3 pin of the chip U1 through a resistor R43, the RE pin of the chip U6 is electrically connected with the DE pin thereof, the DE pin of the chip U6 is electrically connected with the PB12 pin of the chip U1 through a resistor R45, the DI pin of the chip U6 is electrically connected to the PA2 pin of the chip U1 through a resistor R47, the VCC pin of the chip U6 is connected with analog 3.3V voltage, the VCC pin of the chip U6 is also electrically connected with the A pin through a resistor R41, the A pin of the chip U6 is electrically connected with an interface A6, the A pin of the chip U6 is also electrically connected with the B pin thereof through a bidirectional transient suppression diode D22, the B pin of the chip U6 is electrically connected with an interface A7, the B pin of the chip U6 is also connected with an analog ground G through a capacitor C38, the resistor R48 is connected in parallel with the capacitor C38, and the GND pin of the chip U6 is connected with an analog ground G.

Has the advantages that: the utility model discloses in, draw thunder and lightning intensity and waveform information in circuit and the thunder wave shape extraction circuit draws lightning intensity and waveform information from the thunderbolt induced-current through thunder and lightning intensity, can obtain intensity and the waveform of this time thunderbolt after handling by the signal processing unit, and can transmit and save and handle for remote terminal, be convenient for obtain electronic equipment or electron device's earth connection, the ground connection branch line, the impulse current intensity on the line is gathered to the ground connection, can give the lightning protection plan in this area and design corresponding lightning protection measure etc. more accurately rationally, ensure the more reliable operation of system, moreover, the steam generator is simple in structure, therefore, the clothes hanger is strong in practicability.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a circuit diagram of a signal shaping unit;

FIG. 3 is a circuit diagram of a power supply unit;

FIG. 4 is a circuit diagram of a signal processing unit;

FIG. 5 is a circuit diagram of a display unit;

fig. 6 is a circuit diagram of a communication transmission unit.

Detailed Description

The present invention will be further explained with reference to the accompanying drawings.

As shown in fig. 1, the utility model relates to a lightning current impact strength test circuit, which comprises a signal acquisition unit 1, a signal shaping unit 2, a signal processing unit 3, a display unit 4, a power supply unit 5 and a communication transmission unit 6; the signal acquisition unit 1 adopts a KB021 current transformer T1 and is used for converting lightning impulse current into a detectable small current signal, the signal shaping unit 2 is used for shaping the current signal sent by the signal acquisition unit 1 and converting the current signal into a voltage signal, the signal processing unit 3 is used for obtaining the intensity and the impulse waveform of lightning stroke through the voltage signal sent by the signal shaping unit 2, and the power supply unit 5 is used for supplying required direct current voltage to the signal shaping unit 2, the signal processing unit 3, the display unit 4 and the communication transmission unit 6.

As shown in fig. 2, the signal shaping unit 2 includes a rectifying circuit 21, a lightning intensity extracting circuit 22, and a lightning waveform extracting circuit 23; the rectifying circuit 21 comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R10, a resistor R11, a bidirectional transient suppression diode D3, a bidirectional transient suppression diode D4 and a first rectifying bridge 211; the first rectifier bridge 211 is FR107, two ends of the resistor R3 are electrically connected with the signal acquisition unit 1 through an interface a1 and an interface a2, the resistor R4, the resistor R5, the resistor R6 and the bidirectional transient suppression diode D4 are all connected in parallel with the resistor R3, two ends of the bidirectional transient suppression diode D4 are also electrically connected with two input ends of the first rectifier bridge 211, a positive output end of the first rectifier bridge 211 is connected with a digital ground G _ a through a resistor R10, the resistor R11 and the bidirectional transient suppression diode D3 are both connected in parallel with the resistor R10, and a negative output end of the first rectifier bridge 211 is connected with the digital ground G _ a.

The lightning intensity extraction circuit 22 comprises a resistor R1, a resistor R42, a resistor R44, a resistor R46, a resistor R51, a capacitor C3, a capacitor C4, a capacitor C7, an operational amplifier U7A and an operational amplifier U7B; the positive phase input end of the operational amplifier U7A is electrically connected with the positive output end of the first rectifier bridge 211 through a resistor R1, the positive phase input end of the operational amplifier U7A is also connected with a digital ground G _ A through a capacitor C3, the negative phase input end of the operational amplifier U7A is electrically connected with the output end thereof, and the output end of the operational amplifier U7A is electrically connected with the positive phase input end of the operational amplifier U7B through a resistor R42; the positive phase input end of the operational amplifier U7B is connected with a digital ground G _ A through a capacitor C4, the positive phase input end of the operational amplifier U7B is further connected with the digital ground G _ A through a resistor R44 and a resistor R46 in sequence, the negative phase input end of the operational amplifier U7B is electrically connected with the output end of the operational amplifier U7B, the output end of the operational amplifier U7B is electrically connected with a first end of the capacitor C7 through a resistor R51, a first end of the capacitor C7 is electrically connected with the signal processing unit 3, and a second end of the capacitor C7 is connected with the digital ground G _ A.

The lightning waveform extraction circuit 23 comprises a resistor R14, a resistor R15, a resistor R40, a resistor R48, a resistor R52, an operational amplifier U8A and an operational amplifier U8B;

the positive phase input end of the operational amplifier U8A is electrically connected with the positive output end of the first rectifier bridge 211 through a resistor R14, the negative phase input end of the operational amplifier U8A is electrically connected with the output end thereof, and the output end of the operational amplifier U8A is electrically connected with the positive phase input end of the operational amplifier U8B through a resistor R15; the positive phase input end of the operational amplifier U8B is further connected with a digital ground G _ A through a resistor R40 and a resistor R48 in sequence, the negative phase input end of the operational amplifier U8B is electrically connected with the output end of the operational amplifier U8B, the output end of the operational amplifier U8B is electrically connected with the signal processing unit 3 through a resistor R52, and the second end of the operational amplifier U8B is connected with the digital ground G _ A.

The operational amplifier U7A and the operational amplifier U7B are integrated in a chip U7, and the model of the chip U7 is LM 258; the power supply end of the chip U7 is connected with 5V voltage through a resistor R8, the power supply end of the chip U7 is also connected with a digital ground G _ A through a capacitor C6, and the ground end of the chip U7 is connected with the digital ground G _ A; the operational amplifier U8A and the operational amplifier U8B are integrated in a chip U8, and the model of the chip U8 is LM 258; the power supply terminal of the chip U8 is connected with 5V voltage through a resistor R12, the power supply terminal of the chip U8 is also connected with a digital ground G _ A through a capacitor C36, and the ground terminal of the chip U8 is connected with the digital ground G _ A.

As shown in fig. 3, the power supply unit 5 includes a chip U2, a chip P2, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R30, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, an inductor L1, a diode D15, and a diode D16; the model number of the chip U2 is TPS5401, and the model number of the chip P2 is CD 4047.

The positive end of the diode D15 is electrically connected with the interface A4, and the power ground GG is electrically connected with the interface A5; the negative terminal of the diode D15 is electrically connected with the VIN pin of a chip U2, the VIN pin of the chip U2 is connected with a power ground GG through a capacitor C18, the capacitor C19 is connected with a capacitor C18 in parallel, the VIN pin of the chip U2 is further electrically connected with the EN pin thereof through a resistor R22, the EN pin of the chip U2 is connected with the power ground GG through a resistor R26, the SS/TR pin of the chip U2 is connected with the power ground GG through a capacitor C16, the RT pin of the chip U2 is connected with the power ground GG through a resistor R29 and a resistor R28 in sequence, the GND pin of the chip U2 is connected with the power ground GG, the COMP pin of the chip U2 is connected with the power ground GG through a capacitor C17, the COMP pin of the chip U2 is further connected with the power ground GG through a resistor R25 and a capacitor C20 in sequence, the BOOT pin of the chip U2 is electrically connected with the PH pin thereof through a capacitor C11, the positive end of the diode D16 is connected with a power ground GG, the negative end of the diode D16 is electrically connected with the first end of an inductor L1, the second end of the inductor L1 outputs 15V voltage, the second end of the inductor L1 is further electrically connected with the VSNS pin of the chip U2 through a resistor R23 and a resistor R27 in sequence, and the VSNS pin of the chip U2 is connected with the power ground GG through a resistor R30. The second end of the inductor L1 is connected with a power ground GG through a capacitor C14, the capacitor C15 is connected with a capacitor C14 in parallel, the second end of the inductor L1 is further electrically connected with a VDD pin of a chip P2 through a resistor R21, the VDD pin of the chip P2 is connected with the power ground GG through a capacitor C12, the C pin of the chip P2 is electrically connected with an RC COMMON pin thereof through a capacitor C13, the R pin of the chip P2 is electrically connected with an RCcommon pin thereof through a capacitor C13, and the-ASTABLE pin, the + ASTABLE pin, the TRIGGER pin, the Vss, the + TRIGGER pin, the EXT Reset pin and the RETRIGGER pin of the chip P2 are all connected with the power ground GG.

The power supply unit 5 further comprises a chip Q1, a chip U4, a chip U5, a chip U9, a transformer T3, a second rectifier bridge 51, a third rectifier bridge 52, a resistor R36, a resistor R39, a resistor R50, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C34, a capacitor C35, a capacitor C40, a capacitor C41 and a light emitting diode D23; the model numbers of the chip U4 and the chip U9 are HT7533, and the model number of the chip U5 is REF 3125.

The OSC OUT pin of the chip P2 is electrically connected with a grid G1 of a P-channel field effect transistor in a chip Q1 through a capacitor C25, a grid G1 of the P-channel field effect transistor in the chip Q1 is connected with 15V voltage through a resistor R36, and a source S1 of the P-channel field effect transistor in the chip Q1 is connected with 15V voltage; the OSC OUT pin of the chip P2 is further electrically connected to a gate G2 of an N-channel fet in a chip Q1 through a capacitor C27, a gate G2 of the N-channel fet in the chip Q1 is connected to a power ground GG through a resistor R39, a source S2 of the P-channel fet in the chip Q1 is connected to the power ground GG, a drain D1 of the P-channel fet in the chip Q1 and a drain D2 of the N-channel fet are both electrically connected to a first input terminal of a transformer T3, a second input terminal of the transformer T3 is connected to a 15V voltage through a capacitor C28, and a second input terminal of the transformer T3 is further connected to the power ground GG through a capacitor C31.

A first output end and a second output end of the transformer T3 are respectively and electrically connected with two input ends of a second rectifier bridge 51, a positive output end of the second rectifier bridge 51 is electrically connected with a Vin pin of a chip U4, and a negative output end of the second rectifier bridge is connected with an analog ground G; the Vin pin of the chip U4 is connected with an analog ground G through a capacitor C31, the Vin pin of the chip U4 is also electrically connected with the positive terminal of a light-emitting diode D23 through a resistor R50, and the negative terminal of the light-emitting diode D23 is connected with the analog ground G; the GND pin of the chip U4 is connected with an analog ground G, the Vout pin of the chip U4 outputs an analog 3.3V voltage, the Vout pin of the chip U4 is also connected with an analog third rectifier bridge 52 ground G through a capacitor C26, and the capacitor C29 is connected with a capacitor C26 in parallel.

A third output end and a fourth output end of the transformer T3 are respectively electrically connected with two input ends of a third rectifier bridge 52, the positive output end outputs 5V voltage, and the negative output end is connected with a digital ground G _ A; the positive output end of the third rectifier bridge 52 is electrically connected with a Vin pin of a chip U9, and the Vin pin of the chip U9 is connected with a digital ground G _ A through a capacitor C35; the GND pin of the chip U9 is connected with a digital ground G _ A, the Vout pin of the chip U9 outputs a digital 3.3V voltage, the Vout pin of the chip U9 is also connected with the digital ground G _ A through a capacitor C32, and the capacitor C34 is connected with a capacitor C32 in parallel; the Vout pin of the chip U9 is also electrically connected with the Vin pin of the chip U5, the GND pin of the chip U5 is connected with a digital ground G _ A, the Vout pin of the chip U5 outputs 2.5V voltage, the Vout pin of the chip U5 is also connected with the digital ground G _ A through a capacitor C40, and the capacitor C41 is connected with a capacitor C40 in parallel.

As shown in fig. 4, the signal processing unit 3 includes a chip U1, a resistor R9, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C1, a capacitor C2, a capacitor C5, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C43, a capacitor C44, and a crystal Y1; the model of the chip U1 is STM32F103C8T 6.

The VDD1 pin, the VDD2 pin and the VDD3 pin of the chip U1 are all connected with analog 3.3V voltage, the VDD1 pin of the chip U1 is also connected with analog ground G through a capacitor C8, the capacitor C9 and the capacitor C10 are both connected with a capacitor C8 in parallel, the NRST pin of the chip U1 is connected with analog 3.3V voltage through a resistor R9, and the NRST pin of the chip U1 is also connected with analog ground G through a capacitor C5; the VDDA pin of the chip U1 is connected with a digital 3.3V voltage, the VDDA pin of the chip U1 is also connected with an analog ground G through a capacitor C43, and the capacitor C44 is connected with a capacitor C43 in parallel; the VSS1 pin, the VSS2 pin and the VSS3 pin of the chip U1 are all connected to analog ground G, and the VSSA pin of the chip U1 is connected to digital ground G _ A.

The OSC _ IN pin of the chip U1 is connected with an analog ground G through a capacitor C1, the OSC _ IN pin of the chip U1 is also electrically connected with the OSC _ OUT pin through a crystal Y1, and the OSC _ OUT pin of the chip U1 is connected with the analog ground G through a capacitor C2; the PA5 pin of the chip U1 is electrically connected with a first end of a capacitor C7, and the PA6 pin of the chip U1 is electrically connected with a first end of a capacitor C39; the PA8 pin, the PB5 pin, the PB6 pin, the PB7 pin, the PB8 pin and the PB9 pin of the chip U1 are respectively and electrically connected with corresponding positions of the display unit 4, and the PA2 pin, the PA3 pin and the PB12 pin of the chip U1 are respectively and electrically connected with corresponding positions of the communication transmission unit 6.

As shown in fig. 5, the display unit 4 includes a chip U3, a chip LC1, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R37, a resistor R38, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, an inductor L2, and a diode D17; chip U3 is model HT 7991.

The IN pin of the chip U3 is connected with an analog 3.3V voltage through a resistor R31, the IN pin of the chip U3 is also connected with an analog ground G through a capacitor C23, the EN pin of the chip U3 is electrically connected with the PA8 pin of the chip U1, the OC pin of the chip U3 is connected with the analog ground G through a resistor R35, the IN pin of the chip U3 is also electrically connected with the LX pin thereof through an inductor L2, the LX pin of the chip U3 is electrically connected with the positive terminal of a diode D17, the negative terminal of the diode D17 is electrically connected with the FB pin thereof through a resistor R32, the FB pin of the chip U3 is connected with the analog ground G through a resistor R34, and the GND pin of the chip U3 is connected with the analog ground G.

As shown in fig. 6, the communication transmission unit 6 includes a chip U6, a resistor R41, a resistor R43, a resistor R45, a resistor R47, a resistor R49, a capacitor C33, a capacitor C38, and a bidirectional transient suppression diode D22; the model number of the chip U6 is SP 485.

The working principle of the embodiment is as follows:

as shown in fig. 3, in operation, the positive electrode of a DC24V power supply (not labeled) is electrically connected to port a4, the negative electrode is electrically connected to port a5, diode D15 has the function of unidirectional power supply protection, DC24V voltage is connected to power management chip U2 through diode D15, and is converted into DC15V voltage output by power management chip U2 and its accessory circuits, and then is connected to chip P2 through R21, and generates an oscillating waveform through chip P2, one path is input to pin 5 of chip Q1 through capacitor C25 and pull-up resistor R36, the other path is input to pin 2 of chip Q1 through capacitor C27 and pull-down resistor R39, and is converted into ac power to transformer T3 through chip Q1, and is output in two paths after transformer T3, one path is rectified by second rectifier bridge 51 and then is sent to chip U4, and outputs analog 3.3V voltage, the other path is rectified by third rectifier bridge 52 and outputs 5V 3V voltage, and chip U9 is converted into digital voltage output, the chip U5 converts the input 3.3V voltage into a 2.5V reference voltage output.

As shown in fig. 2, when a lightning strike occurs, the current transformer T1 inductively extracts a current signal of an electronic device or an electronic device during the lightning strike, outputs an induced current, discharges the current through the resistors R3, R4, R5, and R6, performs amplitude limiting protection by the bidirectional transient suppression diode D4, rectifies the current signal by the first rectifier bridge 211, converts the current signal into a voltage signal, and then respectively sends the voltage signal to the lightning intensity extraction circuit 22 and the lightning waveform extraction circuit 23. The voltage signal sent to the lightning intensity extraction circuit 22 is firstly subjected to current leakage and amplitude limiting through resistors R10 and R11 and a bidirectional transient suppression diode D3, then is input to U7A through a resistor R1, U7A is a voltage follower, the voltage output from U7A enters an integrating circuit formed by resistors R42, R44, R46 and a capacitor C4, the waveform of the signal is stretched, the signal is conveniently captured by the signal processing unit 3 at the maximum intensity value, then is input to U7B, U7B is a voltage follower, and the signal output by U7B is filtered through C7 to generate an AD _ DIN1 signal which is sent to the signal processing unit 3; U8A and U8B are voltage followers, and the signal entering the lightning waveform extraction circuit 23 is connected through a resistor R14, input to U8A, followed by output by U8A, divided by resistors R15, R40 and R48, output to U8B, and generated through U8B and a resistor R52 as an AD _ DIN2 signal to be sent to the signal processing unit 3.

As shown in fig. 4 to 6, when the signal AD _ DIN1 and the signal AD _ DIN2 are received by the U1, the signal AD _ DIN2 is processed preferentially. When the U1 detects the AD _ DIN2 signal, the high-level timer in the U1 starts to count time, and when the AD _ DIN2 signal disappears, the high-level timer in the U1 stops counting time, so that the duration of the lightning stroke is obtained; then, the U1 continuously collects AD _ DIN1 signals, and stores the collected maximum value, thereby obtaining the intensity of the lightning stroke. And the intensity and duration of the lightning stroke are displayed through LC1 for the convenience of the on-duty personnel to check. Meanwhile, the signal processing unit 3 also converts the intensity and duration of the lightning stroke into serial data and sends the serial data to the communication transmission unit 6, the communication transmission unit 6 converts the serial data into signals in an RS-485 format and is connected with the far-end terminal through an RS-485 interface, so that the intensity and waveform of each lightning stroke can be recorded on the far-end terminal, the impact current intensity on a grounding wire, a grounding branch wire and a grounding summary wire of electronic equipment or an electronic device can be conveniently obtained, the lightning protection plan of the area can be more accurately and reasonably given, corresponding lightning protection measures and the like can be designed, and the system can be ensured to run more reliably.

The utility model discloses do not describe the part unanimously with prior art, do not describe herein any more.

The above is only the embodiment of the present invention, not the limitation of the patent scope of the present invention, all the equivalent structures made by the contents of the specification and the drawings are directly or indirectly applied to other related technical fields, all the same principle is within the patent protection scope of the present invention.

Claims

1. A lightning current impact strength test circuit is characterized in that: the device comprises a signal acquisition unit (1), a signal shaping unit (2), a signal processing unit (3), a display unit (4), a power supply unit (5) and a communication transmission unit (6); the signal acquisition unit (1) is electrically connected with the signal shaping unit (2), and the signal shaping unit (2), the display unit (4) and the communication transmission unit (6) are electrically connected with the signal processing unit (3); the lightning impulse current is converted into a detectable small current signal by the signal acquisition unit (1), the signal shaping unit (2) is used for shaping a current signal sent by the signal acquisition unit (1) and converting the current signal into a voltage signal, the signal processing unit (3) obtains the intensity and the impulse waveform of lightning through the voltage signal sent by the signal shaping unit (2), and the power supply unit (5) is used for providing required direct current voltage for the signal shaping unit (2), the signal processing unit (3), the display unit (4) and the communication transmission unit (6);

the signal shaping unit (2) comprises a rectifying circuit (21), a lightning intensity extracting circuit (22) and a lightning waveform extracting circuit (23); the lightning intensity extraction circuit (22) comprises a resistor R1, a resistor R42, a resistor R44, a resistor R46, a resistor R51, a capacitor C3, a capacitor C4, a capacitor C7, an operational amplifier U7A and an operational amplifier U7B;

the positive phase input end of the operational amplifier U7A is electrically connected with a rectifying circuit (21) through a resistor R1, the positive phase input end of the operational amplifier U7A is also connected with a digital ground G _ A through a capacitor C3, the negative phase input end of the operational amplifier U7A is electrically connected with the output end thereof, and the output end of the operational amplifier U7A is electrically connected with the positive phase input end of the operational amplifier U7B through a resistor R42; the positive phase input end of the operational amplifier U7B is connected with a digital ground G _ A through a capacitor C4, the positive phase input end of the operational amplifier U7B is further connected with the digital ground G _ A through a resistor R44 and a resistor R46 in sequence, the negative phase input end of the operational amplifier U7B is electrically connected with the output end of the operational amplifier U7B, the output end of the operational amplifier U7B is electrically connected with a first end of the capacitor C7 through a resistor R51, a first end of the capacitor C7 is electrically connected with the signal processing unit (3), and a second end of the capacitor C7 is connected with the digital ground G _ A;

the lightning waveform extraction circuit (23) comprises a resistor R14, a resistor R15, a resistor R40, a resistor R48, a resistor R52, an operational amplifier U8A and an operational amplifier U8B; the positive phase input end of the operational amplifier U8A is electrically connected with the rectifying circuit (21) through a resistor R14, the negative phase input end of the operational amplifier U8A is electrically connected with the output end thereof, and the output end of the operational amplifier U8A is electrically connected with the positive phase input end of the operational amplifier U8B through a resistor R15; the positive phase input end of the operational amplifier U8B is connected with a digital ground G _ A sequentially through a resistor R40 and a resistor R48, the negative phase input end of the operational amplifier U8B is electrically connected with the output end of the operational amplifier U8B, and the output end of the operational amplifier U8B is electrically connected with the signal processing unit (3) through a resistor R52.

2. The circuit of claim 1, wherein: the operational amplifier U7A and the operational amplifier U7B are integrated in a chip U7, a power supply end of the chip U7 is connected with 5V voltage through a resistor R8, a power supply end of the chip U7 is also connected with a digital ground G _ A through a capacitor C6, and a ground end of the chip U7 is connected with the digital ground G _ A; the operational amplifier U8A and the operational amplifier U8B are integrated in a chip U8, a power supply terminal of the chip U8 is connected with 5V voltage through a resistor R12, a power supply terminal of the chip U8 is also connected with a digital ground G _ A through a capacitor C36, and a ground terminal of the chip U8 is connected with the digital ground G _ A.

3. The circuit of claim 1, wherein: the rectifying circuit (21) comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R10, a resistor R11, a bidirectional transient suppression diode D3, a bidirectional transient suppression diode D4 and a first rectifying bridge (211); the two ends of the resistor R3 are electrically connected with the signal acquisition unit (1) through an interface A1 and an interface A2 respectively, the resistor R4, the resistor R5, the resistor R6 and the bidirectional transient suppression diode D4 are all connected with the resistor R3 in parallel, the two ends of the bidirectional transient suppression diode D4 are also electrically connected with the two input ends of the first rectifier bridge (211) respectively, the positive output end of the first rectifier bridge (211) is connected with the digital G _ A through a resistor R10, the resistor R11 and the bidirectional transient suppression diode D3 are connected with the resistor R10 in parallel, and the negative output end of the first rectifier bridge (211) is connected with the digital G _ A.

4. The circuit of claim 1, wherein: the power supply unit (5) comprises a chip U2, a chip P2, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R30, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, an inductor L1, a diode D15 and a diode D16;

the power supply unit (5) further comprises a chip Q1, a chip U4, a chip U5, a chip U9, a transformer T3, a second rectifier bridge (51), a third rectifier bridge (52), a resistor R36, a resistor R39, a resistor R50, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C30, a capacitor C31, a capacitor C32, a capacitor C34, a capacitor C35, a capacitor C40, a capacitor C41 and a light-emitting diode D23;

a first output end and a second output end of the transformer T3 are respectively and electrically connected with two input ends of a second rectifier bridge (51), a positive output end of the second rectifier bridge (51) is electrically connected with a Vin pin of a chip U4, and a negative output end of the second rectifier bridge is connected with an analog ground G; the Vin pin of the chip U4 is connected with an analog ground G through a capacitor C31, the Vin pin of the chip U4 is also electrically connected with the positive terminal of a light-emitting diode D23 through a resistor R50, and the negative terminal of the light-emitting diode D23 is connected with the analog ground G; the GND pin of the chip U4 is connected with an analog ground G, the Vout pin of the chip U4 outputs an analog 3.3V voltage, the Vout pin of the chip U4 is also connected with an analog third rectifier bridge (52) ground G through a capacitor C26, and the capacitor C29 is connected with a capacitor C26 in parallel;

a third output end and a fourth output end of the transformer T3 are respectively and electrically connected with two input ends of a third rectifier bridge (52), the positive output end outputs 5V voltage, and the negative output end is connected with a digital ground G _ A; the positive output end of the third rectifier bridge (52) is electrically connected with a Vin pin of a chip U9, and the Vin pin of the chip U9 is connected with a digital ground G _ A through a capacitor C35; the GND pin of the chip U9 is connected with a digital ground G _ A, the Vout pin of the chip U9 outputs a digital 3.3V voltage, the Vout pin of the chip U9 is also connected with the digital ground G _ A through a capacitor C32, and the capacitor C34 is connected with a capacitor C32 in parallel; the Vout pin of the chip U9 is also electrically connected with the Vin pin of the chip U5, the GND pin of the chip U5 is connected with a digital ground G _ A, the Vout pin of the chip U5 outputs 2.5V voltage, the Vout pin of the chip U5 is also connected with the digital ground G _ A through a capacitor C40, and the capacitor C41 is connected with a capacitor C40 in parallel.

5. The circuit of claim 1, wherein: the signal processing unit (3) comprises a chip U1, a resistor R9, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C1, a capacitor C2, a capacitor C5, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C43, a capacitor C44 and a crystal Y1;

the OSC _ IN pin of the chip U1 is connected with an analog ground G through a capacitor C1, the OSC _ IN pin of the chip U1 is also electrically connected with the OSC _ OUT pin through a crystal Y1, and the OSC _ OUT pin of the chip U1 is connected with the analog ground G through a capacitor C2; the PA5 pin of the chip U1 is electrically connected with a first end of a capacitor C7, and the PA6 pin of the chip U1 is electrically connected with a first end of a capacitor C39; the PA8 pin, the PB5 pin, the PB6 pin, the PB7 pin, the PB8 pin and the PB9 pin of the chip U1 are respectively and electrically connected with corresponding positions of the display unit (4), and the PA2 pin, the PA3 pin and the PB12 pin of the chip U1 are respectively and electrically connected with corresponding positions of the communication transmission unit (6).

6. The lightning current surge strength test circuit according to claim 5, wherein: the display unit (4) comprises a chip U3, a chip LC1, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R37, a resistor R38, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, an inductor L2 and a diode D17;

7. The lightning current surge strength test circuit according to claim 5, wherein: the communication transmission unit (6) comprises a chip U6, a resistor R41, a resistor R43, a resistor R45, a resistor R47, a resistor R49, a capacitor C33, a capacitor C38 and a bidirectional transient suppression diode D22;

the RO pin of the chip U6 is electrically connected to the PA3 pin of the chip U1 through a resistor R43, the RE pin of the chip U6 is electrically connected to the DE pin thereof, the DE pin of the chip U6 is electrically connected to the PB12 pin of the chip U1 through a resistor R45, the DI pin of the chip U6 is electrically connected to the PA2 pin of the chip U1 through a resistor R47, the VCC pin of the chip U6 is connected to an analog 3.3V voltage, the VCC pin of the chip U6 is also electrically connected to the a pin thereof through a resistor R41, the a pin of the chip U6 is electrically connected to the interface a6, the a pin of the chip U6 is also electrically connected to the B pin thereof through a bidirectional transient suppression diode D6, the B pin of the chip U6 is electrically connected to the interface a6, the B pin of the chip U6 is also connected to an analog ground G through a capacitor C6, the resistor R6 is connected to a parallel with a capacitor C6, and the GND of the chip U6 is.