CN211327794U - Pulse control circuit, pulse generator and deep brain electrical stimulation system - Google Patents
Pulse control circuit, pulse generator and deep brain electrical stimulation system Download PDFInfo
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- CN211327794U CN211327794U CN201922407479.1U CN201922407479U CN211327794U CN 211327794 U CN211327794 U CN 211327794U CN 201922407479 U CN201922407479 U CN 201922407479U CN 211327794 U CN211327794 U CN 211327794U
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Abstract
The utility model discloses a pulse control circuit, pulse generator and deep electro photoluminescence system of brain, with prior art difference lie in, utilize the pulse to open the device and the pulse is closed the device and is controlled the pulse of pulse generation circuit output. The number of circuit components is greatly reduced, the power consumption and the fault rate of the circuit are reduced, the stability of the pulse control circuit is improved, and meanwhile, the lower power consumption can prolong the service life of an implanted battery. The stimulation precision and the pulse width control precision which are the same as the stimulation precision and the pulse width control precision which are output by using the integrated operational amplifier can be achieved by only using six field effect transistors, and the design of the circuit principle is converted from a complicated design into a simplified design with ingenious conception. In addition, the internal resistance of field effect tube among the prior art is less than 100 ohm, the utility model discloses an internal resistance improves control resolution, linearity for 1K omega's field effect tube, can realize the accurate control to stimulus pulse width and cycle under the equal precision demand.
Description
Technical Field
The utility model belongs to the technical field of implanted medical instrument, especially, relate to a pulse control circuit, pulse generator and deep electro photoluminescence system of brain.
Background
With the development of brain surgery and neuroelectronic science, Deep Brain Stimulation (DBS) can realize the neural interventional operation process without damaging brain tissues and the reversibility of treatment schemes by virtue of its clinical effect superior to that of destructive operation, and becomes the first choice treatment means for advanced parkinson disease worldwide. The existing deep brain stimulation system mainly comprises a pulse generator (IPG) implanted in a body, a stimulation electrode (Lead), an in-vivo Extension Lead (Extension), an in-vitro program control device (programmer & Remoter), a relevant surgical tool (Surgicaltool) and the like. In the system, the precise pulse stimulation of the pulse generator (IPG) implanted in the body is the basis of better treatment effect and higher reliability, and enterprises which obtain the marketing qualification of deep brain electrical stimulation equipment at home and abroad can not develop products related to the pulse generator.
Most of the existing pulse current sources of the IPG are realized by using an operational amplifier, and an internal circuit needs tens of field effect transistors, as shown in fig. 1, which is an internal circuit structure diagram of the IPG in the prior art, and the IPG has a complex circuit structure, a large number of devices and large power consumption.
High-speed logic circuits are needed to meet the requirement of accurate control of the existing pulse width and period, so that the power consumption is high. However, if the power consumption is reduced, the control precision is sacrificed, the linearity is reduced, and the accurate pulse stimulation of the IPG cannot be realized. Therefore, an IPG control circuit scheme with simple structure and low power consumption is needed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a pulse control circuit, pulse generator and deep electro photoluminescence system of brain for solve among the prior art problem that IPG's internal circuit structure is complicated, the device is various and the consumption is big.
In order to solve the above technical problem, a first aspect of the present invention provides a pulse control circuit, including a first power supply, a pulse turn-on device, a pulse turn-off device, a mirror current source, and a pulse generation circuit;
the mirror current source is provided with a first output end and a second output end;
the input end of the mirror current source is connected with the anode of the first power supply, the first output end of the mirror current source is connected with one end of the pulse starting device, the second output end of the mirror current source is connected with one end of the pulse closing device and the pulse generating circuit, and the pulse generating circuit is connected with the anode and the cathode of the first power supply;
the other end of the pulse starting device and the other end of the pulse closing device are both connected to the negative electrode of the first power supply;
the pulse generating circuit is used for outputting a third pulse signal, the pulse opening device controls the opening of the third pulse signal through a first pulse signal, and the pulse closing device controls the closing of the third pulse signal through a second pulse signal;
the first pulse signal and the second pulse signal cooperate to control the pulse width of the third pulse signal.
Optionally, the pulse turning-on device is a first field effect transistor, and the pulse turning-off device is a second field effect transistor;
the grid electrode of the first field effect transistor is used for receiving the first pulse signal, the drain electrode of the first field effect transistor is connected with the first output end, and the source electrode of the first field effect transistor is connected with the negative electrode of the first power supply;
the grid electrode of the second field effect transistor is used for receiving the second pulse signal, the drain electrode of the second field effect transistor is connected with the second output end, and the source electrode of the second field effect transistor is connected with the negative electrode of the first power supply.
Optionally, the mirror current source includes a third field effect transistor and a fourth field effect transistor;
the grid electrode of the third field effect tube is respectively connected with the grid electrode of the fourth field effect tube and the drain electrode of the third field effect tube, the source electrode of the third field effect tube is connected with the anode of the first power supply, and the drain electrode of the third field effect tube is used as the first output end and is connected with the drain electrode of the first field effect tube;
and the source electrode of the fourth field effect transistor is connected with the anode of the first power supply, and the drain electrode of the fourth field effect transistor is used as the second output end and is connected with the drain electrode of the second field effect transistor and the pulse generating circuit.
Optionally, the pulse generating circuit includes a fifth field effect transistor, a sixth field effect transistor, a first capacitor, and a voltage regulator tube;
one end of the first capacitor is connected with the cathode of the voltage regulator tube and the drain electrode of the fourth field effect tube, and the other end of the first capacitor and the source electrode of the sixth field effect tube are both connected with the cathode of the first power supply;
the source electrode of the fifth field effect transistor is connected with the anode of the first power supply, the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor are both connected with the anode of the voltage stabilizing tube, and the drain electrode of the fifth field effect transistor is connected with the drain electrode of the sixth field effect transistor and used for outputting the third pulse signal.
Optionally, the period of the third pulse signal is T, where T ═ C × R × 10, C is a capacitance value of the first capacitor, and R is a channel resistance value of the fourth field effect transistor.
Optionally, the resistance value of the channel resistor of the fourth field effect transistor is 1K Ω.
Optionally, the first field effect transistor, the second field effect transistor, and the sixth field effect transistor are all N-channel field effect transistors.
Optionally, the third field effect transistor, the fourth field effect transistor, and the fifth field effect transistor are P-channel field effect transistors.
Optionally, the frequency of the first pulse signal is 100 Hz.
Optionally, the frequency of the second pulse signal is 100 Hz.
Optionally, the first power supply is a 10V dc power supply.
A second aspect of the present invention provides a pulse generator, including any of the pulse control circuits described in the above feature description.
The third aspect of the utility model provides a deep brain electrical stimulation system, include pulse generator.
The utility model provides a pulse control circuit, pulse generator and deep electro photoluminescence system of brain, with prior art difference lie in, utilize the pulse to open the device and the pulse is closed the device and is controlled the pulse of pulse generation circuit output. The number of circuit components is greatly reduced, the power consumption and the fault rate of the circuit are reduced, the stability of the pulse control circuit is improved, and meanwhile, the lower power consumption can prolong the service life of an implanted battery.
Furthermore, the utility model provides an among the control circuit, can only utilize six field effect transistors to reach and use integrated fortune to put same output stimulation precision and pulse width control precision, realize turning into the design benefit's retrench design by numerous and diverse designs in the design of circuit principle.
In addition, the internal resistance of field effect tube among the prior art is less than 100 ohm, the utility model discloses an internal resistance is 1K omega's field effect tube, can improve control resolution and linearity, can realize the accurate control to stimulus pulse width and cycle under equal precision demand.
Drawings
FIG. 1 is a schematic diagram of an internal circuit of an IPG according to the prior art;
fig. 2 is a schematic diagram of a pulse control circuit according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a pulse control method according to another embodiment of the present invention;
100-mirror current source, 200-pulse generating circuit, T1-first field effect transistor, T2-second field effect transistor, T3-third field effect transistor, T4-fourth field effect transistor, T5-fifth field effect transistor, T6-sixth field effect transistor, D-voltage regulator, C1-first capacitor and DC-first power supply.
Detailed Description
The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "left", "right", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
As shown in fig. 2, a first aspect of the present invention provides a pulse control circuit, which includes a first power supply DC, a pulse turn-on device, a pulse turn-off device, a mirror current source 100 and a pulse generation circuit 200, wherein the mirror current source 100 has a first output terminal and a second output terminal. The input end of the mirror current source 100 is connected to the positive electrode of the first power supply DC, the first output end is connected to one end of the pulse turning-on device, and the second output end is connected to one end of the pulse turning-off device and the pulse generating circuit 200. The other end of the pulse-on device and the other end of the pulse-off device are both connected to the negative electrode of the first power supply DC. The pulse turning-on device is used for controlling a first pulse signal, and the pulse turning-off device is used for controlling a second pulse signal. The pulse generating circuit 200 is configured to output a third pulse signal, and the first pulse signal and the second pulse signal cooperate to control a pulse width of the third pulse signal.
The difference from the prior art is that the pulse output by the pulse generating circuit 200 is controlled by a pulse-on device and a pulse-off device. The number of circuit components is greatly reduced, the power consumption and the fault rate of the circuit are reduced, the stability of the pulse control circuit is improved, and meanwhile, the lower power consumption can prolong the service life of an implanted battery.
Optionally, the pulse-on device is a first fet T1, and the pulse-off device is a second fet T2. The gate of the first fet T1 is configured to receive the first pulse signal, the drain of the first fet T1 is connected to the first output terminal, and the source of the first fet T1 is connected to the negative terminal of the first power supply DC. The gate of the second fet T2 is configured to receive the second pulse signal, the drain of the second fet T2 is connected to the second output terminal, and the source of the second fet T2 is connected to the negative terminal of the first power supply DC.
The device is opened to the pulse with the device all can select for use field effect transistor is closed to the pulse, and field effect transistor's kind has a lot of, for the convenience of explanation, in the embodiment of the utility model embodiment first field effect transistor T1 and second field effect transistor T2 all can select for use N channel field effect transistor, and AO3400N channel field effect transistor can be selected for use to specific model. But is not limited to this type and other types of fets may be implemented without limitation.
The first pulse signal for controlling the first fet T1 may be regarded as a pulse-on signal, and the second pulse signal for controlling the second fet T2 may be regarded as a pulse-off signal. When the first pulse signal is applied to the gate of the first fet T1 at a low level, the first fet T1 is in an off state, and the circuit at the first output terminal is in an open state, and no current flows. According to the principle of the mirror current circuit, the circuit at the second output terminal also has no current flowing, and the pulse generating circuit 200 is in the off state and cannot send out the third pulse signal. When the first pulse signal is applied to the gate of the first fet T1 at a high level, the first fet T1 is in a conducting state, and at this time, the circuit at the first output terminal is in a conducting state, and a current flows. As can be seen from the principle of the mirror current circuit, the current of the second output terminal also flows through the same current as the current of the first output terminal, and in this case, the pulse generating circuit 200 can be powered to generate the third pulse signal. However, since the second fet T2 is connected in parallel with the pulse generating circuit 200, if the gate of the second fet T2 is given a high level at this time, the second fet T2 is in a conducting state, and the current at the second output terminal does not or only partially flow through the pulse generating circuit 200, so that the third pulse signal cannot be generated; if the gate of the second fet T2 is given a low level at this time, the second fet T2 is in an off state, the current of the second output terminal flows into the pulse generating circuit 200 completely, and the pulse generating circuit 200 can generate the third pulse signal. Therefore, it is possible to control the pulse width of the third pulse signal by the time interval of the first pulse signal and the second pulse signal.
Specifically, the mirror current source 100 may include a third fet T3 and a fourth fet T4. The gate of the third fet T3 is connected to the gate of the fourth fet T4 and the drain of the third fet T3, respectively, the source of the third fet T3 is connected to the positive electrode of the first power supply DC, and the drain of the third fet T3 is used as the first output terminal and is connected to the drain of the first fet T1. A source of the fourth fet T4 is connected to the positive terminal of the first power supply DC, and a drain of the fourth fet T4 serves as the second output terminal and is connected to the drain of the second fet T2 and the pulse generating circuit 200. In general, the mirror current source 100 can be implemented by two fets, but is not limited to this case, and other circuits or devices that can implement the same function as the mirror current source 100 can be used as alternatives or variations.
For convenience of description, in the embodiment of the present invention, the third fet T3 and the fourth fet T4 may be P-channel fets, and the specific model may be AO 6800P-channel fets. But is not limited to this type and other types of fets may be implemented without limitation.
Further, the pulse generating circuit 200 includes a fifth fet T5, a sixth fet T6, a first capacitor C1, and a voltage regulator D. One end of the first capacitor C1 is connected to the cathode of the voltage regulator D and the drain of the fourth fet T4, and the other end of the first capacitor C1 and the source of the sixth fet T6 are both connected to the negative electrode of the first power supply DC. The source electrode of the fifth field effect transistor T5 is connected to the positive electrode of the first power supply DC, the gate electrode of the fifth field effect transistor T5 and the gate electrode of the sixth field effect transistor T6 are both connected to the anode of the voltage regulator D, and the drain electrode of the fifth field effect transistor T5 is connected to the drain electrode of the sixth field effect transistor T6 and is configured to output the third pulse signal.
When the first pulse signal is applied to the gate of the first fet T1 at a low level, the first fet T1 is in an off state, and the circuit at the first output terminal is in an open state, and no current flows. According to the principle of the mirror current circuit, the circuit at the second output terminal also has no current flowing, and the pulse generating circuit 200 is in the off state and cannot send out the third pulse signal.
When the first pulse signal is applied to the gate of the first fet T1 at a high level, the first fet T1 is in a conducting state, and at this time, the circuit at the first output terminal is in a conducting state, and a current flows. As can be seen from the principle of the mirror current circuit, the current of the second output terminal also flows through the same current as the current of the first output terminal, and in this case, the pulse generating circuit 200 can be powered to generate the third pulse signal. However, since the second fet T2 is connected in parallel with the pulse generating circuit 200, if the gate of the second fet T2 is given a high level at this time, the second fet T2 is in a conducting state, and the current at the second output terminal does not or only partially flow through the pulse generating circuit 200, so that the third pulse signal cannot be generated; if the gate of the second fet T2 is given a low level at this time, the second fet T2 is in an off state, the current at the second output terminal charges the first capacitor C1, and the first capacitor C1 enters a charging process. After the charging process of the first capacitor C1 is completed, if a high level is applied to the gate of the second fet T2 at this time, the second fet T2 is in a conducting state, and the voltage across the first capacitor C1 is smaller than the charged voltage, the first capacitor C1 enters a discharging process and outputs a pulse voltage, when the discharging voltage of the first capacitor C1 is greater than the directional breakdown voltage of the regulator D, the regulator D is turned on in the reverse direction, and a high level is applied to the gates of the fifth fet T5 and the sixth fet T6, and the fifth fet T5 and the sixth fet T6 are in a conducting state, and output a pulse signal, that is, the third pulse signal.
For convenience of illustration, in the embodiment of the present invention, the fifth fet T5 can be a P-channel fet, and the sixth fet T6 can be an N-channel fet, and the specific types can be AO6800P channel fets and AO3400N channel fets. But is not limited to this type and other types of fets may be implemented without limitation. It should be noted that, in the embodiment of the present invention, the parameters of the N-channel fet and the P-channel fet should be symmetrical and complementary, and specifically, the parameters may be expressed as close absolute values of the turn-on voltages, close absolute values of the turn-on currents, close on resistances, and the like.
The period of the third pulse signal is T, where T ═ C × R × 10, C is the capacitance value of the first capacitor C1, and R is the channel resistance value of the fourth fet T4. The period of the third pulse signal can be controlled by adjusting the capacitance of the first capacitor C1 and the channel resistance of the fourth fet T4.
Optionally, the channel resistance of the fourth fet T4 is 1K Ω. Compare with field effect transistor internal resistance among the prior art is less than 100 omega, the utility model discloses an internal resistance improves control resolution, linearity for 1K omega's field effect transistor, can realize the accurate control to stimulus pulse width and cycle under the equal precision demand.
For convenience of explanation, the IPG control circuit of the present invention is described in detail by using more specific embodiments, in this embodiment, the first fet T1, the second fet T2, and the sixth fet T6 can all use AO3400N channel fets, and the third fet T3, the fourth fet T4, and the fifth fet T5 can all use AO6800P channel fets. The frequency of the first pulse signal and the second pulse signal can be 100Hz, and the first power supply DC can be 10V direct current power supply. As shown in fig. 2, the specific connection relationship of the circuit is as follows:
the positive electrode of the 12V direct-current power supply DC is connected with the sources of AO6800P channel field effect transistors T3, T4 and T5; the negative electrode of the 12V direct current power supply DC is connected with the sources of the AO3400N channel field effect transistors T1, T2 and T6 and one end of a 1uf capacitor C1 and is grounded; a cycle 100Hz pulse turn-on signal Vg is connected with the grid electrode of an AO3400N channel field effect transistor T1; the periodic 100Hz pulse off signal Voff is connected with the grid of an AO3400N channel field effect transistor T2; the gates of the AO6800P channel field effect transistors T3 and T4 are connected and connected with the drain electrode of the AO6800P channel field effect transistor T3 and the drain electrode of the AO3400N channel field effect transistor T1; the drain electrode of the AO6800P channel field effect transistor T4 is connected with the drain electrode of the AO3400N channel field effect transistor T2 and is connected with the other end of the 1uf capacitor C1 and the cathode of the 1N4743 voltage regulator tube D; the anode of the 1N4743 voltage regulator tube D is connected with the gate of the AO6800P channel field effect tube T5 and the gate of the AO3400N channel field effect tube T6; the drain of the AO6800P channel FET T5 is connected to the drain of the AO3400N channel FET T6 and connected to the periodic 100Hz output pulse Vo.
Another embodiment of the present invention provides a pulse control method, which utilizes any one of the above-mentioned feature descriptions to control a pulse circuit.
Optionally, as shown in fig. 3, the pulse control method includes:
s1: the first pulse signal is applied to the pulse-on device, the second pulse signal is applied to the pulse-off device, and the pulse generation circuit 200 outputs the third pulse signal;
s2: adjusting the time interval of the first pulse signal and the second pulse signal to control the pulse width of the third pulse signal.
The embodiment of the utility model also provides a pulse generator, including in the above-mentioned feature description arbitrary pulse control circuit.
The embodiment of the utility model also provides a deep electro photoluminescence system of brain, include pulse generator.
To sum up, the utility model provides a pulse control circuit, pulse generator and deep electro photoluminescence system of brain, with prior art difference lie in, utilize the pulse to open the device and the pulse closes the pulse that the device controlled pulse generation circuit output. The number of circuit components is greatly reduced, the power consumption and the fault rate of the circuit are reduced, the stability of the pulse control circuit is improved, and meanwhile, the lower power consumption can prolong the service life of an implanted battery.
Furthermore, the utility model provides an among the control circuit, can only utilize six field effect transistors to reach and use integrated fortune to put same output stimulation precision and pulse width control precision, realize turning into the design benefit's retrench design by numerous and diverse designs in the design of circuit principle.
In addition, the internal resistance of field effect tube among the prior art is less than 100 ohm, the utility model discloses an internal resistance is 1K omega's field effect tube, can improve control resolution and linearity, can realize the accurate control to stimulus pulse width and cycle under equal precision demand.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example" or "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. And the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.
Claims (13)
1. A pulse control circuit is characterized by comprising a first power supply, a pulse starting device, a pulse closing device, a mirror current source and a pulse generating circuit;
the mirror current source is provided with a first output end and a second output end;
the input end of the mirror current source is connected with the anode of the first power supply, the first output end of the mirror current source is connected with one end of the pulse starting device, the second output end of the mirror current source is connected with one end of the pulse closing device and the pulse generating circuit, and the pulse generating circuit is connected with the anode and the cathode of the first power supply;
the other end of the pulse starting device and the other end of the pulse closing device are both connected to the negative electrode of the first power supply;
the pulse generating circuit is used for outputting a third pulse signal, the pulse opening device controls the opening of the third pulse signal through a first pulse signal, and the pulse closing device controls the closing of the third pulse signal through a second pulse signal;
the first pulse signal and the second pulse signal cooperate to control the pulse width of the third pulse signal.
2. The pulse control circuit of claim 1 wherein said pulse turn-on device is a first fet and said pulse turn-off device is a second fet;
the grid electrode of the first field effect transistor is used for receiving the first pulse signal, the drain electrode of the first field effect transistor is connected with the first output end, and the source electrode of the first field effect transistor is connected with the negative electrode of the first power supply;
the grid electrode of the second field effect transistor is used for receiving the second pulse signal, the drain electrode of the second field effect transistor is connected with the second output end, and the source electrode of the second field effect transistor is connected with the negative electrode of the first power supply.
3. The pulse control circuit of claim 2, wherein said mirror current source comprises a third fet and a fourth fet;
the grid electrode of the third field effect tube is respectively connected with the grid electrode of the fourth field effect tube and the drain electrode of the third field effect tube, the source electrode of the third field effect tube is connected with the anode of the first power supply, and the drain electrode of the third field effect tube is used as the first output end and is connected with the drain electrode of the first field effect tube;
and the source electrode of the fourth field effect transistor is connected with the anode of the first power supply, and the drain electrode of the fourth field effect transistor is used as the second output end and is connected with the drain electrode of the second field effect transistor and the pulse generating circuit.
4. A pulse control circuit as claimed in claim 3, wherein said pulse generating circuit comprises a fifth fet, a sixth fet, a first capacitor, and a voltage regulator;
one end of the first capacitor is connected with the cathode of the voltage regulator tube and the drain electrode of the fourth field effect tube, and the other end of the first capacitor and the source electrode of the sixth field effect tube are both connected with the cathode of the first power supply;
the source electrode of the fifth field effect transistor is connected with the anode of the first power supply, the grid electrode of the fifth field effect transistor and the grid electrode of the sixth field effect transistor are both connected with the anode of the voltage stabilizing tube, and the drain electrode of the fifth field effect transistor is connected with the drain electrode of the sixth field effect transistor and used for outputting the third pulse signal.
5. The pulse control circuit according to claim 4, wherein the period of the third pulse signal is T, where T is C R10, C is a capacitance of the first capacitor, and R is a channel resistance of the fourth FET.
6. The pulse control circuit according to claim 5, wherein a channel resistance of said fourth field effect transistor is 1K Ω.
7. The pulse control circuit of claim 4 wherein said first FET, said second FET and said sixth FET are N-channel FETs.
8. The pulse control circuit as claimed in claim 4, wherein said third FET, said fourth FET and said fifth FET are P-channel FETs.
9. The pulse control circuit according to any one of claims 1 to 8, wherein the frequency of the first pulse signal is 100 Hz.
10. The pulse control circuit according to any one of claims 1 to 8, wherein the frequency of the second pulse signal is 100 Hz.
11. The pulse control circuit of any one of claims 1-8 wherein the first power supply is a 10 volt dc power supply.
12. A pulse generator comprising a pulse control circuit as claimed in any one of claims 1 to 11.
13. A deep brain electrical stimulation system comprising the pulse generator of claim 12.
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