CN211321300U - Stray current processing device - Google Patents
Stray current processing device Download PDFInfo
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- CN211321300U CN211321300U CN202020275257.9U CN202020275257U CN211321300U CN 211321300 U CN211321300 U CN 211321300U CN 202020275257 U CN202020275257 U CN 202020275257U CN 211321300 U CN211321300 U CN 211321300U
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Abstract
The utility model relates to a stray current processing apparatus, include: the buffer unit is used for receiving the pipeline signal and improving the common mode rejection ratio of the signal; the differential amplification unit is connected with the buffer unit, receives the signal output by the buffer unit and is used for carrying out differential amplification on the signal; and the voltage offset unit is connected with the differential amplification unit, receives the signal output by the differential amplification unit and is used for providing potential offset voltage for the signal. The method has the advantage of facilitating identification of the processed pipeline signal.
Description
Technical Field
The utility model belongs to the technical field of stray current technique and specifically relates to a stray current processing apparatus is related to.
Background
The current direct drainage, polar drainage and forced drainage methods recommended by the national standard need to electrically connect a pipeline and an electric railway return line, and generally have the defects of possibly causing interference on railway transmission signals and threatening the safe operation of railways. The railway is required to adopt more complicated anti-interference measures, and the adoption of the drainage methods is often rejected by the railway. Therefore, the grounding drainage method is widely applied in China.
Although the ground drainage method has less interference on railways, the buried pipeline is directly connected with the grounding electrode, so that the invasion of interference current cannot be blocked, interference inflow can be blocked after polar drainage is introduced, meanwhile, the impedance of a drainage branch is increased, and the drainage effect is poor.
Before current drainage, a pipeline signal needs to be processed, an identification signal is not generated in the existing scheme, the current drainage is realized through the forward voltage drop characteristic (0.7V) of a diode, the diode is opened when the voltage difference is larger than the forward voltage drop, different opening values are obtained through 0.7 x n, and the opening point is often not matched with the actual requirement.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a stray current processing apparatus, which has the advantage of facilitating the identification of the processed pipeline signal.
A stray current handling apparatus comprising: the buffer unit is used for receiving the pipeline signal and improving the common mode rejection ratio of the signal; the differential amplification unit is connected with the buffer unit, receives the signal output by the buffer unit and is used for carrying out differential amplification on the signal; and the voltage offset unit is connected with the differential amplification unit, receives the signal output by the differential amplification unit and is used for providing potential offset voltage for the signal.
Further, the buffer unit comprises a first operational amplifier a1 and a second operational amplifier a2, wherein a positive input terminal of the first operational amplifier a1 is connected to the pipeline signal, a positive input terminal of the second operational amplifier a2 is connected to the reference electrode, an inverting input terminal of the first operational amplifier a1 is connected to an inverting input terminal of the second operational amplifier a2, an output terminal of the first operational amplifier a1 is connected to an inverting input terminal of the first operational amplifier a1, and an output terminal of the second operational amplifier a2 is connected to an inverting input terminal of the second operational amplifier a 2.
Further, the differential amplifying unit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the first resistor R1 is connected between the inverting input terminal of the first operational amplifier a1 and the inverting input terminal of the second operational amplifier a2, the second resistor R2 is connected between the output terminal of the second operational amplifier a2 and the inverting input terminal of the second operational amplifier a2, the third resistor R3 is connected between the output terminal of the first operational amplifier a1 and the inverting input terminal of the first operational amplifier a1, the fourth resistor R4 and the seventh resistor R7 are connected in series to the output terminal of the first operational amplifier a1, and the fifth resistor R5 and the sixth resistor R6 are connected in series to the output terminal of the second operational amplifier a 2.
Further, the voltage offset unit includes a third operational amplifier A3 and a voltage generator T, wherein an inverting input terminal of the third operational amplifier A3 is connected between the fourth resistor R4 and the seventh resistor R7, a non-inverting input terminal of the third operational amplifier A3 is connected between the fifth resistor R5 and the sixth resistor R6, and an output terminal of the voltage generator T is connected to the sixth resistor R6.
Furthermore, the device also comprises an interference impact preventing unit which is connected in front of the buffer unit and is used for filtering interference current.
Furthermore, the anti-interference and impact unit comprises a discharge tube K, a piezoresistor RV, a bidirectional transient suppression diode Q, a first inductor L1, a second inductor L2, a third inductor L3 and a fourth inductor L4, wherein the first inductor L1 is connected in series with the second inductor L2, the third inductor L3 is connected in series with the fourth inductor L4, the first inductor L1 is connected with a pipeline signal, the third inductor L3 is grounded, two ends of the discharge tube K are respectively connected with one end of the first inductor L1 and one end of the third inductor L3, two ends of the piezoresistor RV are respectively connected between the first inductor L1 and the second inductor L2 and between the third inductor L3 and the fourth inductor L4, and the bidirectional transient suppression diode Q is respectively connected with one end of the second inductor L2 and one end of the fourth inductor L4.
To sum up, the utility model discloses a following at least one useful technological effect: the pipeline signal processed is convenient to identify, and therefore drainage efficiency of later-stage stray current is improved.
Drawings
Fig. 1 is a circuit diagram of the present invention.
In the figure, 1, a buffer unit; 2. a differential amplification unit; 3. a voltage offset unit; 4. an interference impact prevention unit.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
The utility model discloses a stray current processing apparatus, include:
the buffer unit 1 is used for receiving pipeline signals and improving the common mode rejection ratio of the signals;
the differential amplification unit 2 is connected with the buffer unit 1, receives the signal output by the buffer unit 1, and is used for differentially amplifying the signal;
the voltage offset unit 3 is connected with the differential amplification unit 2, receives the signal output by the differential amplification unit 2, and is used for providing a potential offset voltage for the signal;
and the interference impact preventing unit 4 is connected in front of the buffer unit 1 and is used for filtering interference current.
As shown in fig. 1, the buffer unit 1 includes a first operational amplifier a1 and a second operational amplifier a2, wherein a positive input terminal of the first operational amplifier a1 is connected to the pipeline signal, a positive input terminal of the second operational amplifier a2 is connected to the reference electrode, a negative input terminal of the first operational amplifier a1 is connected to a negative input terminal of the second operational amplifier a2, an output terminal of the first operational amplifier a1 is connected to a negative input terminal of the first operational amplifier a1, and an output terminal of the second operational amplifier a2 is connected to a negative input terminal of the second operational amplifier a 2.
The differential amplifying unit 2 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the first resistor R1 is connected between the inverting input terminal of the first operational amplifier a1 and the inverting input terminal of the second operational amplifier a2, the second resistor R2 is connected between the output terminal of the second operational amplifier a2 and the inverting input terminal of the second operational amplifier a2, the third resistor R3 is connected between the output terminal of the first operational amplifier a1 and the inverting input terminal of the first operational amplifier a1, the fourth resistor R4 and the seventh resistor R7 are connected in series to the output terminal of the first operational amplifier a1, the fifth resistor R5 and the sixth resistor R6 are connected in series to the output terminal of the second operational amplifier a2, and the seventh resistor R7 is connected to the drain performing structure.
The voltage offset unit 3 includes a third operational amplifier A3 and a voltage generator T, an inverting input terminal of the third operational amplifier A3 is connected between the fourth resistor R4 and the seventh resistor R7, a non-inverting input terminal of the third operational amplifier A3 is connected between the fifth resistor R5 and the sixth resistor R6, and an output terminal of the voltage generator T is connected to the sixth resistor R6.
The anti-interference impact unit 4 comprises a discharge tube K, a piezoresistor RV, a bidirectional transient suppression diode Q, a first inductor L1, a second inductor L2, a third inductor L3 and a fourth inductor L4, the first inductor L1 is connected with the second inductor L2 in series, the third inductor L3 is connected with the fourth inductor L4 in series, the first inductor L1 is connected with a pipeline signal, the third inductor L3 is grounded, two ends of the discharge tube K are respectively connected with one end of the first inductor L1 and one end of the third inductor L3, two ends of the piezoresistor RV are respectively connected between the first inductor L1 and the second inductor L2 and between the third inductor L3 and the fourth inductor L4, and the bidirectional transient suppression diode Q is respectively connected with one end of the second inductor L2 and one end of the fourth inductor L4.
The implementation principle of the embodiment is as follows:
interference impact prevention unit 4, by discharge tube K and piezo-resistor RV and first inductance L1, second inductance L2, third inductance L3, surge impact prevention device is constituteed such as fourth inductance L4, interference impact passes through first inductance L1 and second inductance L2 decoupling after discharge tube K releases the low current, again through piezo-resistor RV second grade release, finally again through third inductance L3, meticulous protection is done to fourth inductance L4 and two-way transient suppression diode Q, can filter most impact interference, reach better interference current and release, protection equipment can bear possible various surge impact interference under the field condition.
The pipeline signal and the reference electrode signal are respectively input into a first operational amplifier A1 and a second operational amplifier A2 to form an input buffer circuit, the common mode rejection ratio of the signals is improved, the signals are precisely paired through a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7 to form precise differential amplification, and the input signals possibly have positive potential and negative potential, so that the whole circuit provides potential offset voltage through a voltage generator T, the signals are convenient for MCU identification, C _ P _ OUT signals are output, the C _ P _ OUT signals are input into a drainage execution mechanism, and intelligent drainage on demand is realized by an MCU in the drainage execution mechanism according to a preset algorithm.
The embodiment of this specific implementation mode is the preferred embodiment of the present invention, not limit according to this the utility model discloses a protection scope, so: all equivalent changes made according to the structure, shape and principle of the utility model are covered within the protection scope of the utility model.
Claims (6)
1. A stray current handling apparatus, comprising:
the buffer unit (1) is used for receiving the pipeline signal and improving the common mode rejection ratio of the signal;
the differential amplification unit (2) is connected with the buffer unit (1), receives the signal output by the buffer unit (1), and is used for carrying out differential amplification on the signal;
and the voltage offset unit (3) is connected with the differential amplification unit (2), receives the signal output by the differential amplification unit (2), and is used for providing a potential offset voltage for the signal.
2. Stray current handling device according to claim 1, characterized in that said buffer unit (1) comprises a first operational amplifier a1 and a second operational amplifier a2, the non-inverting input of said first operational amplifier a1 being connected to a pipeline signal, the non-inverting input of said second operational amplifier a2 being connected to a reference electrode, the inverting input of said first operational amplifier a1 being connected to the inverting input of said second operational amplifier a2, the output of said first operational amplifier a1 being connected to the inverting input of said first operational amplifier a1, the output of said second operational amplifier a2 being connected to the inverting input of said second operational amplifier a 2.
3. Stray current handling device according to claim 2, characterized in that the differential amplifying unit (2) comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, the first resistor R1 is connected between the inverting input terminal of the first operational amplifier a1 and the inverting input terminal of the second operational amplifier a2, the second resistor R2 is connected between the output terminal of the second operational amplifier a2 and the inverting input terminal of the second operational amplifier a2, the third resistor R3 is connected between the output terminal of the first operational amplifier a1 and the inverting input terminal of the first operational amplifier a1, the fourth resistor R4 and the seventh resistor R7 are connected in series with the output terminal of the first operational amplifier A1, the fifth resistor R5 and the sixth resistor R6 are connected in series with the output end of the second operational amplifier A2.
4. Stray current handling device according to claim 3, characterized in that said voltage offset unit (3) comprises a third operational amplifier A3 and a voltage generator T, the inverting input of said third operational amplifier A3 being connected between a fourth resistor R4 and a seventh resistor R7, the non-inverting input of said third operational amplifier A3 being connected between a fifth resistor R5 and a sixth resistor R6, the output of said voltage generator T being connected to said sixth resistor R6.
5. Stray current handling device according to claim 4, characterized by further comprising an interference impulse prevention unit (4) connected before said buffer unit (1) for filtering interference currents.
6. The stray current processing device according to claim 5, wherein said anti-interference unit (4) comprises a discharge tube K, a voltage dependent resistor RV, a bidirectional transient suppression diode Q, a first inductor L1, a second inductor L2, a third inductor L3 and a fourth inductor L4, said first inductor L1 is connected in series with said second inductor L2, said third inductor L3 is connected in series with said fourth inductor L4, said first inductor L1 is connected with the pipeline signal, said third inductor L3 is grounded, two ends of said discharge tube K are respectively connected with one end of said first inductor L1 and one end of said third inductor L3, two ends of said voltage dependent resistor RV are respectively connected between said first inductor L1 and said second inductor L2 and between said third inductor L3 and said fourth inductor L4, and said bidirectional transient suppression diode Q is respectively connected with one end of said second inductor L2 and one end of said fourth inductor L4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020275257.9U CN211321300U (en) | 2020-03-07 | 2020-03-07 | Stray current processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020275257.9U CN211321300U (en) | 2020-03-07 | 2020-03-07 | Stray current processing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211321300U true CN211321300U (en) | 2020-08-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020275257.9U Active CN211321300U (en) | 2020-03-07 | 2020-03-07 | Stray current processing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211321300U (en) |
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2020
- 2020-03-07 CN CN202020275257.9U patent/CN211321300U/en active Active
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