CN211293947U - FPGA prototype verification device - Google Patents

Abstract

The utility model provides a FPGA prototype verification device, include: the system comprises a control panel 1, a network port interface board 2, a PCIE interface board 5, a bottom plate frame 16, a user interface board bracket 24, a user interface board 25, a main body board 35, a power input board 39, a rear frame 40, a right frame 41, a front frame 42, a left frame 44, a user front panel 64 and a power board; the power input board 39 supplies power to the control board 1 and the power board, respectively; in the power-on process of the FPGA prototype verification device, the control power input board 39 firstly supplies power to the control board 1 and then supplies power to the power board; in the power-down process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board 39 to disconnect the power supply of the power board firstly and then disconnect the power supply of the control board 1. The utility model discloses part control panel 1 and main part board 35's power, made things convenient for the maintenance to the order of going up electricity and lower electricity has been distinguished, the security of FPGA prototype verification device has been improved on the whole.

Description

FPGA prototype verification device

Technical Field

The utility model relates to a prototype verification field, especially a FPGA prototype verification device.

Background

At present, the prototype verification of a Field Programmable Gate Array (FPGA) can not only accelerate the development of ASIC and other designs, shorten the research and development period, reduce the development cost of an ASIC application system, but also improve the success rate of tape-out.

However, the existing FPGA prototype verification device is not a system, but a single-board bare type, and the verification device in this type has the disadvantages of large occupied area, low resource utilization rate, few functions, poor safety due to only one power supply, and inconvenient maintenance.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides an FPGA prototype verification device that overcomes or at least partially solves the above-mentioned problems.

The embodiment of the utility model provides a FPGA prototype verification device, include: the system comprises a control panel 1, a network port interface board 2, a PCIE interface board 5, a bottom plate frame 16, a user interface board bracket 24, a user interface board 25, a main body board 35, a power input board 39, a rear frame 40, a right frame 41, a front frame 42, a left frame 44, a user front panel 64 and a power board;

the control board 1 is fixed on the bottom board frame 16 and used for managing the working state of the FPGA prototype verification device;

the control board 1 is respectively connected with the network port interface board 2 and the PCIE interface board 5, the network port interface board 2 and the PCIE interface board 5 are fixed on the bottom board frame 16, the network port interface board 2 is used for communicating with an upper computer through a network port of the network port interface board 2, and the PCIE interface board 5 is used for supporting a simulation test through an interface of the PCIE interface board 5;

the user interface board 25 is fixed on the user interface board support fixing plane 18 on the bottom plate frame 16 through the user interface board support 24, and is used for providing an external interface for a user;

the power input board 39 is fixed on the rear frame 40 and used for supplying power to the FPGA prototype verification device;

the power panel includes: the power supply A board 36 and the power supply B board 37 are fixed on the front frame 42 and the rear frame 40 and are used for providing different levels of working voltage for the main body board 35;

the user front panel 64 is fixed on the front frame 42 and is used for providing a control function for a user;

the main body board 35 is connected to the front frame 42, the rear frame 40, the left frame 44 and the right frame 41, respectively, and is configured to complete all functions of the FPGA prototype verification apparatus and provide an expansion port for a user to connect a daughter board to complete functions required by the user;

wherein the power input board 39 supplies power to the control board 1 and the power board, respectively;

in the process of powering on the FPGA prototype verification device, the FPGA prototype verification device controls the power input board 39 to supply power to the control board 1 first and then to supply power to the power board;

in the power-down process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board 39 to disconnect the power supply of the power board first and then disconnect the power supply of the control board 1.

Optionally, the control board 1, the power board, the user interface board 25 and the main body board 35 are spatially parallel to each other, and the control board 1, the user interface board 25 and the main body board 35 respectively provide at least two different types of external user interfaces.

Optionally, the control board 1 comprises: DDR3 memory socket 6, ZYNQ chip 7, high speed FireFly socket 8, power module 9, user front panel connection socket 10, ZYNQ JTAG11 slot, control panel power input interface 12, power input board connection socket 13, SD Card slot 52, Micro SD Card slot;

the DDR3 memory socket 6, the high-speed FireFly socket 8, the power module 9, the user front panel connection socket 10, the ZYNQ JTAG11 slot, the control board power input interface 12, the power input board connection socket 13, the SD Card slot 52 and the Micro SD Card slot are all connected with the ZYNQ chip 7;

the power module 9 converts the voltage supplied from the power input board 39 into different levels of operating voltages to supply the control board 1.

Optionally, the control board 1 further includes: the control panel 1 is connected with the network interface board 2 and the PCIE interface board 5 through the MINI interface card slot respectively;

the network port interface board 2 includes: kilomega network port, UART interface and USB interface;

the PCIE interface board 5 includes: a PCIE interface;

the gigabit network port, the UART interface, the USB interface and the PCIE interface are all connected with the ZYNQ chip 7.

Optionally, the main body plate 35 includes: the device comprises a connecting slot, a main body board high-speed FireFly socket, an FPGA chip, an HSPI2 socket 22, a main body board JTAG maintenance hole 23, a main body board DDR4 socket 30, a DDR3 socket 31, a main body board QTH socket 32, a main body board key 33 and a main body board dial switch 34;

the connecting slot and the main body board high-speed FireFly socket face the control board 1 and are connected with an FPGA chip, and the HSPI2 socket 22, the main body board JTAG maintenance hole 23, the main body board DDR4 socket 30, the DDR3 socket 31, the main body board QTH socket 32, the main body board key 33 and the main body board dial switch 34 all face away from the control board 1 and are connected with the FPGA chip;

the main body board 35 is connected with the power supply a board 36 and the power supply B board 37 through the connection slot, so that the power supply a board 36 and the power supply B board 37 provide different levels of working voltages for the main body board 35 and the FPGA chip;

the communication between the main body board 35 and the control board 1 is completed by connecting the flat cables to the respective high-speed FireFly sockets.

Optionally, the user interface board 25 includes: QSFP optical port 26, FPGA JTAG interface 28, UART interface 27, user interface board high-speed FireFly slot;

the user interface board 25 is connected to the main body board 35 through the user interface board high-speed FireFly slot.

Optionally, the user front panel 64 includes: a kit selection key (54), a system indicator light 56, a power switch key 51 and a clock socket 55;

the user front panel 64 is connected to the control panel 1 through the user front panel connection socket 10.

Alternatively, the power input board 39 includes: 24PIN ATX power input interface 57, 6PIN input interface 58 and 4PIN input interface;

the 24PIN ATX power input interface 57 is connected with an external power supply;

the 4PIN input interface supplies power to the control board 1;

the 6PIN input interface 58 provides power to the power strip.

Optionally, the FPGA prototype verification apparatus further includes: an upper frame 29, a front frame casing 43, a left frame casing 45, a rear frame casing 46, and a right frame casing 47;

the front frame 42 is fixed on the front frame fixing plane 19 of the bottom plate frame 16; the rear frame 40 is fixed on the rear frame fixing plane 21 of the bottom plate frame 16; the left frame 44 is fixed to the left frame fixing plane 20 on the bottom plate frame 16; the right frame 41 is fixed on the right frame fixing plane 17 on the bottom plate frame 16;

the left frame shell 45 is mounted on the left frame 44, the right frame shell 47 is mounted on the right frame 41, the front frame shell 43 is mounted on the front frame 42, and the rear frame shell 46 is mounted on the rear frame 40;

the upper frame 29 is connected to the front frame 42, the rear frame 40, the left frame 44, and the right frame 41, respectively;

the upper frame 29, the front frame casing 43, the left frame casing 45, the rear frame casing 46 and the right frame casing 47 are provided with holes corresponding to positions of all the leaked interfaces, or sockets, or slots in the FPGA prototype verification apparatus.

Optionally, the FPGA prototype verification apparatus further includes: a fan module;

the fan module is fixed on the left frame 44 and the right frame 41 through the left frame shell 45 and the right frame shell 47 respectively, a protective cover is arranged outside a fan blade of the fan module, and the fan module is used for dissipating heat of the FPGA prototype verification device.

Optionally, the FPGA prototype verification apparatus further includes: a battery pack; the preceding, back both ends of bottom plate frame 16 have all been seted up: a handle 15, an electrostatic fixing hole 14 and a rubber pad fixing hole 63;

a Mirco SD Card replacing hole 60 is formed in the bottom plate frame 16 corresponding to a slot position of a Mirco SD Card in the control plate 1, a battery replacing hole 62 is formed in the position corresponding to the battery pack, and a wiring hole 61 for replacing wiring is further formed;

the lifting handle 15 is used for carrying the FPGA prototype verification device;

the static fixing hole 14 is used for being connected with an external static grounding device and releasing static electricity generated by the FPGA prototype verification device;

the rubber pad fixing hole 63 is used for installing a rubber pad, so that the FPGA prototype verification device is placed on the table top of the FPGA prototype verification device in a soft contact mode.

Optionally, the FPGA prototype verification apparatus further includes: a guard post 48;

the protection posts 48 are respectively mounted on the front frame 42 and the rear frame 40, and are used for preventing all leaked interfaces, sockets or slots in any one of the above FPGA prototype verification apparatuses from being damaged.

Optionally, the FPGA prototype verification apparatus further includes: at least one plexiglass mount 49, plexiglass 50 and fixing tabs 59;

the organic glass bracket 49 is mounted on the upper frame 29;

in the case where only one of the plexiglass holders 49 is used, the plexiglass 50 is mounted on the plexiglass holder 49;

in the case of using two of the plexiglass brackets 49, after the two plexiglass brackets 49 are fixed by the fixing pieces 59, the plexiglass 50 is mounted on the two plexiglass brackets 49.

Optionally, all the components in the FPGA prototype verification apparatus have unique corresponding connection interfaces, and the connection interfaces of the components connected with each other correspond to each other, so as to prevent component installation errors.

In the FPGA prototype verification device provided by the utility model, the power input board 39 supplies power to the control board 1 and the power board respectively, and then supplies power to the main body board 35 through the power board; in the power-on process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board 39 to supply power to the control board 1 firstly and then to supply power to the power board; in the power-down process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board 39 to disconnect the power supply of the power board firstly and then disconnect the power supply of the control board 1, namely, the power supplies of the control board 1 and the main body board 35 are separated, when one board has a problem, the power can be cut off independently for replacement or maintenance, the maintenance is convenient, the power-up and power-down sequence is distinguished, the problem that the main body board 35 is powered up before the control board 1 is powered up and the control board 1 is powered down before the main body board 35 is powered down is avoided, and the safety of the FPGA prototype verification device is improved on the whole.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a schematic structural diagram of an isometric view of an FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram corresponding to a front view of an FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram corresponding to a rear view of an FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram corresponding to the left view of the FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram corresponding to a right view of an FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of the bottom view of the FPGA prototype verification device according to an embodiment of the present invention

Fig. 7 is a schematic structural diagram corresponding to a top view of an FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram corresponding to the front view of the control board 1 in the FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a front view and a left view of a user interface board 25 and a user interface board bracket 24 in the FPGA prototype verification apparatus according to an embodiment of the present invention;

fig. 10 is a schematic diagram of an internal structure of the FPGA prototype verification apparatus according to an embodiment of the present invention when the main body board 35 is not installed.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description. It should be understood that the specific embodiments described herein are merely illustrative of the present invention, and are not intended to limit the present invention.

The inventor finds that most of the current FPGA prototype verification devices are arranged in a plane manner, and although there are spatial FPGA prototype verification devices, the current spatial FPGA prototype verification devices can provide fewer user interfaces and fewer natural functions, and the power supply board of the whole device is vertically arranged, so that the space resource utilization rate of the whole device is low. And due to the power supply mode, when one board has a problem, the power supply cannot be independently cut off for replacement or maintenance, the maintenance is very inconvenient, the problem that the main body board is powered on before the control board is powered off and the control board is powered off before the main body board is powered off can also occur, and the safety of the FPGA prototype verification device is poor.

In addition, the conventional FPGA prototype verification device is still in a naked state and is easy to accumulate dust, static electricity generated by the device is not released in a loop, so that the problems of short circuit and the like are caused, the design of convenient carrying is not provided, various leaked interfaces are easy to damage in the carrying process, and due to the naked state, a table top for placing the FPGA prototype verification device is easy to scratch, fan blades of a fan for heat dissipation are not protected, and a user is easy to scratch.

Based on all kinds of above problems, the inventor has done diligent research, combines the characteristics of present FPGA prototype verification device, through a large amount of tests and calculation on the spot, the bold, creative proposition the utility model discloses an FPGA prototype verification device has solved above-mentioned problem. The solution proposed by the inventors is explained and illustrated in detail below.

Referring to fig. 1, there is shown an isometric corresponding schematic structural diagram of an FPGA prototype verification apparatus according to an embodiment of the present invention, where the schematic structural diagram includes: the structure schematic diagram shows a view in an isometric corresponding direction after the whole FPGA prototype verification device is additionally provided with the organic glass 50 through two organic glass supports 49. The control board 1, the network interface board 2, the PCIE (peripheral component Interconnect Express) interface board 5, the user interface board 25, the main body board 35, the power input board 39, the rear frame 40, the right frame 41, the front frame 42, the left frame 44, and the power board are all inside and are not visible in the view, and each part will be described below.

Referring to fig. 2, a schematic structural diagram corresponding to a front view of an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 3, a schematic structural diagram corresponding to a rear view of an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 4, a schematic structural diagram corresponding to a left view of an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 5, a schematic structural diagram corresponding to a right view of an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 6, a schematic structural diagram corresponding to a bottom view of an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 7, a schematic structural diagram corresponding to a top view of an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 8, a schematic structural diagram corresponding to a front view of a control board 1 in an FPGA prototype verification apparatus according to an embodiment of the present invention is shown; referring to fig. 9, a schematic structural diagram showing a front view and a left view of a FPGA prototype verification device after a user interface board 25 is combined with a user interface board bracket 24 according to an embodiment of the present invention is shown; referring to fig. 10, a schematic diagram of an internal structure of the FPGA prototype verification apparatus according to an embodiment of the present invention is shown when the main body board 35 is not installed. All the identified elements in the above figures are respectively:

control board 1, network interface board 2, network interface 3, PCIE interface 4, PCIE interface board 5, DDR3(Double Data Rate synchronous dynamic random access memory) memory socket 6, ZYNQ chip 7, High-Speed interface (FireFly) socket 8, power module 9, user front panel connection socket 10, ZYNQ JTAG slot 11, control board power input interface 12, power input board connection socket 13, static fixing hole 14, handle 15, bottom board frame 16, right frame fixing plane 17, user interface board support fixing plane 18, front frame fixing plane 19, left frame fixing plane 20, rear frame fixing plane 21, HSPI2(High Speed prototype interface) socket 22, main board JTAG maintenance hole 23, user interface board support 24, user interface board 25, fp (Quad Small Form-factor plug, four-channel SFP interface) UART 26, Universal transceiver/adaptor, universal asynchronous receiver/transmitter) interface 27, FPGAJTAG interface 28, upper frame 29, main body board DDR4 socket 30, main body board DDR3 socket 31, main body board high speed (QTH) socket 32, main body board key 33, main body board dip switch 34, main body board 35, power a board 36, power B board 37, power board-to-main body board connection socket 38, power input board 39, rear frame 40, right frame 41, front frame 42, front frame housing 43, left frame 44, left frame housing 45, rear frame housing 46, right frame housing 47, protection column 48, plexiglass bracket 49, plexiglass 50, power switch key 51, SD Card slot 52, system reset key 53, kit selection key 54, clock socket 55, system indicator lamp 56, 24PIN ATX power input interface 57, 6PIN input interface 58, fixing plate 59, Mirco SD Card replacement hole 60, wiring hole 61, battery hole 62, rubber pad fixing hole 63, wiring hole 63, and rubber pad fixing hole 63, A user front panel 64.

With reference to fig. 2 to 10, a schematic structural diagram corresponding to a front view of a control board 1 in the FPGA prototype verification apparatus shown in fig. 8 is used to describe the FPGA prototype verification apparatus, where the control board 1 is fixed on a bottom board frame 16 for managing an operating state of the FPGA prototype verification apparatus, that is, the bottom board frame 16 is a bottom layer of the entire FPGA prototype verification apparatus, the control board 1 is on the bottom board frame 16, a back surface of the control board 1 directly contacts with the bottom board frame 16, and a front surface of the control board 1 faces the inside of the FPGA prototype verification apparatus.

The control panel 1 is connected with the network interface board 2 and the PCIE interface board 5 through the MINI interface card slot respectively, and the network interface board 2 and the PCIE interface board 5 are also fixed on the bottom plate frame (16), the network interface board 2 includes: the FPGA prototype verification device comprises a network port 3, a UART interface and a USB interface, wherein the interfaces are all used for connecting an upper computer (such as a PC) so as to enable the FPGA prototype verification device to be communicated with the upper computer; the PCIE interface board 5 includes: the PCIE interface is connected with a high-speed interface of an external hardware simulation accelerator and used for supporting the simulation test of the FPGA prototype verification device; the interfaces included in the network port interface board 2 and the PCIE interface board 5 are all exposed to the back of the FPGA prototype verification apparatus, and specific interfaces are described below, which is not described in detail first.

On the control panel 1, comprising: DDR3 memory socket 6, which has two sockets for inserting DDR3 memory; the ZYNQ chip 7 is a miniaturized FPGA chip, an ARM core and an integrated element are contained in the chip, the ZYNQ chip 7 is connected with all sockets, interfaces and slots on the control panel 1, and is also connected with the network port 3 and the PCIE interface 4 and used for operating a management system to manage the whole FPGA prototype verification device; the high-speed FireFly socket 8 comprises four sockets in total, one end of a flat cable is inserted on the high-speed FireFly socket, and the other end of the flat cable is inserted on the main body board 35, so that the communication between the control board 1 and the main body board 35 is realized; the power module 9 is used for converting the voltage provided by the power input board 39 into different levels of operating voltages to supply to the control board 1, because the control board 1 needs to provide different levels of voltages according to the user's requirements during normal operation, and thus the power module 9 is required to implement this function.

The control board 1 controls the FPGA prototype verification device and an upper computer, for example: the communication of the PC and the communication of the ZYNQ chip 7 and the FPGA are controlled, the ZYNQ chip 7 is positioned in a bridge in the middle, a hardware embedded system is placed in the ZYNQ chip 7 of the control panel 1, the communication with the PC is carried out through the network port 3 or the PCIE interface 4, and the corresponding software is placed in the PC, so that the integrity of the whole prototype verification system is achieved.

The user front panel connecting socket 10 is used for connecting the control panel 1 and the user front panel 64, and parts on the user front panel 64 also need to be connected to the control panel 1 to play corresponding functional roles; the ZYNQ JTAG slot 11 is a device for externally debugging ZYNQ, and the ZYNQ chip 7 can be debugged by the debugging device, for example: downloading, uploading, etc.; the control board power input interface 12 is connected with the control line of the power supply, and the control line is separated from the power line for supplying the power supply in consideration of safety and controllability because the power supply of the control board is provided with the control line, so the control board power input interface 12 is connected with the control line of the power supply, and is connected with the power input board 39 by using the power input board connecting socket 13, the power supply is specially supplied for the control board 1, and the supplied power supply is converted into working voltages of different grades by the power supply module 9. The SD Card slot 52 is for inserting the SD Card, and the SDCard generally stores data that the user needs to debug and verify.

The static fixing holes 14, the lifting handle 15, the right frame fixing plane 17, the user interface board support fixing plane 18, the front frame fixing plane 19, the left frame fixing plane 20 and the rear frame fixing plane 21 are all located on the bottom plate frame 16, wherein the static fixing holes 14 are used for being connected with an external static eliminating device and used for eliminating static electricity generated by the FPGA prototype verification device; the handle 15 is used for conveniently carrying the FPGA prototype verification device and is provided with anti-skidding and injury-preventing devices; the right frame fixing plane 17, the front frame fixing plane 19, the left frame fixing plane 20 and the rear frame fixing plane 21 are places for fixing the front frame, the rear frame, the left frame and the right frame on the bottom plate frame 16, and the front frame, the rear frame, the left frame and the right frame of the FPGA prototype verification device are all fixed perpendicular to the bottom plate frame 16, so that a three-dimensional structural framework of the FPGA prototype verification device is formed.

The user interface board bracket fixing plane 18 is used for fixing the user interface board bracket 24 and the bottom plate frame 16, and after the user interface board bracket 24 is fixed, the control panel 1 is parallel to the user interface board 25, and referring to fig. 9, the user interface board 25 includes: QSFP optical port 26, UART interface 27, FPGA JTAG interface 28, user interface board high speed interface (FireFly) slot, wherein QSFP optical port 26, UART interface 27, FPGA JTAG interface 28 all leak to the front of FPGA prototype verification device, provide for the user to use; the user interface board 25 is connected to the main body board 35 through a user interface board high-speed FireFly slot.

Referring to fig. 7, the main body board 35 is connected to the front frame 42, the rear frame 40, the left frame 44 and the right frame 41, respectively, for performing all functions of the FPGA prototype verification apparatus, and providing an expansion port for a user, so that the user can connect to the daughter board to perform functions that the user needs to perform; of course, it can be understood that the main body board 35 is spatially parallel to the control board 1 and the user interface board 25, and after the main body board 35 is combined with the upper frame 29, it is equivalent to form the top layer of the FPGA prototype verification apparatus, and the upper frame 29 is connected to the front frame 42, the rear frame 40, the left frame 44, and the right frame 41 respectively; the side of the main body plate 35 facing the control board 1 includes: the device comprises a connecting slot, a main body board high-speed FireFly socket, an FPGA chip and a Micro SD Card slot; the side of the main body board 35 opposite to the control board 1 is the side which can be seen when looking down the FPGA prototype verification apparatus, and includes: HSPI2 socket 22, body board JTAG service hole 23, body board DDR4 socket 30, DDR3 socket 31, body board QTH socket 32, body board keys 33, body board dip switches 34.

The connection slot, the main body board high-speed FireFly socket, the Micro SD Card slot, the HSPI2 socket 22, the main body board JTAG maintenance hole 23, the main body board DDR4 socket 30, the main body board DDR3 socket 31, the main body board QTH socket 32, the main body board key 33 and the main body board dial switch 34 are all connected with the FPGA chip; meanwhile, the main body board 35 is connected with the power supply a board 36 and the power supply B board 37 through the connection slot, so that the power supply a board 36 and the power supply B board 37 provide different levels of working voltages for the main body board 35 and the FPGA chip; the main body board high-speed FireFly socket is described above and is used for connecting with the control board 1 to communicate; inserting a Micro SD Card into the Micro SD Card slot; the HSPI2 socket 22 is used for leading out resources of the FPGA for a user to expand a peripheral interface; the main board JTAG maintenance hole 23 is used when the FGPA needs to be debugged or maintained in an emergency; the main body board DDR4 socket 30 and the main body board DDR3 socket 31 are both used for inserting memory inserts, and the memory capacity of the FPGA prototype verification device is greatly expanded; main body board QTH socket 32, main body board button 33, main body board dip switch 34 all provide the user with the use, and the user can self-define the function of these socket, button, dip switch.

Referring to fig. 7, the figure shows the schematic diagram of the internal structure when the control board 1, the user interface board 25, the power a board 36, the power B board 37 are installed, and the main body board 25 is not installed, wherein the power a board 36 and the power B board 37 are both fixed on the front frame 42 and the rear frame 40, and are also spatially parallel to the control board 1, the user interface board 25, and the main body board 35, because they are top views, the power a board 36 and the power B board 37 block part of the components of the control board 1 and the components of the network interface board 2 and the PCIE interface board 5; because main part board and FPGA chip are at the during operation, can use the operating voltage of different grades according to the demand needs of difference, consequently power A board 36, power B board 37 provide the operating voltage of different grades for main part board 35 through two power boards and main part board connecting socket 38 respectively, and simultaneously, power A board 36, power B board 37 also provide operating power for the fan module.

The power of power a board 36, power B board 37 and the power of control board 1 are all supplied from power input board 39, and referring to fig. 3, power input board 39 is fixed to rear frame 40 and includes: the 24PIN ATX power input interface 57 and the 6PIN input interface 58 are back to the front frame 42 and are leaked out of the FPGA prototype verification device, and the other 4PIN input interface faces the front frame 42; the 24PIN ATX power input interface 57 is connected with an external power supply and provides power for the whole FPGA prototype verification device; the 4PIN input interface is connected with a power input board connecting socket 13 to supply power for the control board 1; the 6PIN input interface 58 provides power to the power A board 36 and the power B board 37.

Referring to fig. 10, a front frame shell 43, a left frame shell 45, a rear frame shell 46 and a right frame shell 47 are respectively and correspondingly installed outside a rear frame 40, a right frame 41, a front frame 42 and a left frame 44, all of which are added with protective cases for dust prevention and safety improvement, the existing FPGA prototype verification device is all a bare PCB board, so that dust inevitably falls into the existing FPGA prototype verification device, and because the existing FPGA prototype verification device is bare, the risk of electric shock is increased in the use process, so that the shells are increased to play a role of dust prevention and avoid the risk of electric shock. In addition, openings are formed in the upper frame 29, the front frame casing 43, the left frame casing 45, the rear frame casing 46, and the right frame casing 47 at positions corresponding to all the interfaces, or sockets, or slots that leak in the FPGA prototype verification apparatus.

Referring to fig. 2, a user front panel 64 is fixed to the front frame 42, and includes: the whole user front panel 64 is connected with the control panel 1 through the user front panel connecting socket 10; the external member selection key 54 is used for a user to select different functions of the FPGA prototype verification device according to own requirements, and the FPGA prototype verification device provides control signal resources for the user through the selection key; the system indicator lamp 56 is an indicator lamp of various states when the FPGA prototype verification device works, and can be customized by a user; the power switch key 51 is a start-up key and a shutdown key of the whole FPGA prototype verification device; the clock socket 55 is a socket provided for the user, through which the FPGA prototype verification apparatus provides the user with clock resources.

Two protection posts 48 are further mounted on the front frame casing 43, and the protection posts 48 are respectively mounted on the front frame 42 and the rear frame 40 for preventing all leaked interfaces, sockets, or sockets in the FPGA prototype verification apparatus from being damaged. Meanwhile, the QSFP optical port 26, the UART interface 27, the FPGA JTAG interface 28, the power switch key 51, the SD Card slot 52, the system reset key 53, the kit selection key 54, the clock socket 55 and the system indicator lamp 56 all leak out of the FPGA prototype verification device, two organic glass supports 49 are installed at the top of the whole FPGA prototype verification device, the organic glass 50 is installed on the organic glass supports 49, and the organic glass 50 further enhances the dust prevention.

It should be noted that the two organic glass brackets 49 are designed because a user may need to connect parts such as an external daughter board or a connecting wire to the main body board 35 when using the FPGA prototype verification apparatus, if the height of the space created by using one organic glass bracket 49 and one organic glass 50 is enough to accommodate the parts, the two organic glass brackets 49 are not needed, if the height of the space created by using one organic glass bracket 49 and one organic glass 50 is not enough to accommodate the parts, the two organic glass brackets 49 are needed, so that the working requirement of the FPGA prototype verification apparatus is met on the basis of ensuring the dustproof function, and in the case of using two organic glass brackets 49, the two organic glass brackets (49) need to be fixed by a fixing sheet (59). In addition, the plexiglass holder 49 and the plexiglass 50 may be selectively installed, i.e., may or may not be installed, depending on the user's needs.

Referring to fig. 3, two protection posts 48 are also mounted on the back frame shell 46, and since the left and right sides of the FPGA prototype verification apparatus only have fans and no interfaces, sockets or slots, there is no need to mount the protection posts 48. Meanwhile, the network port 3, the PCIE interface 4, the 24PIN ATX power input interface 57, and the 6PIN input interface 58 are all exposed to the FPGA prototype verification device, and of course, the areas of the organic glass bracket 49 and the organic glass 50 are larger than those of the FPGA prototype verification device and cover the FPGA prototype verification device.

Referring to fig. 4, three fans in the fan module are mounted on the left frame shell 45, the three fans are fixed on the left frame 44 through the left frame shell 45, protective covers are arranged outside fan blades of the three fans, and the fans are used for dissipating heat for the FPGA prototype verification device.

Referring to fig. 5, three other fans in the fan module are mounted on the right frame shell 47, the three fans are fixed on the right frame 41 through the right frame shell 47, protective covers are also arranged outside fan blades of the three fans, and the fans are also used for dissipating heat for the FPGA prototype verification device.

The utility model discloses FPGA prototype verification device for more convenient maintains FPGA prototype verification device, refers to fig. 6, has seted up Mirco SD Card on bottom plate frame 16 and has changed hole 60, distribution hole 61, battery change hole 62, in order to avoid the mesa fish tail to placing FPGA prototype verification device, has still seted up rubber pad fixed orifices 63. The Mirco SDcard replacing hole 60 is formed for replacing a Mirco SD Card, and a program for starting and controlling the ZYNQ chip 7 is stored in the Mirco SD Card; the wiring holes 61 are opened for conveniently replacing the wiring or some small parts, so that the whole FPGA prototype verification device does not need to be dismantled to replace the wiring or the small parts; the battery replacement hole 62 is provided for facilitating replacement of the battery, and the FPGA prototype verification apparatus further includes: the battery pack is designed for preventing various data loss caused by sudden power failure when the FPGA prototype verification device works, and the battery replacement hole 62 is formed in the position corresponding to the battery pack; the rubber pad fixing hole 63 is formed for installing a rubber pad, and after the rubber pad is installed, the FPGA prototype verification device is placed on the table top of the FPGA prototype verification device in a soft contact mode, and the table top cannot be scratched.

In summary, with reference to fig. 2 to 10, the assembly process of the FPGA prototype verification apparatus according to the embodiment of the present invention is as follows:

1. firstly, fixing a control panel 1, a network port interface board 2 and a PCIE interface board 5;

2. assembling a user interface board 25 and a user interface board bracket 24, wherein the user interface board bracket 24 is fixed on the user interface board bracket fixing plane 18 of the bottom plate frame 16, and the user interface board 25 is fixed on the user interface board bracket 24;

3. assembling the front frame 42 and the rear frame 40, and assembling the power input board 39 on the rear frame 40;

4. fixing the power supply A board 36 and the power supply B board 37 on the front frame 42 and the rear frame 40;

5. assembling a left frame 44 and a right frame 41, respectively assembling fans on a left frame shell 45 and a right frame shell 47 to form a fan module, and then respectively fixing the fan module on the left frame 44 and the right frame 41;

6. securing the user front panel 64 to the front bezel 42;

7. fixing the main body plate 35 to the front frame 42, the rear frame 40, the right frame 41, and the left frame 44, and then assembling the front frame housing 43 and the rear frame housing 46;

8. the upper frame (29) and the protection column (48) are assembled.

All elements and PCBs in the FPGA prototype verification device are provided with unique corresponding connection interfaces, the elements or the PCB connection interfaces which are mutually connected correspond to each other, so that the elements or the PCB can be prevented from being installed wrongly (equivalently, foolproof design is adopted), and the FPGA prototype verification device can be assembled through the process.

The embodiment of the utility model provides an FPGA prototype verification device, the power-on and power-off process of control panel 1 and main body board 35 are orderly, do so in order to protect control panel 1 and main body board 35, in the power-on process of FPGA prototype verification device, FPGA prototype verification device control power input board 39 supplies power for control panel 1 earlier, supplies power for the power panel again, is equivalent to supplying power for main body board 35 afterwards promptly; in the power-down process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board 39 to disconnect the power supply of the power board first, namely, to disconnect the power supply of the main body board 35 first and then disconnect the power supply of the control board 1.

Through the structure, the utility model discloses FPGA prototype verification device can be dismantled in parts, carry out the substep debugging, make entire system debug simplifications and succinct, and simultaneously, the split is come the equipment and is carried out, can bring huge convenience in the aspect of debugging and development, can shorten FPGA prototype verification system's development, part each function, can make things convenient for the engineer to go out on that board when the system goes wrong location problem that can be accurate fast, and structural reservation that has convenient integrated circuit board to dismantle, it is simple to dismantle, can reduce the time of the vacuum during board maintenance. On the premise of ensuring two conditions of leading out more user expanded IO and reducing the board size, the structure of the FPGA prototype verification system built by various PCB boards is designed, and the stability on the physical structure is good. The power supplies of the control panel 1 and the main body panel 35 are separated, so that the maintenance is convenient, the power-on sequence and the power-off sequence are distinguished, and the safety of the FPGA prototype verification device is integrally improved.

In addition, the FPGA prototype verification device of the embodiment of the present invention can be used in cascade, including but not limited to cascade use of two FPGA prototype verification devices, cascade use of four FPGA prototype verification devices, etc., it should be noted that, if two FPGA prototype verification devices are used in cascade, they are in cascade connection in front and back, there are some changes in the overall design, the front end of one FPGA prototype verification device is connected to the back end of another FPGA prototype verification device, the user interface board of the back FPGA prototype verification device, the user front panel is directly placed at the user interface board of the front FPGA prototype verification device, the user front panel is in the coplanar position, and they share one user front panel, that is, there are two user interface boards and one user front panel both at the front end; similarly, the network port interface board and the PCIE interface board of the front FPGA prototype verification apparatus are directly placed at the coplanar positions of the network port interface board and the PCIE interface board of the rear FPGA prototype verification apparatus, that is, there are four network port interface boards and two PCIE interface boards at the rear end; the cascading mode of the four FPGA prototype verification devices is similar to that of the prior art, and only the fan at the middle position in the cascading process is removed.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The present invention has been described in detail, and the principle and the implementation of the present invention have been explained by using specific examples, and the explanation of the above examples is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

Claims (14)

1. An FPGA prototype verification apparatus, comprising: the system comprises a control panel (1), a network port interface board (2), a PCIE interface board (5), a bottom plate frame (16), a user interface board bracket (24), a user interface board (25), a main body plate (35), a power input board (39), a rear frame (40), a right frame (41), a front frame (42), a left frame (44), a user front panel (64) and a power board;

the control board (1) is fixed on the bottom board frame (16) and is used for managing the working state of the FPGA prototype verification device;

the control panel (1) is respectively connected with the network port interface board (2) and the PCIE interface board (5), the network port interface board (2) and the PCIE interface board (5) are fixed on the bottom plate frame (16), the network port interface board (2) is used for communicating with an upper computer through a network port of the network port interface board (2), and the PCIE interface board (5) is used for supporting simulation test through an interface of the PCIE interface board (5);

the user interface board (25) is fixed on a user interface board bracket fixing plane (18) on the bottom plate frame (16) through the user interface board bracket (24) and is used for providing an external interface for a user;

the power input board (39) is fixed on the rear frame (40) and used for supplying power to the FPGA prototype verification device;

the power panel includes: the power supply A board (36) and the power supply B board (37) are fixed on the front frame (42) and the rear frame (40) and are used for providing different levels of working voltage for the main body board (35);

the user front panel (64) is fixed on the front frame (42) and is used for providing a control function for a user;

the main body board (35) is respectively connected with the front frame (42), the rear frame (40), the left frame (44) and the right frame (41) and is used for completing all functions of the FPGA prototype verification device and providing an expansion port for a user so as to connect a sub-board and further complete functions required by the user;

wherein the power input board (39) supplies power to the control board (1) and the power board, respectively;

in the power-on process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board (39) to supply power to the control board (1) firstly and then to supply power to the power board;

and in the power-down process of the FPGA prototype verification device, the FPGA prototype verification device controls the power input board (39) to disconnect the power supply of the power board firstly and then disconnect the power supply of the control board (1).

2. The FPGA prototype verification apparatus of claim 1, wherein the control board (1), the power board, the user interface board (25), and the main body board (35) are spatially parallel to each other, the control board (1), the user interface board (25), and the main body board (35) providing at least two different types of external user interfaces, respectively.

3. FPGA prototype verification device according to claim 1, characterized in that said control board (1) comprises: DDR3 memory socket (6), ZYNQ chip (7), high speed FireFly socket (8), power module (9), user front panel connection socket (10), ZYNQ JTAG slot (11), control panel power input interface (12), power input board connection socket (13), SD Card slot (52), Micro SD Card slot;

the DDR3 memory socket (6), the high-speed FireFly socket (8), the power module (9), the user front panel connection socket (10), the ZYNQ JTAG slot (11), the control panel power input interface (12), the power input panel connection socket (13), the SD Card slot (52) and the Micro SD Card slot are all connected with the ZYNQ chip (7);

the power supply module (9) converts the voltage provided by the power input board (39) into different levels of working voltage to supply to the control board (1).

4. The FPGA prototype verification apparatus according to claim 3, wherein the control board (1) further comprises: the control panel (1) is connected with the network interface board (2) and the PCIE interface board (5) through the MINI interface card slot respectively;

the network port interface board (2) comprises: kilomega network port, UART interface and USB interface;

the PCIE interface board (5) comprises: a PCIE interface;

the gigabit network port, the UART interface, the USB interface and the PCIE interface are all connected with the ZYNQ chip (7).

5. The FPGA prototype verification apparatus of claim 3, wherein the body board (35) comprises: the device comprises a connecting slot, a main body board high-speed FireFly socket, an FPGA chip, an HSPI2 socket (22), a main body board JTAG maintenance hole (23), a main body board DDR4 socket (30), a DDR3 socket (31), a main body board QTH socket (32), a main body board key (33) and a main body board dial switch (34);

the connecting slot and the main body board high-speed FireFly socket face the control board (1) and are connected with an FPGA chip, and the HSPI2 socket (22), the main body board JTAG maintenance hole (23), the main body board DDR4 socket (30), the main body board DDR3 socket (31), the main body board QTH socket (32), the main body board key (33) and the main body board dial switch (34) all face away from the control board (1) and are connected with the FPGA chip;

the main body board (35) is connected with the power supply A board (36) and the power supply B board (37) through the connecting slot, so that the power supply A board (36) and the power supply B board (37) provide different levels of working voltage for the main body board (35) and the FPGA chip;

the communication between the main body board (35) and the control board (1) is completed by connecting the flat cables to respective high-speed FireFly sockets.

6. FPGA prototype verification device according to claim 1, characterized in that said user interface board (25) comprises: QSFP optical port (26), FPGA JTAG interface (28), UART interface (27), user interface board high-speed FireFly slot;

the user interface board (25) is connected with the main body board (35) through the high-speed FireFly slot of the user interface board.

7. The FPGA prototype verification apparatus of claim 3, wherein the user front panel (64) comprises: a kit selection key (54), a system indicator light (56), a power switch key (51) and a clock socket (55);

the user front panel (64) is connected with the control panel (1) through the user front panel connection socket (10).

8. The FPGA prototype verification apparatus of claim 1, wherein the power input board (39) comprises: 24PIN ATX power input interface (57), 6PIN input interface (58) and 4PIN input interface;

the 24PIN ATX power input interface (57) is connected with an external power supply;

the 4PIN input interface supplies power to the control board (1);

the 6PIN input interface (58) supplies power to the power panel.

9. The FPGA prototype verification device of any of claims 1-8, further comprising: an upper frame (29), a front frame shell (43), a left frame shell (45), a rear frame shell (46) and a right frame shell (47);

the front frame (42) is fixed on a front frame fixing plane (19) on the bottom plate frame (16); the rear frame (40) is fixed on a rear frame fixing plane (21) on the bottom plate frame (16); the left frame (44) is fixed on a left frame fixing plane (20) on the bottom plate frame (16); the right frame (41) is fixed on a right frame fixing plane (17) on the bottom plate frame (16);

the left frame outer shell (45) is mounted on the left frame (44), the right frame outer shell (47) is mounted on the right frame (41), the front frame outer shell (43) is mounted on the front frame (42), and the rear frame outer shell (46) is mounted on the rear frame (40);

the upper frame (29) is connected with the front frame (42), the rear frame (40), the left frame (44) and the right frame (41) respectively;

holes are formed in the upper frame (29), the front frame shell (43), the left frame shell (45), the rear frame shell (46) and the right frame shell (47) at positions corresponding to all leaked interfaces, sockets or slots in the FPGA prototype verification device.

10. The FPGA prototype verification device of claim 9, further comprising: a fan module;

the fan module is fixed on the left frame (44) and the right frame (41) through the left frame shell (45) and the right frame shell (47) respectively, a protective cover is arranged outside a fan blade of the fan module, and the fan module is used for dissipating heat of the FPGA prototype verification device.

11. The FPGA prototype verification device of claim 3, further comprising: a battery pack; the front end and the rear end of the bottom plate frame (16) are both provided with: a handle (15), an electrostatic fixing hole (14) and a rubber pad fixing hole (63);

a Mirco SD Card replacing hole (60) is formed in the bottom plate frame (16) corresponding to a Mirco SD Card slot in the control plate (1), a battery replacing hole (62) is formed in the bottom plate frame corresponding to the battery pack, and a wiring hole (61) for replacing wiring is further formed in the bottom plate frame;

the lifting handle (15) is used for carrying the FPGA prototype verification device;

the static fixing hole (14) is used for being connected with an external static grounding device and releasing static generated by the FPGA prototype verification device;

the rubber pad fixing hole (63) is used for installing a rubber pad, so that the FPGA prototype verification device is placed on the table top of the FPGA prototype verification device in a soft contact mode.

12. The FPGA prototype verification device of any of claims 1-8, further comprising: a protection column (48);

the protection columns (48) are respectively arranged on the front frame (42) and the rear frame (40) and are used for preventing all leaked interfaces, or sockets, or slots in the FPGA prototype verification device from being damaged.

13. The FPGA prototype verification device of claim 9, further comprising: at least one plexiglass holder (49), plexiglass (50) and a fixing plate (59);

the organic glass bracket (49) is arranged on the upper frame (29);

in the case of using only one of the plexiglass supports (49), the plexiglass (50) is mounted on the plexiglass support (49);

in the case of using two of the organic glass supports (49), after the two of the organic glass supports (49) are fixed by the fixing piece (59), the organic glass (50) is installed on the two of the organic glass supports (49).

14. The FPGA prototype verification apparatus of claim 1, wherein all components in said FPGA prototype verification apparatus have unique corresponding connection interfaces, and the connection interfaces of components that are connected to each other correspond to each other to prevent component mounting errors.

Images