CN211291497U

CN211291497U - Frequency modulation MEMS gyroscope rate analysis device

Info

Publication number: CN211291497U
Application number: CN202020196797.8U
Authority: CN
Inventors: 李崇; 王雨晨; 侯佳坤
Original assignee: Ocean University of China
Current assignee: Ocean University of China
Priority date: 2020-02-21
Filing date: 2020-02-21
Publication date: 2020-08-18
Anticipated expiration: 2030-02-21

Abstract

The utility model belongs to the technical field of gyroscope signal processing, specifically disclose a frequency modulation MEMS gyroscope rate analytical equipment, it includes analog circuit part and digital circuit part, and wherein the analog circuit part is used for realizing the analog signal collection of MEMS gyroscope. And the digital circuit part comprises a digital signal frequency measuring circuit, a digital signal demodulating circuit and a digital signal filtering circuit. The digital circuit part is mainly used for completing the processing of frequency measurement, demodulation, filtering and the like of MEMS gyroscope signals. The utility model discloses the analytic work of well MEMS gyroscope speed is all accomplished in digital circuit, therefore can effectively avoid introducing crystal oscillator signal in a large number in the analog circuit region, guarantees that the device possess good electromagnetic compatibility. Simultaneously because digital circuit is difficult for receiving the characteristic of environmental impact, consequently, the utility model discloses the device still can accurate analytic gyro angular rate under extreme environment.

Description

Frequency modulation MEMS gyroscope rate analysis device

Technical Field

The utility model belongs to the technical field of gyroscope signal processing, a frequency modulation MEMS gyroscope speed resolver is related to.

Background

The gyroscope is a core device of the inertial navigation system. In recent years, amplitude modulation type MEMS gyroscopes have been widely used in consumer electronics, industrial manufacturing, and military fields, but their navigation accuracy still has a huge room for improvement. As is well known, long-term operation of the MEMS gyroscope and output drift of the MEMS gyroscope caused by the influence of ambient temperature are always the key problems affecting the navigation accuracy. How to further improve the stability of the MEMS gyroscope in long-term operation in a full-temperature environment is a difficult problem in the industry. For the periodic signal output by the MEMS gyroscope, the signal amplitude is easy to be interfered, and the frequency is not easy to be interfered, so that the frequency modulation type MEMS gyroscope is produced. However, as the implementation difficulty of the frequency modulation MEMS gyroscope is high, no mature product scheme exists so far. The existing rate analysis scheme of the frequency modulation MEMS gyroscope has the following general working principle: generally, an analog oscillator circuit is used for converting a high-frequency analog sine wave signal output by an MEMS gyroscope into a square wave signal with the same frequency; then, an analog phase-locked loop circuit is utilized, signals of a plurality of high-speed crystal oscillators are used as reference signals, frequency multiplication is carried out by matching with a butterfly switch mixer, high-frequency signals output by a gyroscope are tracked, and therefore the signal frequency is measured, and in the process, the influence of high-frequency noise signals is reduced along with a multistage low-pass filter; after the signal frequency is measured, in the existing scheme, a hard limiter and a trigger are used for synchronizing analog signals in an analog circuit, and the rate is analyzed by adopting a traditional I/Q demodulation mode.

The rate analysis scheme of the frequency modulation MEMS gyroscope has the following problems in practical application: 1. the main speed analysis link of the traditional scheme is realized in an analog circuit, and due to the characteristic that an analog signal is easily influenced by the ambient temperature, the traditional scheme is difficult to keep accurate analysis in a full-temperature environment. 2. The traditional scheme adopts a common-mode signal acquisition mode, and in the actual circuit operation process, the common-mode signal acquisition can introduce the influence of common-mode noise signals, so that the overall signal-to-noise ratio of the system is not facilitated. 3. The analog phase-locked loop circuit that traditional scheme adopted needs in analog circuit region, for a plurality of top output signal introduction high-speed crystal oscillator signals, because the high-speed switching characteristic of this signal can lead to additional a large amount of spike pulses in signal border, and then arouses a large amount of electromagnetic interference, has seriously influenced analog signal's normal circulation, can produce adverse effect to the SNR undoubtedly, and butterfly switch mixer has aggravated this problem more. 4. Because the physical characteristics of the MEMS gyroscope are limited, the analysis device needs to provide a direct current signal for the MEMS gyroscope to drive oscillation, so that direct current offset is superposed on an output signal of the gyroscope, and the traditional scheme only adopts low-pass filtering to filter a high-frequency noise signal, neglects the influence of the direct current offset noise on a system and further influences the signal-to-noise ratio of the device. 5. The traditional scheme adopts a common crystal oscillator, and is easily influenced by the ambient temperature to generate errors. 6. In the traditional scheme, an analog low-pass filter is used before the rate is analyzed, so that the phase delay problem is caused, and insufficient phase compensation is easily caused by only adopting a strong and hard synchronous signal of a trigger. 7. The traditional low-pass filter for I/Q demodulation can not effectively filter out the superimposed higher harmonic components in the demodulation signal.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a frequency modulation MEMS gyroscope speed analytical equipment to guarantee under extreme environment still can be accurate analyze out the angular rate information that MEMS gyroscope exported.

The utility model discloses a realize above-mentioned purpose, adopt following technical scheme:

a frequency modulated MEMS gyroscope rate resolving device comprising:

the device comprises an analog signal acquisition circuit, a digital signal frequency measurement circuit, a digital signal demodulation circuit and a digital signal filter circuit;

the input end of the analog signal acquisition circuit is connected with the output end of the gyroscope and is configured to receive four paths of sine wave signals which are respectively output by two vibration modes of the gyroscope in a differential signal mode;

the analog signal acquisition circuit also comprises two output ends which are respectively used for outputting square wave signals of a vibration mode;

the two input ends of the digital signal frequency measuring circuit are respectively connected with one output end of the analog signal acquisition circuit; the digital signal frequency measurement circuit also comprises two output ends which are respectively used for outputting the frequency information of the vibration mode;

the input ends of the digital signal demodulation circuits are two and are respectively connected with one output end of the digital signal frequency measuring circuit; the digital signal demodulation circuit also comprises an I/Q demodulation circuit and an output end used for outputting the I/Q demodulated same-phase signal;

one input end of the digital signal filter circuit is connected with the output end of the digital signal demodulation circuit; the digital signal filter circuit also comprises an output end used for outputting the angular rate information output by the gyroscope.

Preferably, the analog signal acquisition circuit comprises a transimpedance operator, a differential operator and a comparison operator;

the transimpedance arithmetic unit is a transimpedance arithmetic unit with a band-pass structure;

four transimpedance calculators are provided; the input end of each transimpedance operator is respectively used for receiving a sine wave signal;

two sine wave signals are respectively from a positive output signal and a negative output signal of a first vibration mode of the gyroscope; the other two sine wave signals are respectively from positive and negative output signals of a second vibration mode;

the first vibration mode and the second vibration mode are two vibration modes of the gyroscope;

the two difference operators are a first difference operator and a second difference operator;

the output ends of the two cross-group arithmetic units corresponding to the first vibration mode are respectively connected with the positive input end and the negative input end of the first differential arithmetic unit; the output ends of the two cross-group arithmetic units corresponding to the second vibration mode are respectively connected with the positive input end and the negative input end of the second differential arithmetic unit;

the two comparison operators are a first comparison operator and a second comparison operator;

the output end of the first differential operator is connected to the input end of the first comparison operator, and the output end of the second differential operator is connected to the input end of the second comparison operator; the output ends of the two comparison calculators are respectively connected with a digital signal frequency measuring circuit.

Preferably, the digital signal frequency measurement circuit comprises a crystal oscillator, a frequency division shaping circuit, a gate controller, a logic controller, a frequency measurement main gate, a counter and a calculation unit; wherein, the crystal oscillator adopts a temperature compensation crystal oscillator;

the output end of the crystal oscillator is connected with the input end of the frequency division shaping circuit, the output end of the frequency division shaping circuit is connected with the input end of the gate controller, and the output end of the gate controller is respectively connected to the frequency measurement main gate and the control end of the logic controller;

the two input ends of the frequency measurement main gate are respectively connected with one output end of the analog signal acquisition circuit;

the output end of the frequency measurement main gate is connected to the input end of the counter, and the output end of the counter is connected to the input end of the computing unit;

the output ends of the computing unit are two, one is a frequency information output end of a first vibration mode, and the other is a frequency information output end of a second vibration mode; two output ends of the computing unit are respectively connected to the digital signal demodulation circuit.

Preferably, the digital signal demodulation circuit includes an adder, an I/Q demodulation circuit, and a digitally controlled oscillator;

one of the adders is a first adder;

the input ends of the first adder are two and are respectively connected with one output end of the digital signal frequency measuring circuit; the output end of the first adder is connected with the I/Q demodulation circuit; the digital controlled oscillator is connected to the signal reference end of the I/Q demodulation circuit;

the output end of the I/Q demodulation circuit is provided with two output ends, one is the output end of the same phase signal, and the other is the output end of the orthogonal phase signal; wherein, the same phase signal output end of the I/Q demodulation circuit is connected to the digital signal filter circuit.

Preferably, the digital signal filtering circuit comprises an adder, a multiplier and a time delay device; wherein:

the adder has two, namely a second adder and a third adder;

the multiplier has five, namely a first multiplier, a second multiplier, a third multiplier, a fourth multiplier and a fifth multiplier;

the number of the time delayers is two, namely a first time delayer and a second time delayer;

the same-phase signal output end of the I/Q demodulation circuit is respectively connected to the input ends of the second adder and the first multiplier; the output end of the second adder is respectively connected to the input end of the second multiplier and the input end of the first delayer;

the output end of the second multiplier is connected to the input end of the third adder;

the output of the first delayer has three paths; each path of output of the first delayer is respectively connected to the input ends of the second delayer, the third multiplier and the fourth multiplier; the output end of the second delayer is connected to the input end of the fifth multiplier;

the output end of the third multiplier is connected to the input end of the third adder;

the output ends of the fourth multiplier and the fifth multiplier are respectively connected to the input end of the second adder;

the first multiplier, the second multiplier, the third multiplier, the fourth multiplier and the fifth multiplier are respectively provided with a constant value input end; the output end of the third adder is the output end of the digital signal filter circuit.

Preferably, the transimpedance operator includes an adder, a capacitor, an amplifier, and a resistor; the adder has two adders, namely a fourth adder and a fifth adder; the capacitor has two, namely a first capacitor and a second capacitor;

the resistors are eight, namely a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor;

the input end of the fourth adder is connected with the input end of the transimpedance operator;

the output end of the fourth adder is connected to the input end of the first capacitor, and the output end of the first capacitor is respectively connected to the input end of the first resistor, the input end of the second capacitor and the positive input end of the amplifier;

the output end of the first resistor and the output end of the second capacitor are respectively connected to a signal reference end;

the output end of the amplifier is connected with the input ends of the second resistor and the sixth resistor respectively;

the output end of the second resistor is respectively connected to the input ends of the third resistor and the fourth resistor; the output end of the third resistor is connected to the signal reference end; the output end of the fourth resistor is connected to the fifth adder;

the output end of the fifth adder is provided with two paths of outputs, one path of output is connected to the reverse input end of the amplifier, the other path of output is connected to the input end of a fifth resistor, and the output end of the fifth resistor is connected to the signal reference end;

the output end of the sixth resistor is respectively connected to the input ends of the seventh resistor and the eighth resistor;

the output end of the seventh resistor is connected to the signal reference end; an output terminal of the eighth resistor is connected to an input terminal of the fourth adder; the output end of the amplifier is used as the output end of the transimpedance operator.

Preferably, an equivalent stray capacitor is further arranged between the input end of the transimpedance operator and the input end of the fourth adder;

the output end of the equivalent stray capacitor is connected to the signal reference end.

Preferably, an equivalent matching impedance is further connected in series between the input end of the transimpedance operator and the input end of the fourth adder.

Preferably, the output end of the fifth adder is further connected with a parasitic capacitance generated by a fifth resistor;

the output end of the parasitic capacitor is connected to the signal reference end;

a first equivalent parallel parasitic capacitance equivalent to the parasitic capacitance generated by the second resistor, the third resistor and the fourth resistor is arranged between the output end of the amplifier and the input end of the fifth adder;

and a second equivalent parallel parasitic capacitance equivalent to the parasitic capacitance generated by the sixth resistor, the seventh resistor and the eighth resistor is arranged between the output end of the amplifier and the input end of the fourth adder.

The utility model has the advantages of as follows:

as above, the utility model provides a frequency modulation MEMS gyroscope speed analytical equipment, the device's signal acquisition accomplishes in analog circuit, and the analytic work of gyroscope speed is all accomplished in digital circuit, therefore can avoid introducing crystal oscillator signal in analog circuit region in a large number, guarantees that the device possess good electromagnetic compatibility. Meanwhile, due to the characteristic that a digital circuit is not easily influenced by the environment, the device can still accurately analyze the angular rate of the gyroscope in an extreme environment.

Drawings

Fig. 1 is a schematic structural diagram of a rate analyzing device of a frequency-modulated MEMS gyroscope according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an analog signal acquisition circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a digital signal frequency measurement circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a digital signal demodulation circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a digital signal filter circuit according to an embodiment of the present invention;

fig. 6 is a block diagram of a circuit structure of a transimpedance operator according to an embodiment of the present invention;

fig. 7 is a more detailed circuit schematic diagram of the transimpedance operator according to the embodiment of the present invention.

Wherein, 1-transimpedance operator, 2 a-first differential operator, 2 b-second differential operator, 3 a-first comparison operator, 3 b-second comparison operator, 4-crystal oscillator, 5-frequency division shaping circuit, 6-gate controller, 7-logic controller, 8-frequency measuring main gate, 9-counter, 10-computing unit, 11-first adder, 12-numerical control oscillator, 13-second adder, 14-third adder, 15-first multiplier, 16-second multiplier, 17-third multiplier, 18-fourth multiplier, 19-fifth multiplier, 20-first time delay, 21-second time delay, 22-fourth multiplier, 23-fifth multiplier, 24-amplifier, 25-equivalent stray capacitance, 26-equivalent matched impedance, 27-first equivalent parallel parasitic capacitance, 28-second equivalent parallel parasitic capacitance.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments:

as shown in fig. 1, a frequency-modulated MEMS gyroscope rate resolving device includes an analog circuit portion and a digital circuit portion.

The utility model discloses to produce devices such as electromagnetic interference's crystal oscillator easily and put in digital circuit to effectively keep apart digital circuit and analog circuit, avoid electromagnetic interference to influence analog signal, strengthen the electromagnetic compatibility of system.

Specifically, the analog circuit part is an analog signal acquisition circuit and is used for acquiring signals of the MEMS gyroscope. And the digital circuit part comprises a digital signal frequency measuring circuit, a digital signal demodulating circuit, a digital signal filtering circuit and the like.

And the digital circuit part is used for completing analysis processing such as frequency measurement, demodulation, filtering and the like of the MEMS gyroscope signal.

The embodiment of the utility model provides an in digital signal frequency measurement circuit, digital signal demodulation circuit and digital signal filter circuit adopt programmable device to realize, wherein, programmable device for example includes FPGA, singlechip, DSP or computer etc..

The following describes each circuit in the embodiment of the present invention in further detail:

and the analog signal acquisition circuit is used for receiving four paths of sine wave signals which are respectively output by two vibration modes of the gyroscope in a differential signal mode, and respectively carrying out denoising processing to obtain square wave signals respectively corresponding to two vibration modes of the gyroscope.

As shown in fig. 2, the input terminal of the analog signal acquisition circuit is connected to the output terminal of the gyroscope. The analog signal acquisition circuit comprises a transimpedance operator 1, a differential operator and a comparison operator.

The transimpedance arithmetic unit is a transimpedance arithmetic unit with a band-pass structure and is used for filtering direct-current offset noise and high-frequency noise in a tiny sine wave signal input to the transimpedance arithmetic unit, so that an effective signal can be ensured to pass smoothly, and the signal-to-noise ratio can be improved.

The number of the transimpedance operators 1 is four, and the input end of each transimpedance operator is provided with a signal input from a gyroscope.

The MEMS gyroscope has two vibration modes, namely a first vibration mode and a second vibration mode, for convenience of description, the first vibration mode is simplified into an A mode for representation, and similarly, the second vibration mode is simplified into a B mode.

The two vibration modes respectively output 4 paths of micro sine wave signals in a differential signal form, namely a positive output signal of the A mode, a negative output signal of the A mode, a positive output signal of the B mode and a negative output signal of the B mode.

The four high-frequency micro sine wave signals are respectively and correspondingly input to the input end of a transimpedance operator 1.

The output end of each transimpedance operator 1 respectively outputs a stable and transmittable sine wave signal, and the direct current offset noise and the high-frequency noise in the sine wave signal are effectively filtered.

There are two differential operators, namely a first differential operator 2a and a second differential operator 2 b.

The output ends of two group-spanning arithmetic units 1 corresponding to the A mode are respectively connected with the positive input end and the negative input end of a first differential arithmetic unit 2 a; the output ends of the two cross-group arithmetic units corresponding to the mode B are respectively connected with the positive input end and the negative input end of the second differential arithmetic unit 2B.

Because the signal at trans-impedance arithmetic unit output is to difference arithmetic unit transmission in-process, has the common mode transmission noise of different degrees on the signal, consequently, the utility model discloses a difference arithmetic unit can be with the effective filtering of common mode transmission noise.

There are two comparison operators, namely a first comparison operator 3a and a second comparison operator 3 b.

All contain hysteresis comparison circuit in first comparison arithmetic unit 3a and the second comparison arithmetic unit 3b, the embodiment of the utility model provides a through rational design hysteresis region, do benefit to the quantization error who reduces the sampling, output with the square wave signal of frequency.

The output of the first differential operator 2a is connected to the input of the first comparison operator 3a, and the output of the second differential operator 2b is connected to the input of the second comparison operator 3 b.

The output ends of the first comparison operator 3a and the second comparison operator 3b are respectively connected to the digital signal frequency measuring circuit.

The direction of the signal flow in the analog signal acquisition circuit is as follows:

outputting 4 paths of sine wave signals in a differential signal mode by two vibration modes of the MEMS gyroscope;

the 4 paths of sine wave signals are respectively subjected to noise filtering by a transimpedance arithmetic unit, and stably transmittable sine wave signals are output, and common mode transmission noise can be generated in the process that the signals output by the transimpedance arithmetic unit are transmitted to a differential arithmetic unit.

The common mode transmission noise is filtered out when passing through the differential operator.

The first differential operator 2a outputs a sine wave signal having the same frequency as the a mode and 2 times the amplitude of the a mode, and the second differential operator 2B outputs a sine wave signal having the same frequency as the B mode and 2 times the amplitude of the B mode.

The signal output by the first differential operator 2a passes through a first comparison operator 3a to obtain a square wave signal with the same frequency as the A mode, wherein the square wave signal carries frequency information of the A mode; in the same way, the method for preparing the composite material,

the signal output by the second differential operator 2B passes through a second comparison operator 3B to obtain a square wave signal with the same frequency as the B mode; the square wave signal carries frequency information of a second vibration mode.

And two paths of square wave signals output by the first comparison operator and the second comparison operator enter the digital signal frequency measuring circuit.

The utility model discloses utilize MEMS top's inherent mechanical characteristic, adopt differential mode signal transmission to replace common mode signal transmission, designed impedance matching model, do benefit to and eliminate common mode noise signal, reduce sampling quantization error, promote the SNR.

And the digital signal frequency measurement circuit is used for receiving the two paths of square wave signals of the vibration modes output by the analog signal acquisition circuit and carrying out frequency measurement processing on the square wave signals to obtain frequency information of the two vibration modes.

As shown in fig. 3, the digital signal frequency measuring circuit includes a crystal oscillator 4, a frequency division shaping circuit 5, a gate controller, a logic controller 7, a frequency measuring main gate 8, a counter 9, and a calculating unit 10.

The crystal oscillator 4 is only one, and a temperature compensation crystal oscillator is preferably adopted, so that the problem of electromagnetic interference in an analog circuit can be effectively reduced compared with the traditional scheme while the gating error in a full-temperature environment can be well controlled.

The output end of the crystal oscillator is connected with the input end of the frequency division shaping circuit, the output end of the frequency division shaping circuit is connected with the input end of the gate controller 6, and the output end of the gate controller is respectively connected to the frequency measurement main gate and the control end of the logic controller.

The frequency measurement main gate 8 has two input ends, and a square wave signal of a vibration mode is correspondingly input respectively.

The output of the frequency measuring main gate 8 is connected to the input of a counter 9, and the output of the counter 9 is connected to the input of a calculating unit 10. The calculation unit 10 is used to calculate the number of pulses per unit time.

The output end of the computing unit 10 has two paths, and each path is used for outputting frequency information of a vibration mode.

The signal flow in the digital signal frequency measuring circuit is as follows:

the crystal oscillator 4 generates a frequency measurement reference signal, enters the frequency division shaping circuit 5 for processing, and then enters the gate controller 6; the gate controller 6 controls the frequency measuring main gate 8 and the logic controller 7 to operate according to the signal.

The frequency measurement main gate 8 has two inputs for receiving square wave signals of A mode and B mode respectively.

Under the control of the logic controller 7, the counter 9 counts the pulse numbers of the square wave signals of the a mode and the B mode respectively, and outputs the pulse numbers to the calculating unit 10 respectively.

The calculation unit 10 calculates frequency information of the a mode and the B mode by calculating the number of pulses in a unit time, and outputs the frequency information of the a mode and the B mode to the digital signal demodulation circuit, respectively.

And the digital signal demodulation circuit is used for receiving the frequency information of the two vibration modes, adding the frequency information of the two vibration modes to obtain a signal to be demodulated, and performing I/Q demodulation on the signal to be demodulated to obtain the same-phase signal.

As shown in fig. 4, the digital signal demodulation circuit includes an adder 11, an I/Q demodulation circuit, and a numerically controlled oscillator 12.

One of the adders is a first adder 11. The first adder 11 has two input ends, and respectively inputs frequency information of one vibration mode, that is, frequency information of the a mode and frequency information of the B mode.

The output of the first adder 11 is connected to the I/Q demodulation circuit.

The numerically controlled oscillator 12 is configured to output two paths of homologous sine and cosine signals as demodulation reference signals of the I/Q demodulation circuit.

The in-phase signal contains angular rate information and higher harmonic components output by the MEMS gyroscope.

The utility model discloses adopt the numerical control oscillator directly to produce homologous signal and be used for the IQ demodulation in digital circuit, guaranteed the synchronism of signal, need not to adopt analog device to carry out synchronizing signal by force in analog circuit, guaranteed phase compensation's accuracy.

The signal flow in the digital signal demodulation circuit runs as follows:

the first adder 11 adds the frequency information of the A mode and the B mode, and outputs the frequency information to the I/Q demodulation circuit as a signal to be demodulated; the numerically controlled oscillator 12 outputs two paths of homologous sine and cosine signals as demodulation reference signals;

the I/Q demodulation circuit demodulates the signal to be demodulated according to the demodulation reference signal, outputs a path of in-phase signal Ix and a path of quadrature phase signal Qx, and inputs the in-phase signal Ix into the digital signal filter circuit for further processing.

And the digital signal filtering circuit is used for receiving the in-phase signal Ix output by the digital signal demodulation circuit and filtering out higher harmonic components in the in-phase signal to obtain the angular rate information output by the MEMS gyroscope.

As shown in fig. 5, the digital signal filtering circuit includes an adder, a multiplier, and a delay.

There are two adders, a second adder 13 and a third adder 14.

There are five multipliers, namely a first multiplier 15, a second multiplier 16, a third multiplier 17, a fourth multiplier 18 and a fifth multiplier 19. There are two delayers, a first delayer 20 and a second delayer 21.

The in-phase signal output ends of the I/Q demodulation circuits are connected to the input ends of the second adder 13 and the first multiplier 15, respectively; the output of the second adder 13 is connected to the second multiplier 16 and the input of the first delayer, respectively.

An output of the second multiplier 16 is connected to an input of the third adder 14.

The output of the first delayer 20 has three outputs, and each output is connected to the input of the second delayer 21, the input of the third multiplier 17, and the input of the fourth multiplier 18.

An output of the second delayer 21 is connected to an input of a fifth multiplier 19.

An output of the third multiplier 17 is connected to an input of the third adder 14.

The output terminals of the fourth multiplier 18 and the fifth multiplier 19 are connected to the input terminal of the second adder 13.

The input terminals of the first multiplier 15, the second multiplier 16, the third multiplier 17, the fourth multiplier 18 and the fifth multiplier 19 have a given constant value k0, k1, k2, k3, k4 respectively, and are input into the corresponding multipliers as shown in fig. 5.

The output of the third adder 14 serves as the output of the digital signal filtering circuit.

The signal flow in the digital signal filter circuit is as follows:

1. the in-phase signal enters the second adder 13 and the first multiplier 15 at the same time;

the in-phase signal is multiplied by a constant value k0 in the first multiplier 15 and output to the third adder 14;

the in-phase signals are added to the signals output from the fourth multiplier 18 and the fifth multiplier 19, respectively, in the second adder 13, and are output to the second multiplier 16 and the first delayer 20.

2. The signal of the second adder 13 is input into the second multiplier 16, multiplied by a constant value k1 and output to the third adder 14; the signal of the second adder 13 is input into the first delayer 20 to wait for the next cycle.

When the next cycle comes, the signal in the first delayer 20 is divided into three paths and output to the third multiplier 17, the fourth multiplier 18 and another delayer, i.e., the second delayer 21.

3. The signal of the first delayer 20 is multiplied by a constant value k2 in the third multiplier 17 and output to the third adder 14; the signal of the first delayer 20 is multiplied by a constant value k3 in the fourth multiplier 18 and output to the second adder 13; the first delay 20 also has an output signal waiting for the next cycle in the second delay 21.

Next cycle, the signal of the second delay 21 is output to the fifth multiplier 19, multiplied by the constant value k4 in the fifth multiplier 19, and output to the second adder 13.

4. So far, a filtering cycle is completed, the third adder 14 adds the input third signal and outputs the added third signal, and the output signal is the gyroscope angular rate signal after the higher harmonic component is filtered out.

To the higher harmonic component that contains in the traditional scheme output angular rate, the utility model discloses digital filter circuit has introduced the feedback mechanism, has realized closed loop design algorithm to be suitable for transfer function's zero point and utmost point realization.

The principle of the digital signal filter circuit for filtering the higher harmonic component is as follows: the embodiment of the utility model provides a digital filter circuit who designs is the high order low delay digital filter circuit, and its transfer function amplitude frequency characteristic possesses good low pass performance, can carry out constant value to the frequency channel of higher harmonic and set for, attenuates higher harmonic component to the at utmost to reach the purpose of filtering.

Compared with other filter circuits, the digital filter circuit in the utility model is a high-order filter, which can fully compress the filter transition band and filter the harmonic component of the high frequency band to the maximum extent; through the operation order of adjustment feedforward part, the delay problem of wave filter has been improved, thereby makes the utility model discloses well digital filter circuit can reach higher operational speed and filtering efficiency.

The following is a further detailed description of the structure of the transimpedance operator provided by the present invention:

as shown in fig. 6, the transimpedance operator includes an input terminal, an output terminal, an adder, a capacitor, an amplifier 24, and a resistor.

There are two adders, a fourth adder 22 and a fifth adder 23.

There are two capacitors, a first capacitor C1 and a second capacitor C3.

The resistors are eight, i.e., a first resistor R2, a second resistor R4, a third resistor R5, a fourth resistor R6, a fifth resistor R7, a sixth resistor R8, a seventh resistor R9, and an eighth resistor R10.

An input of the fourth adder 22 is connected to an input of the transimpedance operator.

The output of the fourth adder 22 is connected to the input of a first capacitor C1, and the output of the first capacitor C1 is connected to the input of the first resistor R2, the second capacitor C3, and the positive input of the amplifier 24, respectively.

The output terminal of the first resistor R2 and the output terminal of the second capacitor C3 are connected to a signal reference terminal, respectively. The signal reference terminal here may be, for example, a zero reference of an analog signal.

The output of the amplifier 24 is connected to the inputs of a second resistor R4 and a sixth resistor R8, respectively.

The output end of the second resistor R4 is connected to the input ends of the third resistor R5 and the fourth resistor R6, respectively; the output end of the third resistor is connected to the signal reference end; the output of the fourth resistor is connected to a fifth adder 23.

The output end of the fifth adder 23 has two outputs, one of the outputs is connected to the inverting input end of the amplifier 24, the other output is connected to the input end of a fifth resistor R7, and the output end of the fifth resistor R7 is connected to the signal reference end.

An output terminal of the sixth resistor R8 is connected to input terminals of the seventh resistor R9 and the eighth resistor R10, respectively.

The output end of the seventh resistor R9 is connected to the signal reference end; the output of the eighth resistor R10 is connected to the input of the fourth adder 22; the output of amplifier 24 serves as the output of the transimpedance operator.

The direction of the signal flow in the transimpedance operator (taking a path of micro sine wave signal output by the gyroscope as an example) is as follows:

a path of micro high-frequency sine wave signal output by the MEMS gyroscope enters the input end of the transimpedance operator through the electromechanical interface, and the fourth adder 22 adds the output signal of the eighth resistor R10 and the input end signal and outputs the added signal to the first capacitor C1.

2. The output signal of the first capacitor C1 enters the first resistor R2, the second capacitor C3, and the non-inverting input of the amplifier 24, respectively, in that order. The signal enters the first resistor R2 and the second capacitor C3 and is output to the signal reference terminal.

3. After the signal passes through the amplifier 24, the output signal of the amplifier 24 is divided into three paths for output:

one path of the output is output to a transimpedance operation output end; one output to the second resistor R4 toward the inverting input of the amplifier 24; one way is output to a sixth resistor R8, which is a precision resistor, towards the non-inverting input of amplifier 24.

4. The signal toward the inverting input terminal of the amplifier 24 is simultaneously output to the third resistor R5 and the fourth resistor R6 after passing through the second resistor R4; the output signal of the third resistor R5 is output to the signal reference terminal.

The output signal of the fourth resistor R6 is output to the fourth adder 23, one output terminal of the fourth adder 23 is output to the inverting input terminal of the amplifier 24, and the other output terminal is output to the fifth resistor R7 and then to the signal reference terminal.

5. The signal toward the non-inverting input terminal of the amplifier 24 passes through the sixth resistor R8, and is simultaneously output to the seventh resistor R9 and the eighth resistor R10. The output signal of the seventh resistor R9 is output to the signal reference terminal.

The output signal of the eighth resistor R10 is output to the fourth adder 22, which adds the input signal mentioned in 1 above.

Through the design of the band-pass trans-impedance arithmetic unit, the direct current offset and the high-frequency noise can be attenuated simultaneously, so that the direct current offset and the high-frequency noise in the tiny high-frequency sine wave signals can be eliminated, the effective signals can be ensured to pass smoothly, and the signal-to-noise ratio is improved.

The transimpedance arithmetic unit attenuates the direct current offset and the high-frequency noise, and the principle that effective signals pass is guaranteed as follows:

in the band-pass transimpedance operator circuit designed according to the embodiment of the present invention, the star network formed by the sixth resistor R8, the seventh resistor R9 and the eighth resistor R10, the equivalent stray capacitance near the transimpedance operator input end, and the second capacitor C3 are used for attenuating high-frequency band signals; and a first capacitor C1 and a first resistor R2 for attenuating the dc offset.

In addition, because the design of the arithmetic ware is striden to above bandeau formula, make the utility model discloses the passband frequency that can also be different to the different MEMS top gauge outfit designs of different batches simultaneously to reach the perfect adaptation to different top gauge outfits.

The utility model discloses fully consider all kinds of factors to the influence that signal transmission and operation caused, add the operation link that some non-ideal factors constitute on the basis of the arithmetic ware circuit of striding resistance more than, constitute the arithmetic ware of striding resistance of considering the influence of multiple factor.

1. As shown in fig. 7, the utility model discloses fully consider the stray capacitance problem that arouses by objective factors such as electromechanical interface, components and parts and carriers, because stray capacitance is the parallel relation mostly, so add its capacitance value to add an equivalent stray capacitance 25 between the input of trans-impedance operation and the input of fourth adder 22, input signal gets into this equivalent stray capacitance, and exports to the signal reference end. The equivalent stray capacitance exhibits the properties of a capacitor to the input signal.

2. As shown in fig. 7, the present invention fully considers the matching impedance problem and the signal delay problem of 4 paths of small sine wave signals in differential transmission. For guaranteeing the parallel data acquisition of 4 small sine wave signals of way and weakening the influence of signal delay, the utility model discloses add an equivalent matching impedance 26 between the input of striding the resistance operation and the input of fourth adder 22, it shows the nature of resistor to input signal. In an actual circuit, impedance change caused by factors such as high-frequency signal reflection in the signal circulation process is fully considered, and a reasonable impedance matching model is designed to ensure that the matching impedance of the 4-path transimpedance arithmetic unit is the same.

3. As shown in fig. 7, the present invention fully considers the non-ideal factors of the resistor, and the parasitic capacitance of the resistor, which is a kind of capacitive impedance, will affect the transmission and operation of the signal. Ideally a parasitic capacitance should be connected in parallel across each resistor. However, the utility model discloses consider the complexity of operation, made equivalent simplification to parasitic capacitance's addition and handled.

The first resistor R2 is connected in parallel with the second capacitor C3, so the parasitic capacitance is equivalent to the sum of the capacitance of the C3 capacitor, and the capacitance of the parasitic capacitance is usually very small, so the influence of the parasitic capacitance of the R2 resistor on the circuit does not need to be considered.

The star network formed by the second resistor R4, the third resistor R5 and the fourth resistor R6 is complicated, and therefore the parasitic capacitances of the three are equivalent to a first equivalent parallel parasitic capacitance, i.e., an equivalent parallel parasitic capacitance E1 shown in fig. 7.

An input terminal of the first equivalent parallel parasitic capacitance 27 is connected to an input terminal of the second resistor R4, and an output terminal of the first equivalent parallel parasitic capacitance 27 is connected to an input terminal of the fifth adder 23.

A parasitic capacitance R7 is added near the fifth resistor R7, the input terminal of the parasitic capacitance R7 is connected to the output terminal of the fourth adder 23, and the output terminal of the parasitic capacitance R7 is connected to the signal reference terminal.

Since the star network formed by the sixth resistor R8, the seventh resistor R9 and the eighth resistor R10 is complicated, the parasitic capacitances of the three are equivalent to the second equivalent parallel parasitic capacitance 28, i.e., the equivalent parallel parasitic capacitance E2 in fig. 7.

An input of the second equivalent parallel parasitic capacitance 28 is connected to an input of a sixth resistor R8 and an output of the second equivalent parallel parasitic capacitance 28 is connected to an input of the fourth adder 22.

4. As shown in fig. 7, the present invention considers the noise gain model of the resistor, the influence of the resistance value, the ambient temperature, the signal frequency, the thermal temperature coefficient, and other factors. Noise due to the resistor increases with increasing resistance value, temperature. Therefore, under extreme high temperature conditions, the resistor with the larger resistance value will have more noise. In order to solve the problem, the utility model designs a star network that is formed by equivalent parallel parasitic capacitance E1, second resistor R4, third resistor R5 and fourth resistor R6 and a star network that is formed by equivalent parallel parasitic capacitance E2, sixth resistor R8, seventh resistor R9 and eighth resistor R10. Through analyzing the resistance noise gain model, two star networks are introduced into each trans-impedance arithmetic unit, and each star network is connected in series and in parallel through the resistor with smaller resistance value (the resistance noise gain is reduced by pressing down the resistance value of each resistor), and is equivalent to the resistor with large resistance value, so that the signal-to-noise ratio of the device under the extremely high temperature condition is ensured, and the practical value of the device is further improved.

The utility model discloses an above design of hindering arithmetic ware strides of considering the influence of multiple factor does benefit to the accuracy of guaranteeing the operation result.

Of course, the above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and it should be noted that any equivalent substitution, obvious modification made by those skilled in the art under the teaching of the present specification fall within the essential scope of the present specification, and the protection of the present invention should be protected.

Claims

1. A frequency modulated MEMS gyroscope rate resolving device, comprising:

2. The gyroscope rate resolving device of claim 1,

the analog signal acquisition circuit comprises a transimpedance arithmetic unit, a differential arithmetic unit and a comparison arithmetic unit;

two paths of sine wave signals are respectively from positive and negative output signals of a first vibration mode of the gyroscope; the other two paths of sine wave signals are respectively from positive and negative output signals of a second vibration mode;

3. The gyroscope rate resolving device of claim 1,

the digital signal frequency measurement circuit comprises a crystal oscillator, a frequency division shaping circuit, a gate controller, a logic controller, a frequency measurement main gate, a counter and a calculation unit; wherein, the crystal oscillator adopts a temperature compensation crystal oscillator;

the output ends of the computing units are two, one is a frequency information output end of a first vibration mode, and the other is a frequency information output end of a second vibration mode; two output ends of the computing unit are respectively connected to the digital signal demodulation circuit.

4. The gyroscope rate resolving device of claim 1,

the digital signal demodulation circuit comprises an adder, an I/Q demodulation circuit and a numerical control oscillator;

one of the adders is a first adder;

5. The gyroscope rate resolving device of claim 1,

the digital signal filtering circuit comprises an adder, a multiplier and a time delay device; wherein:

the adder has two, namely a second adder and a third adder;

6. The gyroscope rate resolving device of claim 2,

the transimpedance operator comprises an adder, a capacitor, an amplifier and a resistor; the adder has two adders, namely a fourth adder and a fifth adder; the capacitor has two, namely a first capacitor and a second capacitor;

7. The gyroscope rate resolving device of claim 6,

an equivalent stray capacitor is also arranged between the input end of the transimpedance operator and the input end of the fourth adder;

8. The gyroscope rate resolving device of claim 6,

and an equivalent matching impedance is also connected in series between the input end of the transimpedance operator and the input end of the fourth adder.

9. The gyroscope rate resolving device of claim 6,

the output end of the fifth adder is also connected with a parasitic capacitor generated by a fifth resistor;