CN211264963U

CN211264963U - Semiconductor package device and control circuit thereof

Info

Publication number: CN211264963U
Application number: CN201921686083.9U
Authority: CN
Inventors: 潘镭
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2019-10-09
Filing date: 2019-10-09
Publication date: 2020-08-14
Anticipated expiration: 2029-10-09

Abstract

The present application relates to a semiconductor package device and a control circuit thereof. The control circuit is connected to the internal circuit. The control circuit includes: a first node for receiving a first power input; a second node to receive a second power input, the second node connected to the internal circuit; a voltage regulator having an input node and an output node, the output node being connected to the internal circuit; and a switching device connected between the first node and the input node of the voltage regulator; wherein the switching device disconnects the first node from the input node of the voltage regulator when the second power input has a second voltage value to supply the second power input having the second voltage value to the internal circuit.

Description

Semiconductor package device and control circuit thereof

Technical Field

The present application relates generally to semiconductor package designs and, more particularly, to semiconductor package elements and control circuits thereof.

Background

Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically labeled as a logical "1" or a logical "0". In other systems, more than two states may be stored. To access the stored information, the electronic device may read or sense the stored state in the memory device. To store information, the electronic device may write or program a state in the memory device.

The memory devices may be volatile or non-volatile. Volatile memory devices (e.g., random access memory) can lose their stored state over time unless periodically refreshed by an external power source. Non-volatile memory, such as flash memory, can store data for long periods of time even in the absence of an external power source.

Embedded multimedia memory cards (eMMC) and Universal Flash Storage (UFS) are two specifications of Flash memory that are mainly used for mobile devices. Both the flash memory and the control chip are packaged together, but the eMMC is based on a parallel data transmission technology, the working mode is half-duplex, reading and writing can not be carried out simultaneously, the UFS is based on a serial data transmission technology and supports a full-duplex mode, and all data channels can simultaneously execute reading and writing operations. Thus, UFS may achieve higher read and write speeds than eMMC.

The first generation UFS standard was issued in 2011 by Joint Electron Device Engineering Council (JEDEC), and the first generation UFS was not widely popularized due to the limitations of factors such as the current application environment and product cost, and had no significant impact on the eMMC standard. In 2013, in 9 months, the JEDEC issued UFS 2.0 standard, the single-channel unidirectional theoretical bandwidth of the UF can reach the level of 1.45Gbps, and the two-channel bidirectional theoretical bandwidth is 5.8Gbps, namely more than 740 MB/s. In 2016, the theoretical bandwidth of UFS2.1 is as high as 11.6Gbps, namely about 1.5GB/s, and compared with eMMC, the UFS has great advantages. And the JEDEC issues UFS3.0 in 2018, 1 month and 30 days, and the single-channel bandwidth can be increased to 11.6Gbps, which is 2 times of the performance of UFS 2.1.

Fig. 1 illustrates a schematic diagram of an exemplary UFS storage system 100. UFS storage system 100 includes a host 102 and a UFS device 104. Host 102 can write data to UFS device 104 or read data from UFS device 104. The UFS device 104 supports two

bi-directional data channels

106, 108, each of which can perform read and write operations simultaneously.

Since the advantages of UFS over eMMC are very significant, UFS is expected to gradually replace eMMC, becoming the mainstream of mobile memory storage systems. To meet the application requirements of mobile devices, further reducing power consumption, improving data reliability, and the like are all issues to be considered in the design of UFS and its package.

SUMMERY OF THE UTILITY MODEL

In one aspect, the present invention provides a control circuit connected to an internal circuit. The control circuit includes: a first node for receiving a first power input; a second node to receive a second power input, the second node connected to the internal circuit; a voltage regulator having an input node and an output node, the output node being connected to the internal circuit; and a switching device connected between the first node and the input node of the voltage regulator; wherein the switching device disconnects the first node from the input node of the voltage regulator when the second power input has a second voltage value to supply the second power input having the second voltage value to the internal circuit.

In some embodiments, when the second power supply input is not at the second voltage value, the switching device conducts a connection between the first node and the input node of the voltage regulator to supply the first power supply input to the voltage regulator, the voltage regulator being configured to convert the first power supply input to generate a regulated first power supply input to supply to the internal circuitry.

In some embodiments, the switching device turns on a connection between the first node and the input node of the voltage regulator to supply the first power supply input to the voltage regulator when the second power supply input is a ground voltage.

In some embodiments, when the switching device conducts the connection between the first node and the input node of the voltage regulator and the first power supply input has a first voltage value, the regulated first power supply input has the second voltage value.

In some embodiments, the switching device comprises a transistor or a fuse.

In some embodiments, the switching device comprises a P-channel metal oxide semiconductor field effect transistor, wherein the first node is connected to a source of the P-channel metal oxide semiconductor field effect transistor, the second node is connected to a gate of the P-channel metal oxide semiconductor field effect transistor, and the input node of the voltage regulator is connected to a drain of the P-channel metal oxide semiconductor field effect transistor. In some embodiments, the control circuit further comprises a resistor connected between the gate of the P-channel metal oxide semiconductor field effect transistor and a ground node.

In some embodiments, the voltage regulator comprises a low dropout linear regulator. In some embodiments, the first voltage value is greater than the second voltage value.

In another aspect, the present invention provides a semiconductor package device, which includes the aforementioned control circuit and internal circuit, wherein the control circuit and the internal circuit are disposed on the same chip.

In some embodiments, the internal circuitry comprises a memory controller. In some embodiments, the semiconductor package element further comprises: a memory array connected to the memory controller. In some embodiments, the memory array comprises a NAND memory array. In other embodiments, the memory array comprises a general purpose flash memory array.

Drawings

The disclosure herein refers to and includes the following figures:

FIG. 1 illustrates a schematic diagram of an exemplary UFS storage system;

figure 2 illustrates an exemplary UFS2.1 device package pin arrangement diagram;

figure 3 illustrates a block diagram of the internal structure of an exemplary UFS package;

FIG. 4 illustrates a circuit schematic of an exemplary low dropout linear regulator;

figure 5 illustrates temperature measurements for various portions of an exemplary UFS package;

FIG. 6 illustrates a schematic diagram of a control circuit according to an embodiment of the present application;

FIG. 7 illustrates a schematic structural diagram of a switching device according to an embodiment of the present application; and

figure 8 illustrates a block diagram of the internal structure of an exemplary UFS package, according to an embodiment of the present application.

Detailed Description

According to standards set by JEDEC, UFS may have three external power inputs: VCC, VCCQ1, and VCCQ 2. Typical voltage ranges are as follows: (1) VCC: 2.4V-2.7V or 2.7V-3.6V; (2) VCCQ 1: 1.14V to 1.26V; (3) VCCQ 2: 1.70V to 1.95V. UFS2.1 devices typically use only VCC and VCCQ2 power inputs, while UFS3.0 devices need to use all three external power inputs.

Fig. 2 shows a pin layout (top view) of an exemplary UFS2.1 device package (e.g., a Ball Grid Array (BGA) package), wherein the definition of each pin can be found in JEDEC related standards documents, such as JEDEC standard 21-C, chapter 3.12.1. Although only VCC and VCCQ2 pins are shown in fig. 1, and VCCQ1 pin is not shown, the VCCQ1 pin may be contained on the actual package, but VCCQ1 pin may not be connected to other components outside and/or inside the package since UFS2.1 devices may not use VCCQ1 power input.

As described above, the UFS packages the flash memory together with the control chip. Thus, different circuit portions inside the UFS package require different supply voltages, and may require additional supply voltages different from VCC, VCCQ1, or VCCQ 2. For example, a front-end UFS interface (i.e., M-PHY) for communicating with a host may require a voltage supply of 0.9V. To obtain various supply voltages within the package, a voltage regulator (e.g., a low dropout regulator (LDO)) is typically incorporated into the package to convert the VCC, VCCQ1, or VCCQ2 supply voltages to the various desired supply voltages.

Fig. 3 illustrates a block diagram of the internal structure of an exemplary UFS package 300.

The UFS package 300 includes a memory array 302 and core logic circuitry 304 to control memory array operations (read or write operations). The core logic circuitry 304 may be part of a memory controller. The core logic circuitry 304 communicates with the memory array 302 through a memory interface 306. Core logic circuitry 304 has multiple interfaces, such as M-PHY 308, 1.8V input/output (I/O) interface 310, and 1.2V I/O interface 312, to communicate with a host or other circuitry. In other embodiments, core logic 304 may have more or fewer interfaces, or have other different interfaces.

As previously described, each circuit portion in UFS package 300 may require a different supply voltage. For example, the memory array 302 and the core logic 304 require 3.3V supply voltage, the memory interface 306 requires 1.2V supply voltage, the M-PHY 308 requires 0.9V supply voltage, the I/O interface 310 requires 1.8V supply voltage, and the I/O interface 312 requires 1.2V supply voltage.

UFS package 300 shown in fig. 3 may have two external power inputs: a 3.3V power input (VCC) and a 1.8V power input (VCCQ 2). Thus, the memory array 302 and the core logic circuitry 304 may be connected to a 3.3V power supply input to receive a 3.3V supply voltage, and the I/O interface 310 may be connected to a 1.8V power supply input to receive a 1.8V supply voltage.

Also included within UFS package 300 are two LDOs connected to a 1.8V power supply input: 0.9V LDO 314 and 1.2VLDO 316. Wherein, LDO 314 receives 1.8V voltage and converts it into 0.9V voltage output, and LDO316 receives 1.8V voltage and converts it into 1.2V voltage output. Thus, M-PHY 308 may be connected to the output of LDO 314 to receive a supply voltage of 0.9V, and memory interface 306 and I/O interface 312 may be connected to the output of LDO316 to receive a supply voltage of 1.2V.

Those skilled in the art will appreciate that figure 3 is merely an illustrative example and that other elements not shown in figure 3 may also be included within the UFS package.

Compared with the traditional linear voltage regulator which requires the input voltage to be at least 2V-3V higher than the output voltage, the LDO is more suitable for the application scene with smaller voltage difference between the input and the output. For example, the voltage difference between the input and the output of LDO 314 in fig. 3 is 0.9V, and the voltage difference between the input and the output of LDO316 is 0.6V. Fig. 4 shows a schematic circuit structure of an exemplary LDO 400.

As shown in fig. 4, LDO 400 includes a reference voltage source 402, an error amplifier 404, a tuning tube 406, and

feedback resistors

408 and 410. In this example, the tuning transistor 406 is a P-channel metal oxide semiconductor field effect transistor (PMOS transistor). Those skilled in the art will appreciate that the tuning tube may be implemented as other types of transistors. The regulating tube 406 receives an input voltage VIN at its source and generates an output voltage VOUT at its drain. The output voltage VOUT is divided by the series-connected

feedback resistors

408 and 410 to generate a feedback voltage VFB that is applied to the non-inverting input (+) of the error amplifier 404. Reference voltage source 402 is coupled to the inverting input of error amplifier 404, thereby applying a reference voltage VR to the inverting input (-) of error amplifier 404. Error amplifier 404 compares VFB with VR and amplifies the difference to generate a control voltage. The output of the error amplifier 404 is connected to the gate of the input tuning transistor 406, so that the gate voltage of the tuning transistor 406 can be controlled to regulate the output voltage VOUT.

When the output voltage VOUT decreases, the feedback voltage VFB decreases accordingly by the voltage dividing effect of the

feedback resistors

408 and 410. Since the feedback voltage VFB is connected to the non-inverting input terminal of the error amplifier 404, the control voltage output by the error amplifier 404 is correspondingly decreased, i.e., the gate voltage of the regulating tube 406 is decreased, the gate-source voltage difference is increased, the drain current is increased, and the output voltage VOUT is correspondingly increased, so that the decrease of the output voltage VOUT is suppressed and kept stable. Likewise, as the output voltage VOUT increases, the feedback voltage VFB increases accordingly through the voltage dividing effect of the

feedback resistors

408 and 410. Since the feedback voltage VFB is connected to the non-inverting input terminal of the error amplifier 404, the control voltage output by the error amplifier 404 increases accordingly, i.e., the gate voltage of the regulating tube 406 increases, the difference between the gate and source voltages decreases, the drain current decreases, and the output voltage VOUT decreases accordingly, so that the increase of the output voltage VOUT is suppressed and kept stable.

Those skilled in the art will appreciate that fig. 4 is merely an illustrative example and that LDOs may be implemented in various other circuit configurations. The present LDO circuits and LDO circuits that may appear in the future are all intended to be covered by the scope of the present application.

The input current and the output current of the LDO are approximately equal. Therefore, the power consumed by the LDO during operation can be calculated by the following equation (1):

P＝(VIN-VOUT)×I (1)，

VIN is the input voltage of the LDO, VOUT is the output voltage of the LDO, and I is the working current of the LDO.

LDOs in UFS packages typically have large operating currents. In some examples, the maximum current of a 0.9V LDO (e.g., LDO 314 in fig. 3) within a UFS package can be up to 450mA, and the maximum current of a 1.2V LDO (e.g., LDO316 in fig. 3) can be up to 150 mA. In this case, it can be calculated from equation (1) that the total power consumed by 0.9V LDO and 1.2V LDO in the UFS package under extreme conditions can be up to about 0.5W, which is about one third of the power consumed by the entire UFS package.

The LDO consumes more power and thus generates more heat, causing its temperature to rise. Figure 5 shows temperature measurements of various components in an exemplary UFS package, when tested at an ambient temperature of 65 ℃. Where 502 represents the temperature of the LDO, 504 represents the temperature of the memory controller, 506 represents the temperature of the capacitor connected to the LDO, and 508 represents the temperature of the M-PHY. As can be seen in fig. 5, the temperature of the LDO is highest, which is about 20 ℃ higher than the temperature of the memory controller and about 60 ℃ higher than the ambient temperature.

The high temperatures generated by the LDO will adversely affect the memory array in its vicinity. In particular, the high temperatures generated by LDOs may cause unpredictable changes in the states of memory cells in a memory array, thereby reducing the reliability of data stored in the memory array. In particular, the impact is particularly severe for UFS in the form of BGA packages.

Therefore, in order to improve the internal data reliability of UFS devices, it is desirable to reduce the power consumption of LDOs within the UFS package during operation, thereby reducing the temperature within the UFS package.

Fig. 6 shows a schematic structural diagram of a control circuit 600 according to an embodiment of the present application. This control circuitry may be used to control the supply voltage provided to internal circuitry (e.g., memory interface 306, M-PHY 308, I/O interface 312, etc. within the UFS package shown in fig. 3) without controlling the operation of the memory array as a memory controller would.

As shown in fig. 6, the control circuit 600 includes a first node 602, a second node 604, a switching device 606, and a voltage regulator 608. The first node 602 is configured to receive a first power input and is connected to a first terminal of a switch device 606. A second terminal of the switching device 606 is connected to an input node of the voltage regulator 608, and an output node of the voltage regulator 608 is connected to internal circuitry.

The second node 604 is configured to receive a second power input and is coupled to a control terminal of the switching device 606, such that the on/off state of the switching device can be controlled based on the second power input. The second node 604 is also connected to internal circuitry. When the second power input is present, the second power input may be supplied to the internal circuit as a supply voltage through the second node 604. Meanwhile, based on the control terminal of the switching device 606 receiving the second power input, the switching device 606 is in an off state, thereby disconnecting the first node 602 from the input node of the voltage regulator 608 such that the voltage regulator 608 does not receive the first power input. In this case, the voltage regulator 608 will not perform voltage conversion and thus will consume little power and generate no heat.

When the second power input is not present, the switching device 606 is in a conducting state, and the switching device 606 connects the first node 602 with the input node of the voltage regulator 608, so that the first power input received by the first node 602 is input to the voltage regulator 608. In one embodiment, the voltage regulator 608 may be an LDO. The voltage regulator may convert the first power input to generate a regulated first power input and supply the regulated first power input to the internal circuit as a supply voltage.

According to an embodiment of the present application, the first node 602 may be an external power input pin (e.g., VCCQ2 pin) of the UFS package, and the second node 604 may be a no-connection pin (NC pin) of the UFS package. For UFS devices that do not use VCCQ1 power inputs (e.g., UFS2.1 devices), the second node 604 may also be a VCCQ1 pin of the UFS package.

According to embodiments of the present application, the voltage regulator 608 may convert the first voltage value (e.g., 1.8V in fig. 3) to the second voltage value (e.g., 0.9V, 1.2V in fig. 3). In some embodiments, the first voltage value is greater than the second voltage value.

According to an embodiment of the present application, when the second power supply input has the second voltage value, the switching device 606 disconnects the first node 602 from the input node of the voltage regulator 608; when the second power supply input is not at the second voltage value, the switching device 606 turns on the connection between the first node 602 and the input node of the voltage regulator 608.

According to an embodiment of the present application, the control circuit 600 may be disposed on the same chip as the internal circuit. For example, control circuit 600 may be formed on the same die as a memory controller within a UFS package, or control circuit 600 may be formed on a substrate within a UFS package.

The switching device 606 in the control circuit 600 shown in fig. 6 may be implemented in various forms. For example, the switch 606 may be implemented by a switch element such as a transistor. Fig. 7 illustrates a schematic diagram of a switching device 700 according to an embodiment of the present application. Switching device 700 may be used to implement switching device 606.

The switching device 700 shown in fig. 7 includes a PMOS transistor 702. The source of the PMOS transistor 702 is a first terminal 704 of the switching device 700, the drain of the PMOS transistor 702 is a second terminal 706 of the switching device 700, and the gate of the PMOS transistor 702 is a control terminal 708 of the switching device 700. Referring to fig. 6, a first terminal 704 of the switching device 700 may be connected to a first node (e.g., 602 in fig. 6) to receive a first power input; a second terminal 704 of the switching device 700 may be connected to an input node of a voltage regulator (e.g., 608 in fig. 6) to pass a first power supply input to the voltage regulator when in an on state; the control terminal 708 of the switching device 700 may be connected to a second node (e.g., 604 in fig. 6) to receive a second power input. The switching device 700 further includes a resistor 710, and the resistor 710 is connected between the gate of the PMOS transistor 702 and the ground node.

When the second node does not receive the second power input with the second voltage value, the gate of the PMOS transistor 702 is substantially at the ground potential, and the source and the drain of the PMOS transistor 702 will be turned on to transfer the first power input received by the first node to the input node of the voltage regulator for voltage conversion. When the second node receives a second power input with a second voltage value, the gate voltage of the PMOS transistor 702 increases, and the source and the drain of the PMOS transistor 702 are disconnected, so that the voltage regulator cannot receive the first power input, thereby reducing the power consumption of the voltage regulator.

It will be appreciated by those skilled in the art that fig. 7 is merely an illustrative example, and that the switching device may be implemented using various other circuit elements, and such implementations are intended to be within the scope of the present application. In some embodiments, the switching device may include a fuse that may be selectively opened and closed based on the control signal. In the event that the second power input is received, a corresponding control signal is generated to cause the fuse to open, thereby disabling the voltage regulator from receiving the first power input.

In some embodiments, the switching device may also be implemented by setting software code to configure firmware.

Figure 8 illustrates a block diagram of the internal structure of an exemplary UFS package 800, in accordance with embodiments of the present application. In accordance with embodiments of the present application, UFS package 800 has control circuitry (e.g., control circuitry 600 shown in figure 6) added therein and utilizes additional external power input, as compared to UFS package 300 shown in figure 3.

The UFS package 800 includes a memory array 802 and core logic 804 to control memory array operations (read or write operations). The core logic 804 may be part of a memory controller. The core logic 804 communicates with the memory array 802 through a memory interface 806. The core logic 804 has a plurality of interfaces, such as M-PHY 808, 1.8V I/O interface 810, and 1.2V I/O interface 812, to communicate with a host or other circuitry. In other embodiments, core logic 804 may have more or fewer interfaces, or have other different interfaces.

As previously described, each circuit portion in UFS package 800 may require a different supply voltage. For example, the memory array 802 and the core logic 804 require 3.3V for supply, the memory interface 806 requires 1.2V for supply, the M-PHY 808 requires 0.9V for supply, the I/O interface 810 requires 1.8V for supply, and the I/O interface 812 requires 1.2V for supply.

In addition to the same 3.3V power input (VCC) and 1.8V power input (VCCQ2) as shown in fig. 3, UFS package 800 shown in fig. 8 receives two additional external power inputs: 0.9V and 1.2V. In some embodiments, additional external power inputs may be received through the NC pin of the UFS package. In other embodiments, an additional external power input (e.g., 1.2V) may be received through the UFS package VCCQ1 pin.

The memory array 802 and the core logic 804 may be connected to a 3.3V power supply input to receive a 3.3V supply voltage, and the I/O interface 810 may be connected to a 1.8V power supply input to receive a 1.8V supply voltage.

UFS package 800 also includes two LDOs: 0.9V LDO 814 and 1.2V LDO 816. However, unlike UFS package 300 shown in fig. 3, LDOs 814 and LDO816 in UFS package 800 are not directly connected to a 1.8V power input.

The switching device 818 is connected between the 1.8V power input and the LDO 814. The switching device 818 may be the switching device 700 shown in fig. 7 or another type of switching device. The control terminal of the switching device 818 is connected to a 0.9V power supply input node (e.g., NC pin). When the 0.9V power input is not provided to UFS package 800, switching device 818 is turned on such that the 1.8V power input is connected to LDO 814. LDO 814 receives the 1.8V voltage and converts it to a 0.9V voltage output. In this case, the 0.9V voltage output by LDO 814 is provided to M-PHY 808 as its supply voltage. When a 0.9V power input is provided to UFS package 800, switching device 818 is open. In this case, LDO 814 cannot receive a 1.8V power input and thus does not perform voltage conversion. An externally provided 0.9V power supply input is provided to the M-PHY 808 as its supply voltage. In one embodiment, to prevent the output voltage of LDO 814 from being erroneously transferred to the control terminal of the switching device 818 without a 0.9V power input, a diode 822 may be disposed between the control terminal of the switching device 818 and the output node of LDO 814. In other embodiments, other circuit configurations capable of forming a unidirectional current path may be used.

Switching device 820 is connected between the 1.2V power input and LDO 816. Switching device 820 may be switching device 700 as shown in fig. 7 or another type of switching device. The control terminal of switching device 820 is connected to a 1.2V power input node (e.g., NC pin or VCCQ1 pin). When the 1.2V power input is not provided to UFS package 800, switching device 820 is turned on such that the 1.8V power input is connected to LDO 816. LDO816 receives the 1.8V voltage and converts it to a 1.2V voltage output. In this case, the 1.2V voltage output by LDO816 is provided to memory interface 806 and I/O interface 812 as its supply voltage. When a 1.2V power input is provided to UFS package 800, switching device 820 is open. In this case, LDO816 cannot receive a 1.8V power input and thus does not perform voltage conversion. An externally provided 1.2V power supply input is provided to the memory interface 806 and the I/O interface 812 as their supply voltages. In one embodiment, to prevent the output voltage of LDO816 from erroneously passing into the control terminal of switching device 820 without a 1.2V power input, a diode 824 is disposed between the control terminal of switching device 820 and the output node of LDO 816. In other embodiments, other circuit configurations capable of forming a unidirectional current path may be used.

According to an embodiment of the present application, the memory array 802 is a general purpose flash memory array. According to an embodiment of the present application, the memory array 802 comprises a NAND memory array.

Those skilled in the art will appreciate that figure 8 is merely an illustrative example, that other elements not shown in figure 8 may be included in a UFS package, and that applications using power inputs having other voltages do not depart from the scope of the present application.

According to embodiments of the present application, pins (e.g., NC pin or VCCQ1 pin) that are left empty on a conventional UFS package may be utilized to provide additional external power inputs to power the circuit portions inside the UFS package. Through adding simple control circuit in the UFS encapsulation for when there is additional external power input, one or more LDOs in the UFS encapsulation can stop working, do not carry out voltage conversion, thereby reduce the consumption, reduce the heat that produces during the operation, and then improve the reliability of UFS storage data.

On the other hand, since the existing pins of the conventional UFS package are used, and the improved UFS package provided by the present application can still use the LDO to provide the supply voltage for the internal circuit, as in the conventional UFS package, without additional external power input, the improved UFS package can be well compatible with the existing storage system, and can directly replace the existing UFS package without modifying other parts of the system.

It will be appreciated by those skilled in the art that although described herein primarily in connection with UFS packages and LDOs in UFS packages, the control circuitry provided herein may also be applied to other semiconductor package components, or for selectively disabling other types of voltage regulators for the purpose of reducing power consumption.

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present invention is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control circuit connected to an internal circuit, the control circuit comprising:

a first node for receiving a first power input;

a second node to receive a second power input, the second node connected to the internal circuit;

a voltage regulator having an input node and an output node, the output node being connected to the internal circuit; and

a switching device connected between the first node and the input node of the voltage regulator;

wherein the content of the first and second substances,

a control terminal of the switching device is connected to the second node and the switching device disconnects the first node from the input node of the voltage regulator when the second power supply input is a second voltage value.

2. The control circuit of claim 1 wherein the switching device conducts the connection between the first node and the input node of the voltage regulator when the second power supply input is not at the second voltage value.

3. The control circuit of claim 2, wherein the switching device turns on the connection between the first node and the input node of the voltage regulator when the second power supply input is a ground voltage.

4. The control circuit of claim 2, wherein when the switching device conducts the connection between the first node and the input node of the voltage regulator and the first power supply input is a first voltage value, the voltage at the output node of the voltage regulator has the second voltage value.

5. The control circuit of claim 1, wherein the switching device comprises a transistor or a fuse.

6. The control circuit of claim 5, wherein the switching device comprises a P-channel metal-oxide-semiconductor field-effect transistor, wherein the first node is connected to a source of the P-channel metal-oxide-semiconductor field-effect transistor, the second node is connected to a gate of the P-channel metal-oxide-semiconductor field-effect transistor, and the input node of the voltage regulator is connected to a drain of the P-channel metal-oxide-semiconductor field-effect transistor.

7. The control circuit of claim 6, further comprising a resistor connected between the gate of the P-channel metal oxide semiconductor field effect transistor and a ground node.

8. The control circuit of claim 1, wherein the voltage regulator comprises a low dropout linear regulator.

9. The control circuit of claim 4, wherein the first voltage value is greater than the second voltage value.

10. A semiconductor package component, comprising:

the control circuit of any one of claims 1-9; and

the internal circuitry, wherein the control circuitry and the internal circuitry are disposed on the same chip.

11. The semiconductor package of claim 10, wherein the internal circuitry comprises a memory controller.

12. The semiconductor package device of claim 11, further comprising:

a memory array connected to the memory controller.

13. The semiconductor package of claim 12, wherein the memory array comprises a NAND memory array.

14. The semiconductor package of claim 12, wherein the memory array comprises a general purpose flash memory array.