CN211205523U - Photoelectric power meter - Google Patents
Photoelectric power meter Download PDFInfo
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- CN211205523U CN211205523U CN201922081350.6U CN201922081350U CN211205523U CN 211205523 U CN211205523 U CN 211205523U CN 201922081350 U CN201922081350 U CN 201922081350U CN 211205523 U CN211205523 U CN 211205523U
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Abstract
The application discloses photoelectric power meter includes: the photoelectric conversion circuit, the gain selection circuit, the main controller and the display circuit; the photoelectric conversion circuit is used for converting the collected optical signal of the light source to be detected into a voltage signal; the gain selection circuit is used for comparing the voltage signal with a preset reference voltage and selecting the amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to the comparison result; the main controller is used for measuring the voltage signal amplified by the amplification factor to obtain corresponding optical power; the display circuit is used for displaying optical power, and solves the technical problems that an existing photoelectric power meter for manual gear shifting is troublesome to operate and easily burns out a circuit.
Description
Technical Field
The application relates to the technical field of power meters, in particular to a photoelectric power meter.
Background
With the development of the optical communication industry, higher requirements are put forward on the photoelectric detection module. For detection of optical power, a range of 0dBm to-30 dBm or more is typically required.
A photoelectric power meter is a commonly used photoelectric detection module. The photoelectric power is generally required to be in a range of 0dBm to-30 dBm or more, and the conventional optical power meter utilizing the photoelectric characteristic of the photodiode manually shifts gears, namely, changes the amplification factor to realize the optical detection of different powers. The manual gear shifting mode is troublesome to operate and easily burns out a circuit.
SUMMERY OF THE UTILITY MODEL
In view of this, the application provides a photoelectric power meter, has solved the photoelectric power meter troublesome poeration of current manual shift, and the technical problem who burns out the circuit easily.
The application provides a photoelectric power meter, includes: the photoelectric conversion circuit, the gain selection circuit, the main controller and the display circuit;
the photoelectric conversion circuit is used for converting the collected optical signal of the light source to be detected into a voltage signal;
the gain selection circuit is used for comparing the voltage signal with a preset reference voltage and selecting an amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to a comparison result;
the main controller is used for measuring the voltage signal amplified by the amplification factor to obtain corresponding optical power;
the display circuit is used for displaying the optical power.
Optionally, the gain selection circuit comprises: a voltage comparison circuit and a self-locking circuit;
the voltage comparison circuit is used for comparing the voltage signal with a preset reference voltage to obtain a comparison result;
the self-locking circuit is used for inputting the comparison result to the photoelectric conversion circuit, so that the photoelectric conversion circuit selectively amplifies the amplification factor of the voltage signal according to the comparison result.
Optionally, the voltage comparison circuit comprises a voltage comparator U1, a relay R L2 and a voltage comparator U8;
the self-locking circuit includes: the circuit comprises a first self-locking circuit and a second self-locking circuit;
the positive input end of the voltage comparator U1 is connected with the output end of the photoelectric conversion circuit, and the output end of the voltage comparator U1 is connected to the pin 1 of the relay R L2 through the first self-locking circuit;
pin 2 of the relay R L2 is grounded, pin 3 is connected with the output end of the photoelectric conversion circuit, and pin 4 is connected with the positive input end of the voltage comparator U8;
the output end of the voltage comparator U8 is connected with the photoelectric conversion circuit through the second self-locking circuit.
Optionally, the first self-locking circuit comprises a relay R L1, a diode D1, a diode D2, an amplifier U3 and a relay R L5;
pin 1 of the relay R L1 is connected with the output end of the voltage comparator U1, pin 2 is grounded, pin 3 is connected with a power supply voltage, and pin 4 is connected with the positive input end of the amplifier U3, the anode of the diode D1 and pin 3 of the relay R L5;
the cathode of the diode D1 is connected with the anode of the diode D2;
the cathode of the diode D2 is connected with the inverting input end of the amplifier U3;
the output end of the amplifier U3 is connected with a pin 1 of the relay R L2;
pin 1 of the relay R L5 is used for inputting a first control signal, pin 5 is connected with pin 1 of the relay R L2, and pin 2 and pin 4 are both grounded.
Optionally, the second self-locking circuit comprises a relay R L3, a diode D4, a diode D5, an amplifier U9 and a relay R L4;
pin 1 of the relay R L3 is connected with the output end of the voltage comparator U8, pin 2 is grounded, pin 3 is connected with a power supply voltage, and pin 4 is connected with the positive input end of the amplifier U9, the anode of the diode D4 and pin 3 of the relay R L4;
the cathode of the diode D4 is connected with the anode of the diode D5;
the cathode of the diode D5 is connected with the inverting input end of the amplifier U9;
the output end of the amplifier U9 is connected with the photoelectric conversion circuit;
and a second control signal is input into a pin 1 of the relay R L4, a pin 5 is connected with the photoelectric conversion circuit, and a pin 2 and a pin 4 are both grounded.
Optionally, the method further comprises: a peak hold circuit;
the input end of the peak holding circuit is connected with the output end of the gain selection circuit, and the output end of the peak holding circuit is connected with the input end of the main controller;
the peak holding circuit is used for holding the peak value of the amplified voltage signal.
Optionally, the peak hold circuit comprises: an amplifier U7, a diode D6, a diode D7, a diode D8, a capacitor C20 and a voltage comparator U10;
the positive input end of the amplifier U7 is connected with the output end of the gain selection circuit, the reverse input end is connected with the output end of the voltage comparator U10 and the anode of the diode D8, and the output end is connected with the cathode of the diode D8 and the anode of the diode D6;
the cathode of the diode D6 is connected with the anode of the diode D7;
the cathode of the diode D7 is connected with the first end of the capacitor C20 and the positive input end of the voltage comparator U10;
the second end of the capacitor C20 is grounded;
the inverting input end of the voltage comparator U10 is connected with the output end of the voltage comparator U10, and the output end of the voltage comparator U10 is connected with the input end of the main controller.
Optionally, the peak hold circuit further comprises: a triode Q4, a resistor R19 and a resistor R20;
the collector of the triode is connected with the cathode of the diode D7, the base of the triode is connected with the first end of the resistor R19 and the first end of the resistor R20, and the emitter of the triode is grounded;
the second end of the resistor R20 is grounded;
the second end of the resistor R19 is used for inputting a discharge signal.
Optionally, a photodiode PIN, an analog switch, a resistor R1, a resistor R2, and a resistor R3;
the input end of the photodiode PIN is used for collecting optical signals of a light source to be detected, and the output end of the photodiode PIN is respectively connected with the first end of the resistor R1, the first end of the resistor R2 and the first end of the resistor R3;
a second end of the resistor R1, a second end of the resistor R2, and a second end of the resistor R3 are respectively connected to a first transmission channel, a second transmission channel, and a third transmission channel of the analog switch, wherein resistance values of the resistor R1, the resistor R2, and the resistor R3 are different;
the input end of the analog switch is connected with the gain selection circuit, and the output end of the analog switch is connected with the voltage comparison circuit and the main controller.
Optionally, the photoelectric conversion circuit further includes: an amplifier U4;
the reverse input end of the amplifier U4 is connected with the output end of the photodiode PIN, the forward input end of the amplifier U4 is grounded, and the output end of the amplifier U4 is negatively fed back.
According to the technical scheme, the method has the following advantages:
the application provides a photoelectric power meter includes: the photoelectric conversion circuit, the gain selection circuit, the main controller and the display circuit; the photoelectric conversion circuit is used for converting the collected optical signal of the light source to be detected into a voltage signal; the gain selection circuit is used for comparing the voltage signal with a preset reference voltage and selecting the amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to the comparison result; the main controller is used for measuring the voltage signal amplified by the amplification factor to obtain corresponding optical power; and the display circuit is used for displaying the optical power.
In this application, after photoelectric conversion circuit converts the light signal that detects into voltage signal, gain selection circuit is according to the contrast result of this voltage signal and preset reference voltage, automatically adaptation ground adjustment is used for the magnification of amplification voltage signal among the photoelectric conversion circuit, then main control unit carries out the measured light power to the voltage signal after the amplification, at last by display circuit output this light power, compare in the photoelectric power meter of manual shift among the prior art, easy operation, and circuit structure has been protected, thereby the photoelectric power meter trouble of having solved current manual shift is operated, and the technical problem of circuit is burnt out easily.
Drawings
Fig. 1 is a schematic structural diagram of an optoelectronic power meter in an embodiment of the present application;
FIG. 2 is a schematic diagram of a gain selection circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a peak hold circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a photoelectric conversion circuit in an embodiment of the present application;
fig. 5 is a schematic flowchart of an application example of an optoelectronic power meter in an embodiment of the present application.
Detailed Description
The embodiment of the application provides a photoelectric power meter, and the photoelectric power meter that has solved current manual shift is troublesome to operate, and burns out the technical problem of circuit easily.
The technical solutions of the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the embodiments in the present application.
In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the embodiments of the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have specific orientations, be configured in specific orientations, and operate, and thus, should not be construed as limiting the embodiments of the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are used broadly and are defined as, for example, a fixed connection, an exchangeable connection, an integrated connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection through an intermediate medium, and a communication between two elements, unless otherwise explicitly stated or limited. Specific meanings of the above terms in the embodiments of the present application can be understood in specific cases by those of ordinary skill in the art.
For ease of understanding, the following provides a detailed description of an optoelectronic power meter provided herein.
The embodiment of the present application provides a first embodiment of an optoelectronic power meter, and specifically refers to fig. 1.
The photoelectric power meter in this embodiment includes: the photoelectric conversion circuit, the gain selection circuit, the main controller and the display circuit; the photoelectric conversion circuit is used for converting the collected optical signal of the light source to be detected into a voltage signal; the gain selection circuit is used for comparing the voltage signal with a preset reference voltage and selecting the amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to the comparison result; the main controller is used for measuring the voltage signal amplified by the amplification factor to obtain corresponding optical power; and the display circuit is used for displaying the optical power.
In this embodiment, after the photoelectric conversion circuit converts the detected optical signal into a voltage signal, the gain selection circuit automatically adaptively adjusts the amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to the comparison result between the voltage signal and the preset reference voltage, then the main controller measures the optical power of the amplified voltage signal, and finally the display circuit outputs the optical power.
The above is a first embodiment of the photoelectric power meter provided in the present application, and the following is a second embodiment of the photoelectric power meter provided in the present application, specifically please refer to fig. 1.
The photoelectric power meter in this embodiment includes: the photoelectric conversion circuit, the gain selection circuit, the main controller and the display circuit; the photoelectric conversion circuit is used for converting the collected optical signal of the light source to be detected into a voltage signal; the gain selection circuit is used for comparing the voltage signal with a preset reference voltage and selecting the amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to the comparison result; the main controller is used for measuring the voltage signal amplified by the amplification factor to obtain corresponding optical power; and the display circuit is used for displaying the optical power.
Specifically, as shown in fig. 2, the gain selection circuit includes: a voltage comparison circuit and a self-locking circuit; the voltage comparison circuit is used for comparing the voltage signal with a preset reference voltage to obtain a comparison result; and the self-locking circuit is used for inputting the comparison result into the photoelectric conversion circuit, so that the photoelectric conversion circuit selects the amplification factor of the amplified voltage signal according to the comparison result.
Specifically, as shown in fig. 1 and fig. 2, the voltage comparison circuit comprises a voltage comparator U1, a relay R L2 and a voltage comparator U8, the self-locking circuit comprises a first self-locking circuit and a second self-locking circuit, the positive input end of the voltage comparator U1 is connected with the output end of the photoelectric conversion circuit, the output end of the voltage comparator U1 is connected to the pin 1 of the relay R L2 through the first self-locking circuit, the pin 2 of the relay R L2 is grounded, the pin 3 is connected with the output end of the photoelectric conversion circuit, the pin 4 is connected with the positive input end of the voltage comparator U8, and the output end of the voltage comparator U8 is connected with the photoelectric conversion circuit through the second self-locking circuit.
In the present embodiment, the voltage comparison circuit is formed by a comparator using an operational amplifier. In order to know the size relation between the ADC reference voltage and the amplifying circuit in real time to avoid the overranging, a voltage comparison circuit is used for comparing the sizes of the ADC reference voltage and the amplifying circuit. When the amplified voltage (the amplified voltage signal, referred to as the amplified voltage for short) is larger than the reference voltage, outputting the forward maximum undistorted voltage; when the amplified voltage < the reference voltage, an inverse maximum undistorted voltage is output. If the single power supply operational amplifier is adopted, the reverse power supply of the operational amplifier is grounded. The comparator outputs either the maximum forward undistorted voltage or 0, which is equivalent to outputting a digital signal of "0" or "1". Compared with the mode of collecting and judging by a single chip microcomputer, the voltage comparison mode has short collection time, so that the voltage comparison mode can respond to the situation that the change of an optical signal is fast.
It is understood that in this embodiment, because three amplification factors are selected, i.e., the feedback resistors have three, different resistance values represent different amplification factors. The design idea of the circuit is that the feedback resistor is selected to be 100K under the default condition, and the amplification factor needs to be large enough because a weak small signal is detected. Then, the voltage is converted into a voltage higher than the reference voltage when the weak small signal is amplified by 100K times, namely 105 times, the voltage signal cannot be transmitted to the ADC, otherwise, the main controller is easily burnt out, so that a feedback resistor 10K is replaced, namely the conversion amplification factor is obtained, and if the voltage obtained by conversion is still larger than the reference voltage, the voltage obtained by conversion is converted into the voltage of 1K.
When the voltage comparator U1 is compared with the voltage comparator U8, if the amplified voltage converted by the voltage comparator U1 is higher than the reference voltage, the voltage comparator U1 outputs high level, and the self-locking circuit locks the amplified voltage to be high level, the high level controls the relay R L2, so that the voltage signal can enter the voltage comparator U8 for further comparison.
Specifically, as shown in fig. 1 and 2, the first latching circuit comprises a relay R L1, a diode D1, a diode D2, an amplifier U3 and a relay R L5, wherein a pin 1 of the relay R L1 is connected with an output end of a voltage comparator U1, a pin 2 is grounded, a pin 3 is connected with a power supply voltage, a pin 4 is connected with a forward input end of the amplifier U3, an anode of the diode D1 and a pin 3 of the relay R L5, a cathode of the diode D1 is connected with an anode of a diode D2, a cathode of the diode D2 is connected with a reverse input end of the amplifier U3, an output end of the amplifier U3 is connected with a pin 1 of the relay R L2, a pin 1 of the relay R L5 is used for inputting a first control signal, a pin 5 is connected with a pin 1 of the relay R L2, and the pin 2 and the pin 4 are both grounded.
The output end of the first self-locking circuit is further connected with a resistor R11 and a resistor R12, and the reverse input end of the amplifier U9 is further connected with a resistor R9 and a resistor R10.
It should be noted that, as shown in fig. 1 and fig. 2, the second self-locking circuit includes a relay R L3, a diode D4, a diode D5, an amplifier U9 and a relay R L4, a pin 1 of the relay R L3 is connected to an output terminal of a voltage comparator U8, a pin 2 is grounded, a pin 3 is connected to a power supply voltage, a pin 4 is connected to a positive input terminal of the amplifier U9, an anode of the diode D4 and a pin 3 of the relay R L4, a cathode of the diode D4 is connected to an anode of a diode D5, a cathode of the diode D5 is connected to a reverse input terminal of the amplifier U9, an output terminal of the amplifier U9 is connected to a photoelectric conversion circuit, a pin 1 of the relay R L4 inputs a second control signal, a pin 5 is connected to the photoelectric conversion circuit, and both the pin 2 and the pin 4 are.
The output end of the second self-locking circuit is further connected with a resistor R15 and a resistor R16, and the reverse input end of the amplifier U9 is further connected with a resistor R13 and a resistor R14.
It should be noted that when the amplified voltage > the reference voltage, the voltage comparison circuit outputs a forward voltage, thereby changing the transmission channel of the analog switch, and thus the result is pulsed. However, the channel selection pin of the analog switch needs to be level-type, so that a 'self-locking' circuit is needed to make the channel selection pin always be high level. Thus, a "latching" circuit is designed.
When the amplified voltage is higher than the reference voltage, for example, the forward input end of the voltage comparator U8 inputs the converted voltage, if the amplified voltage is higher than the reference voltage input by the reverse input end, the voltage comparator U8 outputs the positive power supply voltage value of the amplifier, namely +5V, for the relay R L3, a path is formed on the left, so that the armature is attracted, a switch inside the relay is closed, the +5V is connected to the self-locking circuit, for the U9, the reverse input end is connected to the 2.5V voltage obtained by dividing the voltage of 5V, the forward input end and the reverse input end of the U9 are connected through the diodes D4 and D5, and the diode conduction voltage is about 0.7V, so the voltage U at the forward input end is the voltage U4 and the reverse input end, and the voltage U at the reverse input end is about 0.7in+Will compare with the reverse input end Uin-Is about 1.4V higher, i.e. Uin+＝Uin-And +2 x 0.7, while U9 forms a positive feedback loop through R L4, so that U9 amplifies the voltage until saturation, namely, the positive power supply voltage value is output to be 5V, and for R L4, P1.5 controls the self-locking circuit to stop working, because when the pin P1.5 of the single chip outputs high level, a path is formed with the ground, so that the armature of R L4 is attracted downwards, U9 has no positive feedback, and in addition, R L3 is also disconnected, so that the output of U9 slowly drops to 0V, and the next comparison is waited.
It should be noted that, for the input of the peak hold circuit, since the amplified voltage fluctuates, if the conversion time of the ADC is not fast enough, misjudgment/misdetection is easily caused. As shown in fig. 1 and 3, the photoelectric power meter in the present embodiment further includes: a peak hold circuit; the input end of the peak holding circuit is connected with the output end of the gain selection circuit, and the output end of the peak holding circuit is connected with the input end of the main controller; and a peak holding circuit for holding a peak value of the amplified voltage signal.
Specifically, the peak hold circuit includes: an amplifier U7, a diode D6, a diode D7, a diode D8, a capacitor C20 and a voltage comparator U10; the positive input end of the amplifier U7 is connected with the output end of the gain selection circuit, the negative input end is connected with the output end of the voltage comparator U10 and the anode of the diode D8, and the output end is connected with the cathode of the diode D8 and the anode of the diode D6; the cathode of the diode D6 is connected with the anode of the diode D7; the cathode of the diode D7 is connected with the first end of the capacitor C20 and the positive input end of the voltage comparator U10; the second end of the capacitor C20 is grounded; the inverting input end of the voltage comparator U10 is connected with the output end of the voltage comparator U10, and the output end of the voltage comparator U10 is connected with the input end of the main controller.
It should be noted that, when the amplified voltage is inputted, because the voltage of the pin 6 of the output pin of the amplifier U7 is higher than the voltage of the capacitor C20, the diode D6 and the diode D7 conduct in the forward direction, so that the capacitor C20 is charged, and the capacitor C20 can be charged to the amplified voltage, and when the amplified voltage is smaller than the inputted amplified voltage, i.e., the voltage of the pin 6 is lower than the voltage across the terminals C20, because of the unidirectional conduction of the diode, the input voltage cannot charge the capacitor, so that the outputted amplified voltage is still the same as the inputted amplified voltage.
Further, in order to prevent the voltage on the capacitor C20 from leaking out in time and causing an error in the next detection, the peak holding circuit further includes: a triode Q4, a resistor R19 and a resistor R20; the collector of the triode is connected with the cathode of the diode D7, the base is connected with the first end of the resistor R19 and the first end of the resistor R20, and the emitter is grounded; the second end of the resistor R20 is grounded; the second end of the resistor R19 is used for inputting a discharge signal.
It is understood that, in order to maintain the structural stability of the circuit, the peak holding circuit may further be connected with a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a resistor R17, and a resistor R18.
The triode Q4, the resistor R19 and the resistor R20 form a discharge circuit, namely, the resistor R19, the resistor R20 and the triode Q4 controlled by P1.7, wherein when P1.7 outputs a discharge signal, namely, a high level, Q4 is conducted, and C20 discharges to the ground.
As shown in fig. 4, the photoelectric conversion circuit includes: the circuit comprises a photodiode PIN, an analog switch, a resistor R1, a resistor R2 and a resistor R3; the input end of the photodiode PIN is used for collecting optical signals of a light source to be detected, and the output end of the photodiode PIN is respectively connected with the first end of the resistor R1, the first end of the resistor R2 and the first end of the resistor R3; the second end of the resistor R1, the second end of the resistor R2 and the second end of the resistor R3 are respectively connected with a first transmission channel, a second transmission channel and a third transmission channel of the analog switch, wherein the resistances of the resistor R1, the resistor R2 and the resistor R3 are different; the input end of the analog switch is connected with a gain selection circuit, and the output end of the analog switch is connected with a voltage comparison circuit and a main controller.
Further, the photoelectric conversion circuit further includes: an amplifier U4; the reverse input end of the amplifier U4 is connected with the output end of the photodiode PIN, the forward input end is grounded, and the output end is negatively fed back to the reverse input end of the amplifier U4.
It should be noted that the amplifier U4 has a negative feedback loop connected thereto, and therefore has the characteristics of "virtual short" and "virtual break", and the positive input terminal is grounded, i.e., 0V to ground. Therefore, as can be seen from the "virtual short" characteristic, the voltage at the inverting input terminal is also 0V. All in oneIn this case, the "virtual-off" characteristic indicates that the input current at the inverting input terminal is also 0A. Therefore, an input current I can be obtainedinAnd an output voltage VoutThe relationship of (1) is:
Vout＝Iin*R，
in the formula, R is the resistance value corresponding to the selected feedback resistor.
It is understood that, as shown in fig. 4, the capacitor C7, the capacitor C2, and the capacitor C1 are also connected to the photoelectric conversion circuit for the purpose of stabilizing the circuit structure.
Specifically, the main controller in this embodiment adopts an STC12C5A chip, which is an enhanced 8051 single chip microcomputer, and has the advantages of high speed, low power consumption, ultra-strong anti-interference, low price, and capability of reducing the manufacturing cost of products.
The display circuit L CD12864 in this embodiment is used as a display screen to display the optical power result on the screen, because the response relationship of the current of the diode to the input light is given in the manual or is measured by itself, the program only needs to convert the detected ADC value into the corresponding analog voltage value, then divides the analog voltage value by the amplification factor to obtain the optical response current value, and the optical power can be obtained according to the corresponding relationship.
As shown in fig. 5, the working principle of the optical power meter in this embodiment is as follows: firstly, the PIN diode receives light emitted by a light source to be detected and responds to corresponding photocurrent. The photocurrent is then fed into the amplifier U4, and since the transmission channel a pin of the analog switch is supplied with a positive power supply, i.e., always high, the default transmission channel of the analog switch is channel 1, i.e., the resistor R3 is selected as a feedback resistor, and an amplified voltage is output via the transmission channel. Then enters a voltage comparator U1, if the amplified voltage < the reference voltage Vref, the output of U1 is a negative power voltage value, and the negative power terminal of U1 is grounded, so the output is low level 0V at this time, and the transmission channel of the analog switch is not changed. The amplified voltage is then held stable by a peak hold circuit, and the main controller performs ADC to detect the peak voltage and display the detected optical power value.
If the amplified voltage is greater than the ADC reference voltage Vref, the voltage comparator U1 outputs the voltage value of the positive power supply end of U1, namely +5V, then the coil of the iron core of the relay is electrified, the armature is attracted, and 5V is connected to the self-locking circuit. In the self-locking circuit, the amplifier U3 introduces positive feedback, and the forward input end of the amplifier U3 is higher than the reverse input end by two diode conducting voltages, so that self-locking is realized through the positive feedback, and finally the amplifier U3 outputs +5V voltage. And the +5V voltage outputted from the amplifier U3 is inputted to the pin control B pin of the analog switch, so as to change the transmission channel, the level condition of the channel selection pin "CBA" of the analog switch becomes 011, and then the channel 3, i.e. the selection resistor 10K, is turned on as the feedback resistor. Without the self-locking circuit, once the transmission channel of the analog switch is changed, the output of the voltage comparator U1 returns to the low level, which in turn causes the analog switch to be turned on, i.e., channel 1. Therefore, in order to always obtain high level for the transmission channel pin of the analog switch, a self-locking circuit is added. The reverse terminal voltage of the operational amplifier in the self-locking circuit is 0.5VCC, so when the self-locking circuit is not input, the output of the amplifier U3 is always low level.
In addition, when the output of the amplifier U3 is high level, the iron core coil of the relay R L2 is electrified, the armature is attracted, and then the voltage enters the voltage comparator U8. the working principle is the same as the above, when 10k is used as a feedback resistor, namely the amplification factor is 104, the amplified voltage is higher than the reference voltage Vref of the ADC, the comparator U8 outputs high level, and the self-locking circuit outputs high level all the time, so that the level of three channel control pins CBA of the analog switch is 111, 1k resistor is selected as the feedback resistor, namely the amplification factor is adjusted again.
In the gain selection circuit diagram, P2.3 and P2.4 are detection pins for determining which feedback resistor, i.e., amplification factor, the ADC result is obtained at.
In this embodiment, after the photoelectric conversion circuit converts the detected optical signal into a voltage signal, the gain selection circuit automatically adaptively adjusts the amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to the comparison result between the voltage signal and the preset reference voltage, then the main controller measures the optical power of the amplified voltage signal, and finally the display circuit outputs the optical power.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. An optoelectronic power meter, comprising: the device comprises a main controller, a photoelectric conversion circuit, a gain selection circuit, a main controller and a display circuit;
the photoelectric conversion circuit is used for converting the collected optical signal of the light source to be detected into a voltage signal;
the gain selection circuit is used for comparing the voltage signal with a preset reference voltage and selecting an amplification factor for amplifying the voltage signal in the photoelectric conversion circuit according to a comparison result;
the main controller is used for measuring the voltage signal amplified by the amplification factor to obtain corresponding optical power;
the display circuit is used for displaying the optical power.
2. The optical-electrical power meter according to claim 1, wherein the gain selection circuit comprises: a voltage comparison circuit and a self-locking circuit;
the voltage comparison circuit is used for comparing the voltage signal with a preset reference voltage to obtain a comparison result;
the self-locking circuit is used for inputting the comparison result to the photoelectric conversion circuit, so that the photoelectric conversion circuit selectively amplifies the amplification factor of the voltage signal according to the comparison result.
3. The photoelectric power meter according to claim 2, wherein the voltage comparison circuit comprises a voltage comparator U1, a relay R L2, and a voltage comparator U8;
the self-locking circuit includes: the circuit comprises a first self-locking circuit and a second self-locking circuit;
the positive input end of the voltage comparator U1 is connected with the output end of the photoelectric conversion circuit, and the output end of the voltage comparator U1 is connected to the pin 1 of the relay R L2 through the first self-locking circuit;
pin 2 of the relay R L2 is grounded, pin 3 is connected with the output end of the photoelectric conversion circuit, and pin 4 is connected with the positive input end of the voltage comparator U8;
the output end of the voltage comparator U8 is connected with the photoelectric conversion circuit through the second self-locking circuit.
4. The photoelectric power meter of claim 3, wherein the first self-locking circuit comprises a relay R L1, a diode D1, a diode D2, an amplifier U3 and a relay R L5;
pin 1 of the relay R L1 is connected with the output end of the voltage comparator U1, pin 2 is grounded, pin 3 is connected with a power supply voltage, and pin 4 is connected with the positive input end of the amplifier U3, the anode of the diode D1 and pin 3 of the relay R L5;
the cathode of the diode D1 is connected with the anode of the diode D2;
the cathode of the diode D2 is connected with the inverting input end of the amplifier U3;
the output end of the amplifier U3 is connected with a pin 1 of the relay R L2;
pin 1 of the relay R L5 is used for inputting a first control signal, pin 5 is connected with pin 1 of the relay R L2, and pin 2 and pin 4 are both grounded.
5. The photoelectric power meter of claim 3, wherein the second self-locking circuit comprises a relay R L3, a diode D4, a diode D5, an amplifier U9 and a relay R L4;
pin 1 of the relay R L3 is connected with the output end of the voltage comparator U8, pin 2 is grounded, pin 3 is connected with a power supply voltage, and pin 4 is connected with the positive input end of the amplifier U9, the anode of the diode D4 and pin 3 of the relay R L4;
the cathode of the diode D4 is connected with the anode of the diode D5;
the cathode of the diode D5 is connected with the inverting input end of the amplifier U9;
the output end of the amplifier U9 is connected with the photoelectric conversion circuit;
and a second control signal is input into a pin 1 of the relay R L4, a pin 5 is connected with the photoelectric conversion circuit, and a pin 2 and a pin 4 are both grounded.
6. The photoelectric power meter of claim 1, further comprising: a peak hold circuit;
the input end of the peak holding circuit is connected with the output end of the gain selection circuit, and the output end of the peak holding circuit is connected with the input end of the main controller;
the peak holding circuit is used for holding the peak value of the amplified voltage signal.
7. The photoelectric power meter of claim 6, wherein the peak hold circuit comprises: an amplifier U7, a diode D6, a diode D7, a diode D8, a capacitor C20 and a voltage comparator U10;
the positive input end of the amplifier U7 is connected with the output end of the gain selection circuit, the reverse input end is connected with the output end of the voltage comparator U10 and the anode of the diode D8, and the output end is connected with the cathode of the diode D8 and the anode of the diode D6;
the cathode of the diode D6 is connected with the anode of the diode D7;
the cathode of the diode D7 is connected with the first end of the capacitor C20 and the positive input end of the voltage comparator U10;
the second end of the capacitor C20 is grounded;
the inverting input end of the voltage comparator U10 is connected with the output end of the voltage comparator U10, and the output end of the voltage comparator U10 is connected with the input end of the main controller.
8. The optical-electrical power meter according to claim 7, wherein the peak-hold circuit further comprises: a triode Q4, a resistor R19 and a resistor R20;
the collector of the triode is connected with the cathode of the diode D7, the base of the triode is connected with the first end of the resistor R19 and the first end of the resistor R20, and the emitter of the triode is grounded;
the second end of the resistor R20 is grounded;
the second end of the resistor R19 is used for inputting a discharge signal.
9. The photoelectric power meter according to claim 1, wherein the photoelectric conversion circuit comprises: the circuit comprises a photodiode PIN, an analog switch, a resistor R1, a resistor R2 and a resistor R3;
the input end of the photodiode PIN is used for collecting optical signals of a light source to be detected, and the output end of the photodiode PIN is respectively connected with the first end of the resistor R1, the first end of the resistor R2 and the first end of the resistor R3;
a second end of the resistor R1, a second end of the resistor R2, and a second end of the resistor R3 are respectively connected to a first transmission channel, a second transmission channel, and a third transmission channel of the analog switch, wherein resistance values of the resistor R1, the resistor R2, and the resistor R3 are different;
the input end of the analog switch is connected with the gain selection circuit, and the output end of the analog switch is connected with the voltage comparison circuit and the main controller.
10. The photoelectric power meter of claim 9, wherein the photoelectric conversion circuit further comprises: an amplifier U4;
the reverse input end of the amplifier U4 is connected with the output end of the photodiode PIN, the forward input end of the amplifier U4 is grounded, and the output end of the amplifier U4 is negatively fed back.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922081350.6U CN211205523U (en) | 2019-11-27 | 2019-11-27 | Photoelectric power meter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922081350.6U CN211205523U (en) | 2019-11-27 | 2019-11-27 | Photoelectric power meter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211205523U true CN211205523U (en) | 2020-08-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922081350.6U Expired - Fee Related CN211205523U (en) | 2019-11-27 | 2019-11-27 | Photoelectric power meter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211205523U (en) |
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2019
- 2019-11-27 CN CN201922081350.6U patent/CN211205523U/en not_active Expired - Fee Related
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