CN211197023U

CN211197023U - Silicon chip integration packing box

Info

Publication number: CN211197023U
Application number: CN201922064108.8U
Authority: CN
Inventors: 马劲峰
Original assignee: Strong Core Technology Huai'an Co ltd
Current assignee: Qiangxin Technology (Nantong) Co.,Ltd.
Priority date: 2019-11-26
Filing date: 2019-11-26
Publication date: 2020-08-07
Anticipated expiration: 2029-11-26

Abstract

The utility model discloses a silicon wafer integrated packing box, which comprises a box body; the silicon wafer carrier is detachably arranged in the box body, a single silicon wafer carrier is provided with a plurality of silicon wafer accommodating grooves, and a plurality of limiting clamping grooves are formed in two sides of the single silicon wafer carrier; the limiting component is detachably arranged in the box body and is matched with the limiting clamping grooves on the at least one silicon wafer carrier, and the at least one silicon wafer carrier is positioned through the limiting component. The utility model discloses the box uses plastics integration injection moulding, and the built-in integrative at least one silicon chip carrier that is formed with a plurality of silicon chip storage tanks that forms of box, spacing picture peg form in the spacing draw-in groove of silicon chip carrier fixedly, effectively reduce the silicon chip carrier because of sloshing and lead to the condition that the silicon chip damaged, convenient and practical, only need become the silicon chip with the freshness protection package suit back in hundreds of uses in addition, directly put into independent silicon chip storage tank can, can save the multichannel process, alleviate the work load of packing link.

Description

Silicon chip integration packing box

Technical Field

The utility model relates to a silicon chip packing transportation technical field, concretely relates to silicon chip integration packing box.

Background

Currently, finished silicon wafers processed at the wire-cutting end are generally prepared by placing oil absorbing paper in front of and behind every 100 wafers, then sealing the openings by using freshness protection packages, and labeling the openings. Then packaging into a foam box according to every 400 pieces, finally forming a sealed foam box according to every 400 pieces, and placing every 4 or 6 foams into a carton to form 1600 or 2400 pieces into a box for storage. However, this approach has the following disadvantages: (1) a large number of foam boxes are purchased and placed in a warehouse, so that the occupied area is large, the potential safety hazard is high, and the foam boxes are not suitable for the modern development requirement; (2) the foam box is easy to damage, cannot be recycled in large batch, is easy to form resource waste, and brings great cost pressure to enterprises; (3) the foam box is directly placed in the packing box, and in the transportation, the condition that the foam box appears shaking easily, probably leads to the phenomenon that the silicon chip damaged, especially the corner position of silicon chip, the practicality is relatively poor.

Therefore, in order to solve the technical problem of the above existence, the utility model provides a silicon chip integration packing box.

SUMMERY OF THE UTILITY MODEL

The utility model provides a silicon chip integration packing box, include:

a box body;

the silicon wafer carrier is detachably arranged in the box body, a single silicon wafer carrier is provided with a plurality of silicon wafer accommodating grooves, and a plurality of limiting clamping grooves are formed in two sides of the single silicon wafer carrier;

and the limiting component is detachably arranged in the box body and is matched with the plurality of limiting clamping grooves on the at least one silicon wafer carrier, and the at least one silicon wafer carrier is positioned through the limiting component.

According to the technical scheme, the silicon wafer accommodating grooves are independent unit cells formed on at least one silicon wafer carrier, and the silicon wafer accommodating grooves are arranged at intervals through the partition plates.

According to the technical scheme, the partition plate is provided with the groove, and the plurality of silicon wafer accommodating grooves are formed between every two silicon wafer accommodating grooves and the partition plate to form limiting clamping grooves matched with the limiting assemblies.

By adopting the technical scheme, the limiting assembly comprises a limiting plugboard, and the limiting plugboard is inserted into the limiting clamping groove on at least one silicon wafer carrier to realize fixation.

According to the technical scheme, the silicon wafer corner protecting pad is detachably arranged at the four corners of the silicon wafer accommodating groove.

By adopting the technical scheme, the single silicon wafer corner protection pad is made of soft materials.

By adopting the technical scheme, at least one silicon wafer carrier is made of hard materials.

By adopting the technical scheme, the box body is made of plastic materials.

The utility model has the advantages that:

1. the utility model discloses the box uses plastics integration injection moulding, and the box embeds at least one silicon chip carrier that an organic whole formed with a plurality of silicon chip storage tanks, and spacing picture peg pegs are pegged graft and are formed fixedly in the spacing draw-in groove of silicon chip carrier, effectively reduce the silicon chip carrier and lead to the condition that the silicon chip damaged because of shaking, convenient and practical, and silicon chip carrier adopts hard material, and is not fragile in addition, can reciprocate the circulation and use, and it is convenient to retrieve, need not prepare a large amount of stocks;

2. the utility model discloses a plurality of silicon chip storage tanks are two liang between an organic whole be formed with the baffle and carry out the interval, effectively avoid the silicon chip in the single silicon chip storage tank to cause the interference to the silicon chip in all the other silicon chip storage tanks, be provided with the recess on the baffle moreover and make the height that highly is less than the silicon chip storage tank of baffle, make things convenient for getting of silicon chip to put, only need become the silicon chip with the freshness protection package suit back in hundred, directly put into independent silicon chip storage tank can, can save the multichannel process, alleviate the work load of packing link.

Drawings

Fig. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a top view of fig. 1.

Fig. 3 is a partially enlarged schematic view of a portion a of fig. 2.

Fig. 4 is a schematic structural diagram of the silicon wafer carrier of the present invention.

Fig. 5 is a schematic structural view of the utility model discloses install spacing picture peg in the box.

The reference numbers in the figures illustrate: 1. a box body; 2. a silicon wafer carrier; 21. a silicon wafer accommodating groove; 22. a limiting clamping groove; 23. a partition plate; 231. a groove; 3. a limiting inserting plate; 4. silicon wafer corner protector pad.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.

Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present invention, and should not be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship indicated based on the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

Referring to fig. 1 to 5, the present invention relates to a silicon wafer integrated packing box, which comprises a box body 1; at least one silicon wafer carrier 2 is detachably arranged in the box body 1, a single silicon wafer carrier 2 is provided with a plurality of silicon wafer accommodating grooves 21, and a plurality of limiting clamping grooves 22 are formed in two sides of the single silicon wafer carrier 2; the limiting component is detachably arranged in the box body 1 and is matched with the limiting clamping grooves 22 on the silicon wafer carrier 2, and the limiting component is used for positioning the silicon wafer carrier 2.

In this embodiment, the silicon wafer accommodating grooves 21 are independent unit cells formed on at least one silicon wafer carrier 2, the silicon wafer accommodating grooves 21 are arranged at intervals through the partition plates 23, on one hand, the partition plates 23 are integrally formed between the silicon wafer accommodating grooves 21 to separate the silicon wafer accommodating grooves, so that interference of silicon wafers in the silicon wafer accommodating grooves 21 to silicon wafers in other silicon wafer accommodating grooves 21 is effectively avoided, grooves 231 are formed in the single partition plate 23 on the other hand, the arrangement of the grooves 231 in the partition plate 23 enables the height of the partition plate 23 to be smaller than the height of the silicon wafer accommodating grooves 21, and the silicon wafers are conveniently and rapidly taken and placed through the design of the.

In this embodiment, a plurality of silicon chip storage tanks 21 are formed with spacing draw-in groove 22 with spacing subassembly looks adaptation between two liang, spacing subassembly includes spacing picture peg 3, spacing picture peg 3 is pegged graft and is realized fixing in spacing draw-in groove 22 on at least one silicon chip carrier 2, at least one silicon chip carrier 2 is fixed through spacing picture peg 3, compare in silicon chip carrier 2 and directly place in box 1, the condition that leads to the silicon chip to damage because of silicon chip carrier 2 rocks can effectively be reduced in the setting of spacing picture peg 3.

In this embodiment, the detachable silicon chip angle bead pad of installing in the four corners position of single silicon chip storage tank 21, single silicon chip angle bead pad adopt soft materials, and the protection is wrapped up to the corner position of silicon chip through soft materials's silicon chip angle bead pad, can show the problem that reduces the silicon chip corner and damage, and soft materials can be soft rubber, also can be other soft materials certainly, the utility model discloses not use this as the restriction.

In this embodiment, at least one silicon chip carrier 2 adopts hard material, and silicon chip carrier 2 of hard material is not fragile, and hard material can be the stereoplasm sponge, also can be other soft materials certainly, the utility model discloses not regard this as the restriction, box 1 adopts the plastics material in addition, and box 1 uses plastics integration injection moulding, can reciprocal cycle use, and it is convenient to retrieve, need not prepare a large amount of stocks.

The utility model has the advantages that: the utility model discloses the box uses plastics integration injection moulding, and the built-in integrative at least one silicon chip carrier that is formed with a plurality of silicon chip storage tanks that forms of box, spacing picture peg form in the spacing draw-in groove of silicon chip carrier fixedly, effectively reduce the silicon chip carrier because of sloshing and lead to the condition that the silicon chip damaged, convenient and practical, only need become the silicon chip with the freshness protection package suit back in hundreds of uses in addition, directly put into independent silicon chip storage tank can, can save the multichannel process, alleviate the work load of packing link.

The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutes or changes made by the technical personnel in the technical field on the basis of the utility model are all within the protection scope of the utility model. The protection scope of the present invention is subject to the claims.

Claims

1. A silicon chip integration packing box is characterized by comprising:

a box body (1);

the silicon wafer carrier (2) is detachably arranged in the box body (1), a single silicon wafer carrier (2) is provided with a plurality of silicon wafer accommodating grooves (21), and a plurality of limiting clamping grooves (22) are formed in two sides of the single silicon wafer carrier (2);

the limiting assembly is detachably arranged in the box body (1) and is matched with the limiting clamping grooves (22) on the silicon wafer carrier (2), and the limiting assembly is used for positioning the silicon wafer carrier (2).

2. The silicon wafer integrated packaging box of claim 1, wherein: the silicon wafer accommodating grooves (21) are independent unit cells formed on at least one silicon wafer carrier (2), and the silicon wafer accommodating grooves (21) are arranged at intervals through partition plates (23).

3. The silicon wafer integrated packaging box of claim 2, wherein: a groove (231) is formed in each partition plate (23), and a limiting clamping groove (22) matched with the limiting component is formed between every two silicon wafer accommodating grooves (21) and the partition plates (23).

4. The silicon wafer integrated packaging box of claim 3, wherein: the limiting component comprises a limiting inserting plate (3), and the limiting inserting plate (3) is inserted into a limiting clamping groove (22) on at least one silicon wafer carrier (2) to realize fixation.

5. The silicon wafer integrated packaging box of claim 1, wherein: the silicon wafer corner protecting pads (4) are detachably arranged at the four corners of the single silicon wafer accommodating groove (21).

6. The silicon wafer integrated packaging box of claim 5, wherein: the silicon wafer corner protection pad (4) is made of soft materials.

7. The silicon wafer integrated packaging box of claim 1, wherein: at least one silicon wafer carrier (2) is made of hard material.

8. The silicon wafer integrated packaging box of claim 1, wherein: the box body (1) is made of plastic materials.