CN211184327U

CN211184327U - Load driving circuit with power switch adjusting function and lighting driving system thereof

Info

Publication number: CN211184327U
Application number: CN201921404957.7U
Authority: CN
Inventors: 张波
Original assignee: Shenzhen Kiwi Microelectronic Co ltd
Current assignee: Shenzhen Biyi Microelectronics Co., Ltd
Priority date: 2019-08-27
Filing date: 2019-08-27
Publication date: 2020-08-04
Anticipated expiration: 2029-08-27

Abstract

The utility model discloses a take switch regulatory function's load drive circuit and lighting driving system thereof, the switch is coupled between load drive circuit and power, and load drive circuit has current feedback pin and at least one configuration pin and includes: the output end of the switch detection circuit provides a power switch signal representing whether the switching action of the power switch meets the preset condition or not; the input end of the reference setting circuit is coupled with the switch detection circuit, the reference setting circuit is selectively coupled with the configuration component, and the output end of the reference setting circuit provides a current reference; and a conduction control circuit, the input end of which is coupled with the reference setting circuit, and the output end of which is coupled with the control end of the power transistor. The utility model discloses the application can conveniently realize many grades of output current's arbitrary adjustable, satisfies the different demands of user in a flexible way.

Description

Load driving circuit with power switch adjusting function and lighting driving system thereof

Technical Field

The utility model relates to a power electronic technology field, concretely but not limited to relate to a load drive circuit and lighting drive system.

Background

With the popularization of L ED driving, the demand for light brightness adjustment gradually derives, and at present, the simplest method is to use a wall switch (hereinafter also referred to as a power switch), fig. 1 is a schematic circuit diagram of light brightness adjustment performed by the wall switch in the prior art, as shown in fig. 1, an output current is adjusted by the power switch coupled between an AC power end and a rectifying circuit, a basic principle of the method is that a L ED driver determines an interval time between front and rear switching of the wall switch and switching on, and generally, the interval time is less than 7s, which means that the output current needs to be adjusted, otherwise, the output current is not changed when the normal switch is switched on next time.

The basic principle of the existing switch step dimming is that 3 output current references are set inside a chip, and when the switching of a power switch is detected (the interval time is less than 7s), the reference sequence of the 3 output currents is switched to meet the purpose of output current regulation.

Fig. 2 is a circuit diagram of a lamp brightness adjusting system in the prior art, fig. 3 is a circuit diagram of a lamp brightness adjusting control circuit in the prior art, fig. 4 is a diagram of a relationship of lamp brightness adjustment in the prior art, fig. 2 to fig. 4 show that generally, whether a switch is turned Off or dimming is normally judged, which is identified by a rule of a voltage VDD at an input terminal of a switch circuit, because the voltage VDD enters a low voltage latch (UV L O) due to insufficient Power after the switch is powered Off, and then the voltage VDD is slowly decreased due to a decrease in consumption current to a very low value, and if the voltage VDD reaches a turn-on voltage again before the voltage VDD decreases to a POR (Power Off Reset, system restart reference value), an internal output current reference is changed.

The existing switch stepping dimming has a problem that the proportion of output current is fixed, and the light efficiency is not flexible enough in design. For example, different light intensities or light intensity ratios are required for different applications, and adaptive design cannot be realized by the existing chip products. In addition, the dimming current output of the current scheme is adjusted from large to small, cannot be adjusted from small to large, and cannot meet different living habits and living requirements of the public.

In view of the above, there is a need to design a new dimming control method to overcome the above-mentioned drawbacks of the existing dimming control methods.

SUMMERY OF THE UTILITY MODEL

In order to solve the one or more problems, the utility model provides a load drive circuit and lighting driving system who has power switch dimming function.

According to an aspect of the utility model, a load drive circuit, coupling switch, wherein switch coupling is between load drive circuit and power, its characterized in that, load drive circuit has current feedback pin and at least one configuration pin, and wherein the sampling resistance is coupled to the current feedback pin, and every configuration pin is coupled a configuration part, and load drive circuit includes: the switch detection circuit is provided with an input end and an output end, and the output end of the switch detection circuit provides a power switch signal for representing whether the switching action of the power switch meets the preset condition; a reference setting circuit having an input and an output, wherein the input of the reference setting circuit is coupled to the switch detection circuit, the reference setting circuit is selectively coupled to the configuration component, and the output of the reference setting circuit provides a current reference; and the conduction control circuit is provided with an input end and an output end, the input end of the conduction control circuit is coupled with the reference setting circuit, and the output end of the conduction control circuit is coupled with the control end of the power transistor.

In one embodiment, the switch detection circuit, the reference setting circuit and the conduction control circuit are disposed in a semiconductor wafer, and the sampling resistor and the configuration component are disposed outside the semiconductor wafer.

In one embodiment, the input terminal of the switch detection circuit is coupled to the sampling resistor.

In one embodiment, the reference setting circuit includes: the switch selection circuit is provided with an input end and a plurality of output ends, and the input end of the switch selection circuit is coupled with the output end of the switch detection circuit; and at least two selection switches, each selection switch having a control terminal, a first terminal and a second terminal, the control terminal of each selection switch being coupled to the plurality of output terminals of the switch selection circuit in a one-to-one correspondence, each configuration pin being coupled to the first terminal of the corresponding selection switch, the second terminal of each selection switch being coupled to the output terminal of the reference setting circuit.

In one embodiment, the load driving circuit further includes an error amplifying circuit and a compensation capacitor, wherein a first input terminal of the error amplifying circuit is coupled to the output terminal of the reference setting circuit, a second input terminal of the error amplifying circuit is coupled to the sampling resistor, and an output terminal of the error amplifying circuit is coupled to the compensation capacitor and the conduction control circuit.

In one embodiment, the reference setting circuit includes: the switch selection circuit is provided with an input end and a plurality of output ends, and the input end of the switch selection circuit is coupled with the output end of the switch detection circuit; the control ends of the first selection switch, the second selection switch and the third selection switch are respectively coupled with the output ends of the switch selection circuit, and the first end of the first selection switch, the first end of the second selection switch and the first end of the third selection switch are coupled with the reference setting circuit; the reference voltage source is coupled with the second end of the first selection switch; a third resistor, having a first terminal coupled to the reference voltage source and a second terminal coupled to the second terminal of the second selection switch and coupled to the first configuration resistor through the first configuration pin; and a fourth resistor having a first end coupled to the reference voltage source and a second end coupled to the second end of the third selection switch and to the second configuration resistor via the second configuration pin.

In one embodiment, the reference setting circuit includes: the switch selection circuit is provided with an input end and a plurality of output ends, and the input end of the switch selection circuit is coupled with the output end of the switch detection circuit; the reference current source is coupled with the output end of the reference setting circuit; the control ends of the first selection switch, the second selection switch and the third selection switch are respectively coupled with a plurality of output end reference current sources of the switch selection circuit, the first end of the first selection switch, the first end of the second selection switch and the first end of the third selection switch are coupled with the reference current sources, the second end of the first selection switch is coupled with the first configuration resistor through the first configuration pin, the second end of the second selection switch is coupled with the second configuration resistor through the second configuration pin, and the second end of the third selection switch is coupled with the built-in resistor or the third configuration resistor through the third configuration pin.

The conduction control circuit includes: a frequency modulation circuit that generates a first adjustment signal based on a current reference; an amplitude modulation circuit that generates a second adjustment signal based on a current reference; a trigger circuit having two input terminals and an output terminal, the two input terminals receiving a first adjustment signal and a second adjustment signal, respectively; and an operational amplifier circuit, the input end of which is coupled to the output end of the trigger circuit, and the output end of which is coupled to the control end of the power transistor.

According to another aspect of the present invention, a lighting driving system with power switch dimming function comprises a rectifying circuit, a load driving circuit as described in any of the above embodiments, and an L ED lamp, wherein the load driving circuit comprises a power transistor, and the rectifying circuit is coupled between the power switch and the load driving circuit.

In one embodiment, the load driving circuit further comprises a diode having an anode coupled to the first terminal of the power transistor and a cathode coupled to the output terminal of the rectifying circuit and the anode of the L ED lamp, and an inductor having a first terminal coupled to the first terminal of the power transistor and a second terminal coupled to the cathode of the L ED lamp.

The utility model provides a load drive circuit and lighting drive system have realized many grades of output current to through the setting to external configuration part, realize that many grades of electric currents are nimble adjustable, can be suitable for different occasions, also can make the adjustting of lighteness order be suitable for different use custom.

Drawings

Fig. 1 is a schematic diagram of a circuit for adjusting the brightness of a lamp by a wall switch in the prior art.

Fig. 2 is a circuit diagram of a lamp brightness adjusting system in the prior art.

Fig. 3 is a circuit diagram of a lamp brightness adjustment control circuit in the prior art.

Fig. 4 is a schematic diagram showing the relationship between OCP, Toff _ min, switch and VDD in the conventional lamp brightness adjustment design.

Fig. 5 is a schematic diagram of a system architecture of a load driving system according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a system architecture of a load driving system according to another embodiment of the present invention.

Fig. 7 is a schematic circuit diagram of a load driving system according to an embodiment of the present invention.

Fig. 8 is a schematic circuit diagram of a reference setting circuit according to an embodiment of the present invention.

Fig. 9 is another schematic circuit diagram of the reference setting circuit according to an embodiment of the present invention.

Fig. 10 is a flowchart illustrating a step of detecting whether the switching operation of the power switch satisfies the predetermined condition according to an embodiment of the present invention.

Fig. 11 is a schematic diagram of an adjusting effect of the load driving system according to an embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

For further understanding of the present invention, preferred embodiments of the present invention will be described below with reference to examples, but it should be understood that these descriptions are only for the purpose of further illustrating the features and advantages of the present invention, and are not intended to limit the claims of the present invention.

The description in this section is for exemplary embodiments only, and the present invention is not limited to the scope of the embodiments described. The same or similar technical means as those of the embodiments may be substituted for the technical features of the embodiments described and claimed.

The "plurality" in the specification means two or more; "Multi-gear" means two or more gears. "coupled" or "connected" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.

In one embodiment, the load driving circuit includes a power switch S coupled to the power switch S through a rectifying circuit 52, wherein the power switch S is configured to control connection and disconnection of the power supply to the load driving circuit, in one embodiment, the power switch S is a wall switch disposed on a wall, which facilitates operation of the power switch S for controlling connection and disconnection of the load driving circuit to and from a mains ac power supply, the wall switch does not increase system cost, compatibility is good, efficiency is not lost, the load driving circuit may detect switching of the power switch S and further determine whether switching of the power switch S meets predetermined conditions, the load driving circuit has at least one configuration pin (CS2 and CS 48) each for coupling corresponding configuration elements (R1 and R2) to the power switch S, in one embodiment, the configuration element is a power switch CS, c.

In the embodiment shown in fig. 5, the load 53 comprises L ED lights, and the load driving system shown is a lighting driving system with mains switched dimming functionality.

In the embodiment shown in fig. 5, the load driving circuit may further include a rectifying circuit 52, a diode D, and an inductor L in addition to the driving control circuit 54, wherein the anode of the diode D is coupled to the first terminal of the power transistor K, the cathode is coupled to the output terminal of the rectifying circuit 52, and the anode of the L ED lamp, the first terminal of the inductor L is coupled to the first terminal of the power transistor K, and the second terminal is coupled to the cathode of the L ED lamp, wherein the driving control circuit 54 may be a semiconductor chip, or an electronic package.

Fig. 6 shows a schematic view of a load driving system according to another embodiment of the present invention. The load driving system includes a linear driving circuit. The power transistor K in the load driving system is directly coupled to the load 53, wherein the power transistor K is a linear device and can operate in a resistance variable region.

The load driving system of the embodiment shown in fig. 5 and 6 further includes a rectifying circuit 52 coupled between the switching power supply Q and the load driving circuit, for rectifying the commercial power ac into a bus voltage of a steamed bun waveform, and forming a dc signal through filtering of the input capacitor.

In one embodiment, the

drive control circuit

54 or 64 shown in fig. 5 or 6 is provided on a semiconductor wafer, and the

drive control circuit

54 or 64 includes the switch detection circuit 31, the reference setting circuit 32, and the conduction control circuit 34 shown in fig. 7. The semiconductor wafer may be further provided with a power transistor K and an error amplifying circuit 33 as shown in fig. 7.

Fig. 7 shows a schematic diagram of a load driving system according to an embodiment of the present invention. Wherein the load driving circuit 3 has a current feedback pin CS and two configuration pins C and D for coupling externally with a sampling resistor Rcs and configuration resistors R1 and R2, respectively. The corresponding gear current value is adjusted by configuring the resistance value of the resistor R1 or R2. Of course, the load driving circuit 3 may have only one configuration pin at least for realizing the two-gear output current. The load drive circuit 3 includes a switch detection circuit 31, a reference setting circuit 32, an error amplification circuit 33, and a conduction control circuit 34. In one embodiment, the error amplification circuit 33 may not be employed. The switch detection circuit 31 is configured to detect a switching action of the power switch S and provide a power switch signal a indicating whether the switching action of the power switch S meets a predetermined condition, for example, when the switching action of the power switch S is determined to meet the predetermined condition, the power switch signal a is in an active state, such as presenting a high level pulse. In one embodiment, when the off duration of the power switch S meets a preset duration, if the off duration is greater than the first time threshold and less than the second time threshold, the power switch signal a in an active state is output for switching the configuration pin coupled to the reference setting circuit. For example, fig. 10 is a flowchart of a step of detecting whether a switching operation of the power switch meets a predetermined condition according to an embodiment of the present invention: if the voltage of the current sampling signal Vcs is less than 100mv for 10ms to 7s, the power switch signal a is switched from an invalid value to an valid value, and the switch selection circuits in the reference setting circuit sequentially switch the switch selection signals O, P, Q to be in an valid state to sequentially turn on the corresponding selection switches. The switching is performed once every time the switching action of the power switch meeting the preset condition is detected. Of course, the switching action of the power switch meeting the predetermined condition may also be in other forms, such as two off-on actions.

The reference setting circuit 32 is coupled to the switch detection circuit 31, and the reference setting circuit 31 selectively couples the reference setting circuit 32 to a configuration pin (C or D) based on the power switch signal a, and sets the current reference B based on at least a parameter on the configuration pin to which it is coupled. In the illustrated embodiment, the current reference B is set by detecting a resistance value on the configuration pin. In one embodiment, the reference setting circuit comprises at least two selection switches, wherein each configuration pin is coupled with one selection switch, when the switching action of the power switch S meets a predetermined condition, the selection switches are switched on, and the configuration pins are switched, so that the parameter is changed, the current reference is changed correspondingly, and the current gear shifting is realized. The number of the selection switches can be equal to or larger than the number of the configuration pins. In one embodiment, the number of selection switches is greater than the number of configuration pins, and the load driving circuit sets the multi-level current based on parameters on the configuration pins and internal parameters.

Fig. 8 shows a circuit schematic diagram of a reference setting circuit according to an embodiment of the present invention. The reference setting circuit comprises a plurality of selection switches, and the selection switches are sequentially switched on based on the state of the switching power supply signal A to change parameters accessed into the reference setting circuit and realize current gear shifting. The reference setting circuit includes a switch selection circuit 321, a first selection switch K1, a second selection switch K2, a third selection switch K3, a reference voltage source V1, and resistors R3 and R4. The reference setting circuit is coupled to the outside and configuration resistors R1 and R2 through configuration pins C and D, respectively. The switch selection circuit 321 is coupled to the state detection circuit 31 for receiving the power switch signal a. The switch selection circuit 321 generates a plurality of switch selection signals O, P and Q based on the power supply switch signal a. In one embodiment, the switch select signals O, P and Q are sequentially asserted in response to the power switch signal a for rendering the corresponding select switch conductive. When the power switch signal a is in an active state each time, the switch selection signal in the active state is switched once according to a preset sequence, for example, the states of the switch selection signal O, P and Q are switched from 100 to 010, and then to 001, where 0 represents turning off the corresponding selection switch, and 1 represents turning on the corresponding selection switch. The control terminals of the first selection switch K1, the second selection switch K2 and the third selection switch K3 are controlled by switch selection signals O, P and Q respectively, so as to sequentially switch on the selection switches according to a set sequence. When the switch selection signal O, P and the Q state are switched from 100 to 010, going to 001 indicates that the first selection switch K1 is turned on, the second selection switch K2 is turned on, and the third selection switch K3 is turned on. A first terminal of the first selection switch K1, a first terminal of the second selection switch K2, and a first terminal of the third selection switch K3 are coupled to the output terminal of the reference setting circuit 32 for providing the current reference B. The second terminal of the first selection switch K1 is coupled to a reference voltage source V1. The second terminal of the second selection switch K2 is coupled to the resistor R3 and coupled to the first configuration resistor R1 through the first configuration pin C, wherein the other terminal of the third resistor R3 is coupled to the reference voltage source V1. The second terminal of the third selection switch K3 is coupled to the fourth resistor R4 and to the second configuration resistor R2 through the second configuration pin D, wherein the other terminal of the fourth resistor R4 is coupled to the reference voltage source V1. When the switch selection signal O, P and the Q state are switched from 100 to 010 and then to 001, the voltage source is switched from the terminal B to the terminal C to the terminal B, and then to the terminal D to the terminal B, the reference current signal B is respectively switched from V1 to R1/(R1+ R3) × V1 and then to R2/(R2+ R4) × V1, which are respectively proportional to the current values of the three-level output currents. The current value of the second gear current can be adjusted by adjusting the resistance value of the configuration resistor R1, and the current value of the third gear current can be adjusted by adjusting the resistance value of the configuration resistor R2. With the reference setting circuit shown in fig. 8, when the resistance values of the configuration resistors R1 and R2 are the same, only two stages of current output can be realized. If R1/(R1+ R3) > R2/(R2+ R4), the current intensity is high, medium, and weak when the selection switches K1, K2, and K3 are sequentially switched. If R1/(R1+ R3) < R2/(R2+ R4), the current intensity is high, weak, and medium when the selection switches K1, K2, and K3 are sequentially switched.

Fig. 9 shows a circuit schematic of a reference setting circuit according to another embodiment of the present invention. The reference setting circuit includes a switch selection circuit 321, a first selection switch K1, a second selection switch K2, a third selection switch K3, a reference current source I1, a reference voltage source V1, and a calculation unit 322. The switch selection circuit 321 is coupled to the state detection circuit 31, and the switch selection circuit 321 generates a plurality of switch selection signals O, P, Q based on the power switch signal a. When the power switch signal a is in an active state for each time, the active value in the switch selection signal O, P, Q is sequentially switched once, for example, the power switch signal a sequentially appears three active states (three high level pulses appear), the switch selection signals O, P and Q state can be respectively switched from 100 to 010, from 010 to 001, and from 001 to 100, so that the reference setting circuit is respectively coupled to the configuration pin C, switched to be coupled to the configuration pin D, switched to be coupled to the terminal E, and switched to be coupled to the terminal C, and the current source I1 charges the resistors R5, R6, R7, and R5 to generate corresponding voltage signals for further generating the current reference B. . The terminal E may be a configuration pin for coupling with the external configuration resistor R7, or may not be a configuration pin for coupling with the internal resistor R7. The computing unit 322 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of the computing unit 322 is coupled to the reference voltage source V1, the second input terminal of the computing unit 322 is coupled to the reference current source I1, and the output terminal of the computing unit 322 is used for providing the current reference B. The control terminals of the first selection switch K1, the second selection switch K2 and the third selection switch K3 are respectively controlled by a switch selection signal O, P, Q to sequentially switch on the selection switches according to a set sequence. A first terminal of the first selection switch K1, a first terminal of the second selection switch K2, and a first terminal of the third selection switch K3 are coupled to the reference current source I1, and a second terminal of the first selection switch K1, a second terminal of the second selection switch K2, and a second terminal of the third selection switch K3 are coupled to three configuration resistors R5, R6, and R7 through three configuration pins C, D, E, respectively. When the switch select signal O, P and the Q state can be switched from 100 to 010 to 001, respectively, the current references are set to K0R 5, K0R 6, and K0R 7, respectively, where K0 is a constant associated with current source I1 and voltage source V1. The first current value can be adjusted by adjusting the resistance of R5, the second current value can be adjusted by adjusting the resistance of R6, and the third current value can be adjusted by adjusting the resistance of R7. By adjusting the resistance values of R5, R6 and R7, the magnitude relation of the three-gear current values can be adjusted at will, and current references in any sequence, such as strong-medium-weak, weak-medium-strong, medium-strong-weak and the like, can be realized during sequential switching. Therefore, the embodiment is not limited to the switching of the fixed current reference which can only be from large to small in the prior art, and the switching of the current reference from small to large can also be realized by the configuration of the external resistor. Even when the resistances of the configuration resistors R5 and R6 are set to be the same, the system can achieve two-stage current output. When the resistance values of the configuration resistors R5, R6, and R7 are set to be the same, the system can achieve first-gear current output. In addition, the current value of each level of current can be adjusted in the same proportion by adjusting the resistance value of the sampling resistor.

When the load driving circuit has at least two configuration pins and the mutual positions of the plurality of configuration components are correspondingly exchanged, the output sequence of the corresponding stage current is correspondingly changed, for example, when the configuration pin C is coupled to R5, the pin D is coupled to R6, and the pin E is coupled to R7, when the power switch sequentially performs the switching actions meeting the predetermined conditions, the output current sequentially outputs three-stage current values I1, I2, and I3 and continues to circulate, when the configuration pin C is coupled to R7, the pin D is coupled to R5, and the pin E is coupled to R6, when the power switch sequentially performs the switching actions meeting the predetermined conditions, the output current sequentially outputs three-stage current values I3, I1, and I2 and continues to circulate.

In another embodiment, the load driving circuit including the reference setting circuit shown in fig. 9 has two configuration pins C and D for implementing three-level current adjustment, where R7 is an on-chip resistor, R5 and R6 are off-chip resistors, and the magnitude relationship of the currents in each level can be adjusted by adjusting R5 and R6. When the positions of R5 and R6 are exchanged, the sequence of the corresponding stage currents is changed accordingly, for example, when the original configuration pin C is coupled to R5 and the pin D is coupled to R6, the output currents sequentially show three stage current values I1, I2, and I3 when the power switch sequentially performs the switching operation meeting the predetermined condition, and when the configuration pin C is coupled to R6 and the pin D is coupled to R5, the output currents sequentially show three stage current values I2, I1, and I3 when the power switch sequentially performs the switching operation meeting the predetermined condition.

In another embodiment of the present invention, the reference setting circuit may not include the reference voltage source V1 and the calculating unit, and the current reference is provided directly by the coupling terminal of the current source I1 and the selection switch.

The embodiments shown in fig. 8 and 9 realize three-gear output current and regulation. In other embodiments, two-stage output current and regulation can be achieved by providing a configuration pin and two selection switches for the reference setting circuit shown in fig. 8 or fig. 9. By providing three or more configuration pins to the reference setting circuit shown in fig. 8, output current and regulation functions of more stages can be realized. By providing the reference setting circuit shown in fig. 9 with two configuration pins and two selection switches, two-stage output current and regulation can be realized. By providing four or more configuration pins to the reference setting circuit shown in fig. 9, output current and regulation functions of more stages and the like can be realized.

Continuing with the description of fig. 7, the error amplifying circuit 33 includes an error amplifying circuit 331 and a compensation capacitor Comp, wherein a first input terminal of the error amplifying circuit 331 is coupled to the output terminal of the reference setting circuit 32, a second input terminal of the error amplifying circuit 331 is coupled to the sampling resistor Rcs for receiving a current sampling signal representing the output current, and an output terminal of the error amplifying circuit 331 is coupled to the compensation capacitor Comp and the conduction control circuit 34. The error amplification circuit 33 error-amplifies the difference between the current sampling signal and the current reference B so that the average value of the output current follows the current reference B. The current value of each gear can be adjusted in the same proportion by adjusting the resistance value of the sampling resistor Rcs. When the reference setting circuit shown in fig. 8 is used, the sampling resistor Rcs determines the maximum output current among the multi-stage currents. When the reference setting circuit as shown in fig. 9 is employed, the base output current can be adjusted by adjusting the sampling resistance Rcs.

In another embodiment, the load drive system does not include an error amplification circuit, and the conduction control circuit 34 performs open-loop control of the current based directly on the current reference B.

From the description of the above embodiments, it can be known that the setting of the current level with any size relationship can be conveniently realized by setting the external resistor including the sampling resistor Rcs and the plurality of configuration resistors R5, R6 and R7, and various design requirements can be flexibly met.

The conduction control circuit 34 controls the power transistor K based on a current reference B. in the embodiment shown in FIG. 7, the conduction control circuit 34 includes a frequency modulation circuit (FM)341, an amplitude modulation circuit (AM)342, a trigger circuit 343, and an operational amplifier circuit 344. in the embodiment shown in FIG. 7, the frequency modulation circuit 341 generates a first adjustment signal based on the current reference B. the frequency modulation circuit 341 may be any circuit that can adjust the frequency of the power transistor K. in the illustrated embodiment, the frequency modulation circuit 341 generates a first adjustment signal based on an error amplification signal of the current reference B and the current sampling signal and a zero current detection signal ZCD of an inductor L. when the current reference B rises, the system frequency may be lowered. when the ZCD signal is active, the frequency modulation circuit 341 outputs an effective value for setting the trigger circuit 343, the power transistor K is turned on, the amplitude modulation circuit 342 generates a second adjustment signal based on the current reference B. in one embodiment, when the sawtooth signal rises to either the reference signal or the error amplification signal of the error amplification circuit, the amplitude modulation circuit 342 outputs an effective value for resetting the trigger circuit 343, turning off the power transistor K. the trigger circuit has two inputs and one input terminals for receiving the two adjustment signals, the respective reset signal, the operational amplifier circuit outputs a reset signal, the reset signal output terminal 344, the reset signal is coupled to the trigger signal output terminal 344, the trigger circuit 344, the trigger signal output terminal is coupled to the trigger circuit 344, the trigger circuit 344.

The conduction control circuit can have any other applicable structure and is controlled by adopting any applicable control mode, so that the output current follows the current reference.

In one embodiment, the switch detection circuit 31, the reference setting circuit 32, and the conduction control circuit 34 are disposed inside a semiconductor wafer, and the sampling resistor Rcs and configuration components such as the configuration resistors R1, R2 (or R5, R6) are disposed outside the semiconductor wafer.

In addition to configuring the resistance through the configuration pin, the capacitance or current may also be configured through the configuration pin, with the current reference being adjusted by configuring parameters of configuration components coupled to the reference setting circuit.

As can be seen from the above embodiments, the magnitude relationship of the multi-step current can be adjusted by adjusting the external parameters on each configuration pin. In this way, each lighting manufacturer can freely set the proportion of the output current by selecting the first resistor R1 and the second resistor R2 (or the fifth resistor R5 and the sixth resistor R6) conveniently, rather than being fixedly set by the control chip. For example, the luminances may be set to 60%, 80%, and 100%, respectively, for the luminance adjustment in a working environment, or to 10%, 70%, and 100%, respectively, for the use as a night light, reading, and working, and other different functions. The designer can easily realize the expansion of various functions of the lighting device only by the selection and the arrangement of the external resistor.

Fig. 11 shows a relationship between the magnitude of the multi-step current according to an embodiment of the present invention. By adjusting parameters of configuration components, such as setting the resistance values of the resistors R5, R6 and R7 as R5< R6< R7 current reference as shown in the embodiment of fig. 9, the three-gear current can be adjusted from small to large, and the brightness gradually becomes brighter, setting the resistance values of the resistors R5, R6 and R7 as R5> R6> R7, or correspondingly exchanging the positions of the original resistors R5 and R7, the three-gear current can be adjusted from large to small, and the brightness becomes darker from bright.

In one embodiment, the switch detection circuit 31 is coupled to the sampling resistor Rcs for obtaining the current sampling signal, and provides the power switch signal a based on the current sampling signal.

Fig. 10 shows a flowchart for providing a power switch signal a for detecting whether a power switch in a load driving circuit meets a predetermined condition according to an embodiment of the present invention. The detection step comprises: when the power switch S is turned off for shutdown, the current sampling signal Vcs falls. Detecting a current sampling signal Vcs, and when the state that the detected Vcs is less than a preset value such as 100mv exceeds a first set time such as 10ms, starting timing to indicate that a power switch is in an off action, and timing the state. If the interval from the turning-off to the turning-on of the power switch S exceeds a second set time, such as 7 seconds, the system current reference is reset to the initial value. If the interval from off to on is greater than the first set time (e.g. 10ms) but less than the second set time (e.g. 7S), the system determines that the current reference needs to be changed, i.e. the switching action of the power switch S meets the predetermined condition, and the switch detection circuit outputs an effective power switch signal a, such as a high level pulse, for switching on the selection switch to change the current reference.

In other embodiments, the switch detection circuit 31 may detect the operation of the power switch S by detecting parameters of other types or other locations. For example, the voltage at the output end of the rectifying circuit is detected to measure the switching action, and further, the switching action is used for judging whether the switching action of the power switch S meets the preset condition.

As can be seen from the above description, the load driving circuit, the lighting driving system with the power switch dimming function, and the driving method provided in the embodiments of the present invention can realize the multi-gear arbitrary adjustment of the output current by selecting the external configuration component. The switching effect from weak to strong or from strong to weak can be realized for multi-gear output current, and two-gear or one-gear output can also be realized on a three-gear current load driving circuit.

The description and applications of the present invention are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the present invention.

Claims

1. A load driving circuit, wherein a power switch is coupled between the load driving circuit and a power source, the load driving circuit having a current feedback pin and at least one configuration pin, wherein the current feedback pin is coupled to a sampling resistor, and each configuration pin is coupled to a configuration component, the load driving circuit comprising:

the switch detection circuit is provided with an input end and an output end, and the output end of the switch detection circuit provides a power switch signal for representing whether the switching action of the power switch meets the preset condition;

a reference setting circuit having an input and an output, wherein the input of the reference setting circuit is coupled to the switch detection circuit, the reference setting circuit is selectively coupled to the configuration component, and the output of the reference setting circuit provides a current reference; and

and the conduction control circuit is provided with an input end and an output end, the input end of the conduction control circuit is coupled with the reference setting circuit, and the output end of the conduction control circuit is coupled with the control end of the power transistor.

2. The load driving circuit according to claim 1, wherein the switch detection circuit, the reference setting circuit and the conduction control circuit are provided in a semiconductor wafer, and the sampling resistor and the configuration part are provided outside the semiconductor wafer.

3. The load driving circuit according to claim 1, wherein the input terminal of the switch detection circuit is coupled to the sampling resistor.

4. The load driving circuit according to claim 1, wherein the reference setting circuit comprises:

the switch selection circuit is provided with an input end and a plurality of output ends, and the input end of the switch selection circuit is coupled with the output end of the switch detection circuit; and

the control end of each selector switch is coupled with a plurality of output ends of the switch selection circuit in a one-to-one correspondence mode, each configuration pin is coupled with the first end of the corresponding selector switch, and the second end of each selector switch is coupled with the output end of the reference setting circuit.

5. The load driving circuit according to claim 1, further comprising an error amplifying circuit and a compensation capacitor, wherein a first input terminal of the error amplifying circuit is coupled to the output terminal of the reference setting circuit, a second input terminal of the error amplifying circuit is coupled to the sampling resistor, and an output terminal of the error amplifying circuit is coupled to the compensation capacitor and the conduction control circuit.

6. The load driving circuit according to claim 1, wherein the reference setting circuit comprises:

the switch selection circuit is provided with an input end and a plurality of output ends, and the input end of the switch selection circuit is coupled with the output end of the switch detection circuit;

the control ends of the first selection switch, the second selection switch and the third selection switch are respectively coupled with the output ends of the switch selection circuit, and the first end of the first selection switch, the first end of the second selection switch and the first end of the third selection switch are coupled with the reference setting circuit;

the reference voltage source is coupled with the second end of the first selection switch;

a third resistor, having a first terminal coupled to the reference voltage source and a second terminal coupled to the second terminal of the second selection switch and coupled to the first configuration resistor through the first configuration pin; and

a fourth resistor, a first terminal of which is coupled to the reference voltage source, a second terminal of which is coupled to the second terminal of the third selection switch and to the second configuration resistor through the second configuration pin.

7. The load driving circuit according to claim 1, wherein the reference setting circuit comprises:

the reference current source is coupled with the output end of the reference setting circuit;

the control ends of the first selection switch, the second selection switch and the third selection switch are respectively coupled with a plurality of output end reference current sources of the switch selection circuit, the first end of the first selection switch, the first end of the second selection switch and the first end of the third selection switch are coupled with the reference current sources, the second end of the first selection switch is coupled with the first configuration resistor through the first configuration pin, the second end of the second selection switch is coupled with the second configuration resistor through the second configuration pin, and the second end of the third selection switch is coupled with the built-in resistor or the third configuration resistor through the third configuration pin.

8. The load driving circuit of claim 1, wherein the conduction control circuit comprises:

a frequency modulation circuit that generates a first adjustment signal based on a current reference;

an amplitude modulation circuit that generates a second adjustment signal based on a current reference;

a trigger circuit having two input terminals and an output terminal, the two input terminals receiving a first adjustment signal and a second adjustment signal, respectively; and

and the input end of the operational amplifier circuit is coupled with the output end of the trigger circuit, and the output end of the operational amplifier circuit is coupled with the control end of the power transistor.

9. A lighting driving system with power switch regulation function, comprising a rectifying circuit, a load driving circuit as claimed in any one of claims 1 to 8 and an L ED lamp, wherein the load driving circuit comprises a power transistor, and the rectifying circuit is coupled between the power switch and the load driving circuit.

10. The lighting driving system according to claim 9, wherein the load driving circuit further comprises:

a diode having an anode coupled to the first terminal of the power transistor and a cathode coupled to the output terminal of the rectifying circuit and the anode of the L ED lamp;

and an inductor having a first terminal coupled to the first terminal of the power transistor and a second terminal coupled to L cathode of the ED lamp.