CN211183824U - Synchronous rectification control circuit and isolated power supply conversion circuit - Google Patents
Synchronous rectification control circuit and isolated power supply conversion circuit Download PDFInfo
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- CN211183824U CN211183824U CN201922234924.9U CN201922234924U CN211183824U CN 211183824 U CN211183824 U CN 211183824U CN 201922234924 U CN201922234924 U CN 201922234924U CN 211183824 U CN211183824 U CN 211183824U
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Abstract
The utility model discloses a synchronous rectification control circuit and an isolated power conversion circuit, wherein the synchronous rectification control circuit can be coupled with a synchronous rectification transistor and can send a control signal to the synchronous rectification transistor; the synchronous rectification control circuit includes: the circuit comprises a comparison circuit, a drive circuit, a signal regulating circuit and a conduction voltage drop regulating circuit. The input end of the comparison circuit is respectively coupled with the synchronous rectification transistor and at least one reference signal, and the output end of the comparison circuit is respectively coupled with the driving circuit and the signal regulating circuit; the output end of the driving circuit is coupled with the synchronous rectification transistor and used for sending a control signal to the synchronous rectification transistor according to a signal output by the comparison circuit; the input end of the signal adjusting circuit is coupled with the comparison circuit, and the output end of the signal adjusting circuit is coupled with the conduction voltage drop adjusting circuit and used for adjusting a set reference signal in at least one reference signal according to a signal output by the comparison circuit. The utility model discloses can realize the accurate shutoff to synchronous rectifier transistor, can improve turn-off speed simultaneously, promote the reliability of circuit.
Description
Technical Field
The utility model belongs to the technical field of the electronic circuit, a control circuit is related to, especially, relate to a synchronous rectification control circuit and isolated power supply converting circuit.
Background
Synchronous Rectification (SR) is a technology that uses Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) to replace a rectifier diode to reduce Rectification loss, and is widely used in the fields of industrial power supplies, consumer electronics, and the like. Fig. 1 is a Flyback architecture diagram using a diode for secondary side rectification, and fig. 2 is a Flyback architecture diagram using SR for secondary side rectification. The synchronous rectification MOSFET with extremely low on-state resistance is adopted to replace a rectification diode, so that the rectification loss can be reduced.
The SR MOSFET turn-off design is the key and difficult point of the SR control technology; there are two methods of SR shutdown in the industry, which are a prejudged method and a voltage detection shutdown method.
FIG. 3 is a waveform diagram illustrating a conventional pre-determined SR shutdown method; referring to fig. 3, the pre-determined SR shutdown method obtains the shutdown point of the SR MOSFET by a prediction method, and has a disadvantage that the dynamic process may be common, that is, the primary power switch tube and the secondary rectifier tube may have a common state, so that the flyback circuit operates abnormally and has low reliability.
FIG. 4 is a waveform diagram illustrating a conventional SR shutdown method using voltage detection; referring to fig. 4, the voltage detection turn-off method turns off the MOSFET by detecting the voltage across the MOSFET and when the voltage Vds between the drain and the source reaches a certain threshold Vth _ off, the disadvantage is that CCM cannot be compatible and the efficiency is low.
In view of the above, there is an urgent need to design a new synchronous rectification control method to overcome the above-mentioned drawbacks of the existing synchronous rectification control method.
SUMMERY OF THE UTILITY MODEL
The utility model provides a synchronous rectification control circuit and isolated power supply converting circuit can realize the accurate shutoff to synchronous rectifier transistor, improves the circuit reliability.
For solving the technical problem, according to the utility model discloses an aspect adopts following technical scheme:
a synchronous rectification control circuit can be coupled with a synchronous rectification transistor and can send a control signal to the synchronous rectification transistor; the synchronous rectification control circuit comprises:
the input end of the comparison circuit is respectively coupled with the synchronous rectification transistor and at least one reference signal, and the output end of the comparison circuit is respectively coupled with the driving circuit and the signal regulating circuit;
the output end of the driving circuit is coupled with the synchronous rectifying transistor and used for sending a control signal to the synchronous rectifying transistor according to the signal output by the comparison circuit;
the input end of the signal regulating circuit is coupled with the comparison circuit, and the output end of the signal regulating circuit is coupled with the conduction voltage drop regulating circuit and used for regulating a set reference signal in at least one reference signal according to a signal output by the comparison circuit; and
and the input end of the conduction voltage drop regulating circuit is coupled with the set reference signal, and the output end of the conduction voltage drop regulating circuit is coupled with the synchronous rectifying transistor and used for regulating the control end voltage of the synchronous rectifying transistor.
As an embodiment of the present invention, the signal adjusting circuit is configured to adjust the setting reference signal according to the signal output by the comparing circuit, and does not adjust other reference signals. In another embodiment, the signal conditioning circuit of the present invention is configured to adjust the set reference signal and the other reference signals according to the signal output by the comparison circuit.
As an embodiment of the present invention, the conduction voltage drop adjustment circuit includes a transconductance operational amplifier, a first input terminal and a second input terminal of which are coupled to the drain of the synchronous rectification transistor and the second reference signal respectively, an output terminal of which is coupled to the control terminal of the synchronous rectification transistor, and the second reference signal is the setting reference signal.
As an embodiment of the present invention, the driving circuit includes a trigger, the set terminal of the trigger is coupled to the first output terminal of the comparing circuit, the reset terminal of the trigger is coupled to the second output terminal of the comparing circuit, and the output terminal of the trigger is coupled to the control terminal of the synchronous rectification transistor.
As an embodiment of the present invention, the driving circuit includes a trigger; the comparison circuit comprises a first comparator and a second comparator; the input end of the first comparator is respectively coupled with the first reference signal and the drain electrode of the synchronous rectification transistor; the input end of the second comparator is respectively coupled with the drain electrode of the synchronous rectification transistor and a third reference signal; the output end of the first comparator is coupled with the position end of the trigger; the output end of the second comparator is coupled with the reset end of the trigger, and the output end of the trigger is coupled with the control end of the synchronous rectification transistor.
As an embodiment of the present invention, the conduction voltage drop adjustment circuit includes a transconductance operational amplifier and a transconductance operational amplifier control unit, the input end of the transconductance operational amplifier control unit is coupled to the output end of the third comparator and the output end of the RS flip-flop respectively, and the output end of the transconductance operational amplifier control unit is coupled to the enable end of the transconductance operational amplifier.
As an embodiment of the present invention, after the pulse width modulation signal PWM effectively continues the setting time and the voltage Vds between the drain and the source of the synchronous rectification transistor > the second reference signal, the transconductance operational amplifier control unit outputs the control signal to control the operation of the transconductance operational amplifier, so that the transconductance operational amplifier adjusts the driving voltage of the synchronous rectification transistor.
As an embodiment of the present invention, the synchronous rectification control circuit includes a high-voltage starting module, the input of the high-voltage starting module is coupled to the drain of the synchronous rectification transistor, and the output of the high-voltage starting module is coupled to the power supply pin of the synchronous rectification control circuit.
As an embodiment of the present invention, the at least one reference signal coupled to the input terminal of the comparison circuit includes a first reference signal, a second reference signal, and a third reference signal; the setting reference signal is a second reference signal.
As an embodiment of the present invention, the comparison circuit is used to compare the magnitude of the voltage Vds between the drain and the source of the synchronous rectification transistor and the first reference signal, the second reference signal, and the third reference signal, and outputs the corresponding output signal to the driving circuit, the signal conditioning circuit, and the conduction voltage drop conditioning circuit.
As an embodiment of the present invention, the comparison circuit includes a first comparator, a second comparator and a third comparator; the positive phase input end of the first comparator is coupled with a first reference signal, and the negative phase input end of the first comparator is coupled with the drain electrode of the synchronous rectification transistor; the positive phase input end of the second comparator is coupled with the drain electrode of the synchronous rectification transistor, and the negative phase input end of the second comparator is coupled with the third reference signal; the positive phase input end of the third comparator is coupled with the drain electrode of the synchronous rectification transistor, and the negative phase input end of the third comparator is coupled with the second reference signal.
As an embodiment of the present invention, the input terminal of the signal adjusting circuit is coupled to the output terminal of the third comparator and the output terminal of the second comparator respectively, so as to obtain the output signals of the second comparator and the third comparator, and adjust the value of the second reference signal.
As an embodiment of the present invention, the adjustment period of the second reference signal corresponds to the synchronous rectification period of the synchronous rectification transistor.
As an embodiment of the present invention, the driving circuit controls the synchronous rectification transistor to be completely turned on when Vds of the synchronous rectification transistor is smaller than the first reference signal;
the driving circuit controls the synchronous rectification transistor to be turned off when the voltage Vds between the drain and the source of the synchronous rectification transistor is greater than a third reference signal; wherein the first reference signal is less than the third reference signal.
As an embodiment of the present invention, after the PWM signal is PWM for the effective duration setting time and the voltage Vds between the drain and the source of the synchronous rectification transistor > the second reference signal is satisfied simultaneously, the conduction voltage drop adjusting circuit controls the voltage Vgs between the gate and the source of the synchronous rectification transistor to be lowered when the voltage Vds is greater than the second reference signal;
and the conduction voltage drop regulating circuit controls the voltage Vgs between the grid electrode and the source electrode of the synchronous rectification transistor to rise when the voltage Vds is smaller than a second reference signal.
As an embodiment of the present invention, the method for adjusting the setting reference signal by the signal conditioning circuit includes: if the time difference Δ T from when Vds begins to be greater than the second reference signal to when Vds is greater than the third reference signal within the period is greater than the set time difference threshold T0, increasing the value of the second reference signal; if the time difference Δ T from when the voltage Vds begins to be greater than the second reference signal to when Vds is greater than the third reference signal within the period is less than the set time difference threshold T0, the value of the second reference signal is decreased.
The utility model also discloses an isolated power supply converting circuit, isolated power supply converting circuit include primary circuit and secondary circuit, and input voltage is received to the primary circuit, and the primary circuit includes primary winding and former limit switch. The secondary circuit comprises a secondary winding and the synchronous rectification control circuit, and the secondary winding and the primary winding are coupled to form a transformer.
The beneficial effects of the utility model reside in that: the utility model provides a synchronous rectification control circuit and isolated power supply converting circuit can realize the accurate shutoff to synchronous rectifier transistor (like SR MOSFET), can improve turn-off speed simultaneously to the synchronous rectifier transistor (like SR MOSFET) of the different internal resistances of adaptation. The utility model discloses can compatible CCM, efficient, and can avoid former vice limit to be in common, promoted the reliability of circuit.
Drawings
Fig. 1 is a schematic diagram of a Flyback architecture using a diode as secondary side rectification.
Fig. 2 is a schematic diagram of a Flyback architecture using SR as secondary side rectification.
Fig. 3 is a waveform diagram illustrating a conventional pre-determined SR shutdown method.
Fig. 4 is a waveform diagram illustrating a conventional SR shutdown method using a voltage detection shutdown method.
Fig. 5 is a schematic circuit diagram of a synchronous rectification control circuit according to an embodiment of the present invention.
Fig. 6 is a schematic circuit diagram of a synchronous rectification control circuit according to an embodiment of the present invention.
Fig. 7 is a flowchart of a synchronous rectification control method according to an embodiment of the present invention.
Fig. 8 is a signal waveform diagram of a synchronous rectification control method according to an embodiment of the present invention.
Fig. 9 is a flowchart of voltage regulation in the synchronous rectification control method according to an embodiment of the present invention.
Fig. 10 is a signal waveform diagram of voltage regulation according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For further understanding of the present invention, preferred embodiments of the present invention will be described below with reference to examples, but it should be understood that these descriptions are only for the purpose of further illustrating the features and advantages of the present invention, and are not intended to limit the claims of the present invention.
The description in this section is for exemplary embodiments only, and the present invention is not limited to the scope of the embodiments described. The same or similar prior art means and some technical features of the embodiments are mutually replaced and are also within the scope of the description and the protection of the invention.
"coupled" or "connected" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives. The transistor in the specification refers to a single element based on a semiconductor material, and includes a triode, a field effect transistor, a thyristor, and the like, which are made of various semiconductor materials.
The utility model discloses a synchronous rectification control circuit, synchronous rectification control circuit can be coupled a synchronous rectification transistor, and can to synchronous rectification transistor sends control signal, controls synchronous rectification transistor work.
Fig. 5 is a schematic circuit diagram of a synchronous rectification control circuit according to an embodiment of the present invention; referring to fig. 5, in an embodiment of the present invention, the synchronous rectification control circuit includes: a comparator circuit 1, a driver circuit 3, and a signal conditioning circuit 5. The input end of the comparison circuit 1 is coupled to the synchronous rectification transistor M1 and at least one reference signal, and the output end of the comparison circuit 1 is coupled to the driving circuit 3 and the signal conditioning circuit 5. The output terminal of the driving circuit 3 is coupled to the synchronous rectification transistor M1 for sending a control signal to the synchronous rectification transistor M1 according to the signal output by the comparing circuit 1. The input end of the signal adjusting circuit 5 is coupled to the comparing circuit 1, and the output end of the signal adjusting circuit 5 is coupled to the conduction voltage drop adjusting circuit and the comparing circuit 1, respectively, for adjusting the set reference signal in at least one reference signal according to the signal output by the comparing circuit 1. In addition, the synchronous rectification control circuit also comprises a conduction voltage drop adjusting circuit, wherein the input end of the conduction voltage drop adjusting circuit is coupled with the set reference signal, and the output end of the conduction voltage drop adjusting circuit is coupled with the synchronous rectification transistor and used for adjusting the control end voltage of the synchronous rectification transistor, so that the current flowing through the synchronous rectification transistor can be controlled. Specifically, a first input terminal of the conduction voltage drop adjustment circuit is coupled to the setting reference signal, a second input terminal of the conduction voltage drop adjustment circuit is coupled to a drain of the synchronous rectification transistor, and an output terminal of the conduction voltage drop adjustment circuit is coupled to a control terminal of the synchronous rectification transistor.
In an embodiment of the present invention, the at least one reference signal coupled to the input terminal of the comparison circuit 1 includes a first reference signal, a second reference signal, and a third reference signal (which may be a first reference voltage-V1, a second reference voltage-V2, and a third reference voltage-V3, respectively); the set reference signal refers to a second reference voltage-V2. In one embodiment of the invention, V1 > V2 > V3 > 0, such that-V1 < -V2 < -V3 < 0.
The comparison circuit is used for comparing the voltage Vds between the drain and the source of the synchronous rectification transistor with the first reference voltage-V1, the second reference voltage-V2 and the third reference voltage-V3, and outputting corresponding output signals to the driving circuit 3 and the signal adjusting circuit 5.
In an embodiment of the present invention, the comparison circuit 1 includes a first comparator U1, a second comparator U2, and a third comparator U3; the non-inverting input terminal of the first comparator U1 is coupled to the first reference voltage-V1, and the inverting input terminal of the first comparator U1 is coupled to the drain of the synchronous rectification transistor M1; the non-inverting input terminal of the second comparator U2 is coupled to the drain of the synchronous rectification transistor M1, and the inverting input terminal of the second comparator U2 is coupled to a third reference voltage-V3; the non-inverting input terminal of the third comparator U3 is coupled to the drain of the synchronous rectification transistor M1, and the inverting input terminal of the third comparator U3 is coupled to the second reference voltage-V2.
The utility model discloses an in the embodiment, drive circuit includes the trigger, the set end of trigger is coupled the first output of comparison circuit, the reset end of trigger is coupled the second output of comparison circuit, the output of trigger is coupled the control end of synchronous rectifier transistor.
In an embodiment of the present invention, the driving circuit includes a flip-flop; the comparison circuit comprises a first comparator and a second comparator. The input end of the first comparator is respectively coupled with the first reference signal and the drain electrode of the synchronous rectification transistor. The input end of the second comparator is respectively coupled with the drain electrode of the synchronous rectification transistor and the third reference signal. The output end of the first comparator is coupled with the position end of the trigger; the output end of the second comparator is coupled with the reset end of the trigger, and the output end of the trigger is coupled with the control end of the synchronous rectification transistor.
In an embodiment of the present invention, the driving circuit 3 includes an RS flip-flop 31 and a driving element 33; the output end of the first comparator U1 is coupled to the set end of the RS flip-flop 31; an output terminal of the second comparator U2 is coupled to a reset terminal of the RS flip-flop 31, an output terminal of the RS flip-flop 31 is coupled to an input terminal of the driving element 33, and an output terminal of the driving element 33 is coupled to a control terminal of the synchronous rectification transistor M1.
In an embodiment of the present invention, the input terminal of the signal adjusting circuit 5 is coupled to the output terminal of the third comparator U3 and the output terminal of the second comparator U2, respectively, for obtaining the output signals of the second comparator U2 and the third comparator U3, so as to adjust the value of the second reference voltage; the adjustment of the second reference voltage by the signal conditioning circuit 5 is performed periodically. The regulation period of the second reference signal corresponds to the synchronous rectification period of the synchronous rectification transistor. For example, the adjusting period of the second reference signal may be equal to the synchronous rectification period, and the adjusting period of the second reference signal may also be an integer multiple of the synchronous rectification period.
Fig. 6 is a schematic circuit diagram of a synchronous rectification control circuit according to an embodiment of the present invention; referring to fig. 6, in an embodiment of the present invention, the synchronous rectification control circuit further includes a conduction voltage drop adjusting circuit 7, an input end of the conduction voltage drop adjusting circuit 7 is coupled to a drain of the synchronous rectification transistor M1 and a second reference signal (a second reference voltage-V2), and an output end of the conduction voltage drop adjusting circuit 7 is coupled to a control end of the synchronous rectification transistor M1 for adjusting a control end voltage of the synchronous rectification transistor, so as to control a current flowing through the synchronous rectification transistor M1. When the synchronous rectification transistor M1 is in the on state, the larger the voltage of the gate-to-source voltage Vgs of the synchronous rectification transistor M1, the larger the current flowing through the synchronous rectification transistor M1 is controlled to be.
In an embodiment of the present invention, the conduction voltage drop adjustment circuit 7 includes a transconductance operational amplifier 71, a first input terminal and a second input terminal of which are respectively coupled to the drain of the synchronous rectification transistor M1 and a second reference voltage-V2, an output terminal of which is coupled to the control terminal of the synchronous rectification transistor M1, and the second reference voltage is the setting reference signal.
As shown in fig. 6, in an embodiment of the present invention, the conduction voltage drop adjustment circuit 7 includes a transconductance operational amplifier 71 and a transconductance operational amplifier control unit 73. The first input terminal and the second input terminal of the transconductance operational amplifier 71 are respectively coupled to the drain of the synchronous rectification transistor M1 and the second reference voltage-V2, and the output terminal of the transconductance operational amplifier 71 is coupled to the control terminal of the synchronous rectification transistor M1. The input end of the transconductance operational amplifier control unit 73 is coupled to the output end of the third comparator U3 and the output end of the RS flip-flop 31, respectively, and the output end of the transconductance operational amplifier control unit 73 is coupled to the enable end of the transconductance operational amplifier 71. In an embodiment of the present invention, after the PWM signal PWM effectively continues to set time and the voltage Vds between the drain and the source of the synchronous rectification transistor M1 > the second reference voltage-V2 is satisfied, the transconductance operational amplifier control unit 73 outputs a control signal to control the operation of the transconductance operational amplifier 71 (otherwise, the transconductance operational amplifier EA does not perform the adjustment function), and the transconductance operational amplifier adjusts the driving voltage of the synchronous rectification transistor M1. Wherein, the PWM signal PWM effective may be the PWM effective generated by the pulse width modulation module in the driving unit. When the flip-flop is in the set state, the PWM may be active.
In an embodiment of the present invention, the driving circuit controls the synchronous rectification transistor M1 to be completely turned on when Vds of the synchronous rectification transistor M1 is smaller than the first reference voltage-V1. In an embodiment of the present invention, the driving circuit controls the synchronous rectification transistor M1 to be turned off when the voltage Vds between the drain and the source of the synchronous rectification transistor M1 is greater than the third reference voltage-V3. In an embodiment of the present invention, after the voltage Vds between the drain and the source of the conducting voltage drop adjusting circuit in the PWM effective duration setting time and the synchronous rectification transistor M1 > the second reference voltage-V2, the conducting voltage drop adjusting circuit controls the voltage Vgs between the gate and the source of the synchronous rectification transistor M1 to decrease when the voltage Vds is greater than the second reference signal, and controls the voltage Vgs between the gate and the source of the synchronous rectification transistor M1 to increase when the voltage Vds is less than the second reference voltage-V2.
In an embodiment of the present invention, the adjusting of the set reference voltage by the signal adjusting circuit 5 includes: if the time difference delta T from when Vds begins to be greater than the second reference voltage to when Vds is greater than the third reference voltage within the period is greater than the set time difference threshold T0, increasing the value of the second reference voltage; if the time difference Δ T from when Vds begins to be greater than the second reference voltage to when Vds is greater than the third reference voltage within the cycle is less than the set time difference threshold T0, the value of the second reference voltage is decreased.
Fig. 9 is a flowchart illustrating voltage (second reference voltage-V2) adjustment in the synchronous rectification control mode according to an embodiment of the present invention; referring to fig. 9, in an embodiment of the present invention, the adjusting process of the second reference voltage-V2 includes: t0 is set inside the synchronous rectification control circuit, when the MOS tube is conducted in the nth period, the delta T in the current period is obtained, the delta T is the time difference that Vds begins to be larger than-V2 to Vds > -V3, otherwise, the MOS tube is waited to be conducted. Namely, a point of time when the voltage Vds between the drain and the source of the synchronous rectification transistor M1 starts to be greater than-V2 and a point of time when the voltage Vds between the drain and the source is greater than the third reference voltage, Δ T is a time difference between the two points of time. When the time difference Δ T of the nth cycle > T0, assigning V2 of the next cycle as V2- Δ V; when the time difference Δ T of the nth cycle is < T0, V2 of the next cycle is assigned to V2+ Δ V. Entering the next period, when the MOS tube is conducted in the (n + 1) th period, obtaining the delta T in the current (n + 1) th period, and repeating the assignment rule of the V2.
Fig. 10 is a signal waveform diagram of voltage regulation according to an embodiment of the present invention; referring to fig. 10, in an embodiment of the present invention, when the MOS transistor is turned on in the nth cycle, Δ T > T0 assigns V2 of the next cycle to V2- Δ V, i.e., the second reference voltage-V2 is-V2 + Δ V, i.e., the value of-V2 is raised, as shown in fig. 10. When the MOS transistor is turned on in the (n + 1) th period, the value of the voltage DeltaTn is less than T0, and the value of the voltage V2 in the next period is assigned to be V2+ DeltaV, namely the value of the voltage V2 is-V2-DeltaV, -V2 is reduced. The second reference voltage-V2 in each subsequent cycle is assigned according to the above rule. Through the assignment of adjusting V2, can realize the accurate shutoff of SR MOSFET, turn-off speed improves, the utility model discloses a synchronous rectification control circuit and control method adopt self-adaptation's regulation mode in order to adapt to different SR MOSFETs.
The utility model discloses an in the embodiment, synchronous rectification control circuit includes high-pressure starting module, the drain terminal of synchronous rectification transistor is coupled to high-pressure starting module's input, and the power supply pin of synchronous rectification control circuit is coupled to high-pressure starting module's output.
In an embodiment of the present invention, the synchronous rectification control circuit includes the synchronous rectification transistor.
The utility model discloses an in the embodiment, an isolated power supply converting circuit is disclosed, isolated power supply converting circuit includes primary circuit and secondary circuit, and the primary circuit receives input voltage, and the primary circuit includes primary winding and primary switch. The secondary circuit comprises a secondary winding and the synchronous rectification control circuit, and the secondary winding and the primary winding are coupled to form a transformer.
The utility model discloses a synchronous rectification control method, synchronous rectification control method includes:
comparing the voltage between the drain and the source of the synchronous rectification transistor with at least one set reference signal;
sending a control signal to the synchronous rectification transistor according to a comparison result of the voltage between the drain and the source of the synchronous rectification transistor and at least one set reference signal;
and adjusting the set reference signal in the at least one reference signal according to the comparison result of the voltage between the drain and the source of the synchronous rectification transistor and the set at least one reference signal.
In an embodiment of the present invention, the setting of the reference signal may be setting of a reference voltage, and the adjusting of the setting of the reference voltage includes: if the time difference delta T from when Vds begins to be greater than the second reference voltage to when Vds is greater than the third reference voltage within the period is greater than the set time difference threshold T0, increasing the value of the second reference voltage; if the time difference Δ T from when Vds begins to be greater than the second reference voltage to when Vds is greater than the third reference voltage within the cycle is less than the set time difference threshold T0, the value of the second reference voltage is decreased. In an embodiment of the present invention, the specific adjustment manner can be referred to the above description of fig. 9 and 10.
In an embodiment of the present invention, when Vds of the synchronous rectification transistor is smaller than the first reference voltage, the synchronous rectification transistor is controlled to be completely turned on; in an embodiment of the present invention, when the voltage Vds between the drain and the source of the synchronous rectification transistor is greater than the third reference voltage, the synchronous rectification transistor is controlled to be turned off; wherein the first reference voltage is less than the third reference voltage.
In an embodiment of the present invention, after the PWM is valid for the set time and the voltage Vds between the drain and the source of the synchronous rectification transistor > the second reference voltage is satisfied, the voltage Vgs between the gate and the source of the synchronous rectification transistor is controlled to be decreased when the voltage Vds is greater than the second reference signal; and controlling the voltage Vgs between the grid electrode and the source electrode of the synchronous rectification transistor to rise when the voltage Vds is smaller than a second reference signal.
Fig. 7 is a flowchart of a synchronous rectification control method according to an embodiment of the present invention; referring to fig. 7, in an embodiment of the present invention, the voltage of the HV terminal corresponds to Vds, and the voltage of the HV terminal may be equal to Vds or positively correlated to Vds. In a certain period, when the Vds voltage at the synchronous rectification transistor (in an embodiment of the present invention, the synchronous rectification transistor is an MOS transistor, for example, it can be an MOSFET) is smaller than the first reference voltage-V1, the first comparator U1 outputs a high level, and the RS flip-flop is in a set state, so that the MOS transistor is completely turned on. And then, carrying out condition judgment to judge whether the following conditions are met simultaneously: a. PWM is effective and lasts for a certain time T; b. the current cycle occurs through Vds > -V2. If the two conditions are met simultaneously, the MOS tube is controlled to enter a conduction voltage drop regulation process, otherwise, the MOS tube is still continuously and completely conducted. When Vds is larger than a second reference voltage-V2, the conduction voltage drop regulating circuit controls the driving voltage Vgs to be reduced; when Vds is less than the second reference voltage-V2, the conduction voltage drop adjustment circuit controls the driving voltage Vgs to rise. When Vds is still less than the third reference voltage-V3, the second comparator U2 outputs a low level, repeating the above comparison between Vds and-V2 to adjust the driving voltage Vgs. When Vds is larger than a third reference voltage-V3, the second comparator U2 outputs a high level, the RS trigger is in a reset state, and the MOS transistor is cut off.
Fig. 8 is a signal waveform diagram of a synchronous rectification control method according to an embodiment of the present invention; referring to fig. 8, in an embodiment of the present invention, the control process is as shown in the signal waveform diagram corresponding to fig. 8.
Under the condition that the set reference signal of the conduction voltage drop adjusting circuit is fixed and unchanged, because the internal resistances of various synchronous rectifier tube SRMOSFETs are different, the turn-off points are different, and the voltage stress of the SR MOSFET is influenced. The utility model discloses can match the settlement reference signal that corresponds adaptively according to the SR MOSFET of difference to accurate correspondence closes the breakpoint, in order to realize accurate shutoff.
To sum up, the utility model provides a synchronous rectification control circuit and isolated power supply converting circuit can realize the accurate shutoff to synchronous rectifier transistor (if present SR MOSFET), can improve turn-off speed simultaneously to the synchronous rectifier transistor (if present SR MOSFET) of the different internal resistances of adaptation. The utility model discloses can compatible CCM, efficient, and can avoid former vice limit to be in common, promoted the reliability of circuit.
The description and applications of the present invention are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the present invention.
Claims (10)
1. A synchronous rectification control circuit is characterized in that the synchronous rectification control circuit can be coupled with a synchronous rectification transistor and can send a control signal to the synchronous rectification transistor; the synchronous rectification control circuit comprises:
the input end of the comparison circuit is respectively coupled with the synchronous rectification transistor and at least one reference signal, and the output end of the comparison circuit is respectively coupled with the driving circuit and the signal regulating circuit;
the output end of the driving circuit is coupled with the synchronous rectifying transistor and used for sending a control signal to the synchronous rectifying transistor according to the signal output by the comparison circuit;
the input end of the signal regulating circuit is coupled with the comparison circuit, and the output end of the signal regulating circuit is coupled with the conduction voltage drop regulating circuit and used for regulating a set reference signal in at least one reference signal according to a signal output by the comparison circuit; and
and the input end of the conduction voltage drop regulating circuit is coupled with the set reference signal, and the output end of the conduction voltage drop regulating circuit is coupled with the synchronous rectifying transistor and used for regulating the control end voltage of the synchronous rectifying transistor.
2. The synchronous rectification control circuit of claim 1, wherein:
the conduction voltage drop adjusting circuit comprises a transconductance operational amplifier, a first input end and a second input end of the transconductance operational amplifier are respectively coupled with a drain electrode of the synchronous rectification transistor and a second reference signal, an output end of the transconductance operational amplifier is coupled with a control end of the synchronous rectification transistor, and the second reference signal is the set reference signal.
3. The synchronous rectification control circuit of claim 1, wherein:
the driving circuit comprises a trigger, wherein the set end of the trigger is coupled with the first output end of the comparison circuit, the reset end of the trigger is coupled with the second output end of the comparison circuit, and the output end of the trigger is coupled with the control end of the synchronous rectification transistor.
4. The synchronous rectification control circuit of claim 1, wherein:
the driving circuit comprises a trigger;
the comparison circuit comprises a first comparator and a second comparator; the input end of the first comparator is respectively coupled with the first reference signal and the drain electrode of the synchronous rectification transistor; the input end of the second comparator is respectively coupled with the drain electrode of the synchronous rectification transistor and a third reference signal;
the output end of the first comparator is coupled with the position end of the trigger; the output end of the second comparator is coupled with the reset end of the trigger, and the output end of the trigger is coupled with the control end of the synchronous rectification transistor.
5. The synchronous rectification control circuit of claim 4, wherein:
the conduction voltage drop adjusting circuit comprises a transconductance operational amplifier and a transconductance operational amplifier control unit, wherein the input end of the transconductance operational amplifier control unit is respectively coupled with the output end of the third comparator and the output end of the trigger, and the output end of the transconductance operational amplifier control unit is coupled with the enabling end of the transconductance operational amplifier.
6. The synchronous rectification control circuit of claim 1, wherein:
the synchronous rectification control circuit comprises a high-voltage starting module, wherein the input end of the high-voltage starting module is coupled with the drain end of the synchronous rectification transistor, and the output end of the high-voltage starting module is coupled with the power supply pin of the synchronous rectification control circuit.
7. The synchronous rectification control circuit of claim 1, wherein:
at least one reference signal coupled to an input end of the comparison circuit comprises a first reference signal, a second reference signal and a third reference signal; the setting reference signal is a second reference signal.
8. The synchronous rectification control circuit of claim 7, wherein:
the comparison circuit comprises a first comparator, a second comparator and a third comparator; the positive phase input end of the first comparator is coupled with a first reference signal, and the negative phase input end of the first comparator is coupled with the drain electrode of the synchronous rectification transistor;
the positive phase input end of the second comparator is coupled with the drain electrode of the synchronous rectification transistor, and the negative phase input end of the second comparator is coupled with the third reference signal;
the positive phase input end of the third comparator is coupled with the drain electrode of the synchronous rectification transistor, and the negative phase input end of the third comparator is coupled with the second reference signal.
9. The synchronous rectification control circuit of claim 8, wherein:
the input end of the signal adjusting circuit is respectively coupled to the output end of the third comparator and the output end of the second comparator, and is used for obtaining output signals of the second comparator and the third comparator so as to adjust the value of the second reference signal.
10. An isolated power conversion circuit is characterized by comprising a primary side circuit and a secondary side circuit, wherein the primary side circuit receives an input voltage and comprises a primary side winding and a primary side switch; the secondary circuit comprises a secondary winding and a synchronous rectification control circuit as claimed in any one of claims 1-9, the secondary winding and the primary winding being coupled to form a transformer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110896283A (en) * | 2019-12-13 | 2020-03-20 | 杭州必易微电子有限公司 | Synchronous rectification control circuit, isolated power supply conversion circuit and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110896283A (en) * | 2019-12-13 | 2020-03-20 | 杭州必易微电子有限公司 | Synchronous rectification control circuit, isolated power supply conversion circuit and control method |
| CN110896283B (en) * | 2019-12-13 | 2024-07-02 | 杭州必易微电子有限公司 | Synchronous rectification control circuit, isolated power conversion circuit and control method |
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