CN211149492U - Printing consumable chip - Google Patents

Abstract

The utility model provides a printing consumable chip, which comprises a clock module, a central control module, a random number module, a storage module, a communication module and a data protection module; the central control module is respectively connected with the clock module, the random number module, the storage module, the communication module and the data protection module and is used for fetching and decoding and executing control on other modules; the clock module is used for providing a clock for the chip; the storage module is used for storing data written into the chip; the data protection module is used for verifying and authenticating with the printer; the random digital module is used for generating random data required by the data protection module; the communication module is responsible for communicating with the host computer, is used for receiving or sending the information of communicating with the host computer, the communication module still includes antenna element. Through the utility model discloses can solve chip manufacturing cost, size, the problem of flexibility is used in the installation, provides more nimble scheme for the design of chip.

Description

Printing consumable chip

Technical Field

The utility model relates to a printing consumables field especially relates to a printing consumables chip.

Background

Most of consumable chips communicated with a printer on the market are connected in a contact mode, the connection mode not only occupies a large area on the chip and causes the size of the whole chip to be limited, but also causes the corresponding contacts of the chip and the printer to be contacted, causes the installation position of the chip to be limited by the printer and an ink box structure, and has a plurality of limitations.

Disclosure of Invention

Based on this, it is necessary to provide a printing consumable chip aiming at the problem that the printing consumable chip in the related art can only contact communication.

According to the utility model discloses an aspect provides printing consumables chip, include:

the device comprises a clock module, a central control module, a random number module, a storage module, a communication module and a data protection module; the central control module is respectively connected with the clock module, the random number module, the storage module, the communication module and the data protection module and is used for fetching and decoding and executing control on other modules; the clock module is used for providing a clock for the chip; the storage module is used for storing data written into the chip; the data protection module is used for verifying and authenticating with the printer; the random digital module is used for generating random data required by the data protection module; the communication module is responsible for communicating with the host computer and is used for receiving or sending information communicated with the host computer, and the communication module comprises an antenna unit.

In one embodiment, the communication module at least further includes a filtering demodulation unit and a load modulation unit, and the filtering demodulation module and the load modulation module are respectively connected to the antenna unit.

In one embodiment, the filtering demodulation unit is composed of a three-stage filtering circuit and a demodulation circuit, and the three-stage filtering circuit is connected with the demodulation circuit in series.

In one embodiment, the demodulation circuit includes: the grid electrodes of the sixth transistor, the seventh transistor and the eighth transistor are connected with the drain electrodes of the sixth transistor, the source electrode of the sixth transistor is connected with the drain electrode of the seventh transistor, the source electrode of the seventh transistor is connected with the drain electrode of the eighth transistor, and the source electrode of the eighth transistor is grounded; the drain electrode of the ninth transistor is connected with a sixth resistor, the other end of the sixth resistor is connected with a seventh resistor and the grid electrode of the ninth transistor, the other end of the seventh resistor is connected with the grid electrode of the tenth transistor, the source electrode of the ninth transistor is connected with a fourth resistor, and the other end of the fourth resistor is grounded; the sources of the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are respectively grounded, the drains of the tenth transistor, the eleventh transistor and the fifteenth transistor are respectively connected with the drains of the second transistor, the third transistor, the fourth transistor and the fifteenth transistor, the eleventh transistor is connected with the drain of the tenth transistor, and the gate of the thirteenth transistor is connected with the drain of the twelfth transistor; the grid electrodes of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are mutually connected, and the drain electrode of the first transistor is connected with the grid electrode of the first transistor; the sources of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all grounded; the drain electrode of the third transistor is connected with the input end of the first inverter, and the output end of the first inverter is connected with the first output end; the drain electrode of the fifth transistor is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the second output end.

In one embodiment, the load modulation unit includes at least four selected circuits, and the selected circuits are connected in parallel.

In one embodiment, the selective breaking branch comprises at least a resistor and a transistor, and the resistor and the transistor are connected in series.

In one embodiment, the data protection module comprises an algorithm unit and a data verification unit, wherein the algorithm unit is used for security authentication of a chip and read/write protection of data information; the data verification unit is used for verifying the authenticity of the input data information.

In one embodiment, the algorithm unit comprises an algorithm input, an algorithm main body and an algorithm output, wherein the algorithm main body comprises an algorithm check control group and an algorithm state control group, the algorithm check control group is composed of an exclusive-or gate check circuit, and the algorithm state control group is composed of a plurality of counters.

In one embodiment, the data check unit is composed of two parts, namely CRC data check and ID data check.

In one embodiment, the memory module includes at least one of volatile memory cells and non-volatile memory cells.

The printing consumable chip provided by the embodiment of the utility model comprises a clock module, a central control module, a random number module, a storage module, a communication module and a data protection module; the central control module is respectively connected with the clock module, the random number module, the storage module, the communication module and the data protection module and is used for fetching and decoding and executing control on other modules; the clock module is used for providing a clock for the chip; the storage module is used for storing data written into the chip; the data protection module is used for verifying and authenticating with the printer; the random digital module is used for generating random data required by the data protection module; the communication module is responsible for communicating with the host computer for receive or send the information with the host computer communication, communication module still includes antenna element, can solve chip manufacturing cost, size, installs the problem of use flexibility, provides more flexible scheme for the design of chip.

The consumable chip comprises the communication module, the communication module at least further comprises a filtering demodulation unit and a load modulation unit, the filtering demodulation unit and the load modulation unit are respectively connected with the antenna unit, so that accurate feedback of output signals of the antenna unit and accurate obtaining of a rising edge and a falling edge of signals of the antenna unit can be achieved, and analog signals on the antenna unit are converted into digital signals.

Drawings

Fig. 1 is a block diagram of a printing consumable chip according to an embodiment of the present invention.

Fig. 2 is an algorithm frame diagram of an algorithm unit of a printing consumable chip according to the embodiment of the present invention.

Fig. 3 is a circuit diagram of a filtering demodulation unit of a printing consumable chip according to the present invention.

Fig. 4 is a circuit diagram of a load modulation unit of a printing consumable chip according to an embodiment of the present invention.

Detailed Description

In this embodiment, the embodiment of the utility model provides a printing consumables chip is provided. Fig. 1 is a block diagram of a printing consumable chip according to an embodiment of the present invention. As shown in fig. 1, the printing consumable chip apparatus includes:

the device comprises a clock module, a central control module, a random number module, a storage module, a communication module and a data protection module; the central control module is respectively connected with the clock module, the random number module, the storage module, the communication module and the data protection module and is used for fetching and decoding and executing control on other modules; the clock module is used for providing a clock for the chip; the random digital module is used for generating random data required by the data protection module; the storage module is used for storing data written into the chip; the data protection module is used for verifying and authenticating with the printer; the communication module is responsible for communicating with the host computer, is used for receiving or sending the information of communicating with the host computer, the communication module still includes antenna element. In this embodiment, the central control module and each of the other modules and the modules are connected in an electrical connection and/or a communication connection.

The clock module is connected with the central control module and used for providing clock signals for the central control module so as to ensure normal work of the chip and normal output of signals.

Wherein, central control module does the utility model discloses the treater of consumptive material chip can be the ARM kernel, also can be the MSP430 kernel. The central control module is responsible for printer command data processing, including receiving commands and data sent by the printer, such as a computer authentication command. The storage module is connected with the central control module and used for receiving and storing printer transmission data, and the storage module at least comprises one of a nonvolatile storage unit and a volatile storage unit.

In the embodiment, the storage module comprises a nonvolatile storage unit and a volatile storage unit, wherein the nonvolatile storage unit and the volatile storage unit are connected with each other and used for calling and storing data, the nonvolatile storage unit is F L ASH or EEPROM and used for storing various recording information (including ID identification codes and the like), the volatile storage unit is SRAM and used for storing temporarily generated data, such as data received by communication, data sent by communication and the like.

Of course, the memory module may be a nonvolatile memory unit or a volatile memory unit as long as data saving can be achieved according to design requirements, and it should be understood that the nonvolatile memory unit is not limited to F L ASH or EEPROM as long as data storage can be achieved and data is not lost.

The random number module is connected with the data protection module, and is configured to generate a random number for the data protection module to perform data processing, and provide a secret foundation for data output of the data protection module.

The data protection module is respectively connected with the random number module, the central control module and the communication module and used for verifying authenticity of input data information and data in the chip and guaranteeing data safety of the chip.

In this embodiment, the data protection module includes an algorithm unit and a data verification unit.

The data checking unit is connected with the central control module and used for checking authenticity of input data information.

Specifically, the CRC data check is to perform N-bit CRC data matching on the CRC data received by the chip, if the data matching is successful, the received data is proved to be correct, and the next operation can be continuously performed, otherwise, the chip determines that the data is invalid, and the chip maintains the original state.

And the ID data verification is to perform data matching on the received ID identification code, if the matching is successful, the received ID data is proved to be correct, the next operation can be continuously executed, otherwise, the chip judges that the data is invalid, and the chip keeps the original state.

Of course, the data checking unit may be executed by CRC data checking or ID data checking alone according to design requirements, and it should be understood that the data checking unit checking method is not limited thereto as long as it can perform authenticity checking on the input data information.

The algorithm unit is respectively connected with the random number module, the central control module and the communication module, receives the random numbers generated by the random number module, receives data in the storage module and control instructions of the central control module transmitted by the communication module, and combines and operates related data and control instructions to realize the safety authentication of the chip.

Specifically, in this implementation, the algorithm unit is connected to the random number module, receives the random number of the random number module for data operation, and is connected to the central control module, the central control module is connected to the volatile memory unit and the nonvolatile memory unit in the memory module, respectively, the volatile memory unit in the memory module is connected to the nonvolatile memory unit in the memory module, and the algorithm unit receives the instruction of the central control module, and calls the data of the nonvolatile memory to the algorithm unit through the control instruction, thereby generating the data required by the algorithm unit. The scheme for calling the data of the nonvolatile memory by the specific algorithm unit is as follows: the control module transmits the calling instruction to the nonvolatile storage unit through the volatile storage unit, transmits data in the nonvolatile storage unit to the volatile storage unit, and the central control module calls related data through the volatile storage unit.

It is understood that the scheme for the specific algorithm unit to call the data in the nonvolatile memory unit may be to call the data in the nonvolatile memory unit directly through the control module instruction.

It can be understood that, when the chip is authenticated, the printer sends an authentication command and a string of unique data to the consumable chip, after the consumable chip receives the command and the data through the communication module, the central control module controls to input the data sent by the printer, the random data generated by the random digital-analog module of the chip and part of the data in the nonvolatile storage unit into the algorithm unit, and the algorithm unit operates the mechanism of the algorithm unit to process the data.

In the present embodiment, the central control module controls a part of data input into the nonvolatile memory unit of the arithmetic unit to be input through the volatile memory unit.

Specifically, an algorithm frame diagram of the algorithm unit is shown in fig. 2, and in the present embodiment, the algorithm is divided into 3 parts: algorithm input, algorithm body and algorithm output. The algorithm input is connected with the algorithm main body, the algorithm main body is connected with the algorithm output, the algorithm input is responsible for inputting data, the algorithm main body is responsible for calculating, and the algorithm output is responsible for outputting the calculated data to the communication module or the central control module.

Wherein the algorithm inputs include: random numbers, command inputs, and inputs to volatile memory cells. Specifically, the random number is derived from a random number module; the instruction input is from the central control module; the input to the volatile memory cell is derived from the non-volatile memory cell.

The algorithm main body is composed of an algorithm operation group, an algorithm check control group and an algorithm state control group. The algorithm state control group is respectively connected with the algorithm operation group and the algorithm check control group, and the algorithm operation group is connected with the algorithm check control group. The algorithm state control group comprises a plurality of control states, and different operations are executed according to different control state control algorithm operation groups and the control algorithm check control group is started to execute.

In the present embodiment, the arithmetic operation group includes a random number operator KReg, a register memory L Reg, and an encryption operator MReg, and is composed of 3 sets of M registers.

The random number operator KReg is a random number operation block, and specifically, the resultant random number is obtained by performing shift xor on a fixed initial input random number.

In the embodiment, the output of the register memory L Reg is still Y-bit data after being processed by a certain algorithm by reading X (X > Y) -bit data, thereby improving the responsibility of operation.

The encryption arithmetic unit MReg is mainly responsible for the encryption part of the algorithm, and mainly comprises the basic operations of shifting, exclusive-or and the like.

Of course, the arithmetic operation set is not limited to this configuration as long as encryption can be achieved according to design requirements.

The algorithm check control group is 3 groups of check lines, and the check lines can be formed by digital circuits such as NAND gates, XOR gates and the like according to the understanding of the technical personnel in the field; the algorithm state control group is used for controlling the algorithm operation group to execute different operations and controlling the algorithm check control group to start execution, and is composed of a counter in the embodiment.

It is understood that the different operations performed by the algorithm state control group to control the set of algorithm operations may be any one of encryption, operations, etc.

The uncertainty of the algorithm input end of the algorithm unit and the complexity of the algorithm main body ensure the safety of the algorithm output end.

As shown in fig. 1, the communication module is connected to the central control module for implementing real-time communication between the printing consumable chip and the printer, and the communication module is connected to the storage module for external data storage and internal data output.

In this embodiment, the communication module is an antenna unit, and the communication module includes a filtering demodulation unit and a load modulation unit.

Specifically, as shown in the circuit of the filtering demodulation unit of the printing consumable chip in fig. 3, the filtering demodulation unit is composed of a three-level filtering circuit and a demodulation circuit, wherein the three-level filtering circuit is connected in series with the demodulation circuit;

in this embodiment, the first input terminal signal-in is connected to one end of the first resistor R1, the first resistor R1 is connected to the first capacitor C1, the second resistor R2 is connected to the second capacitor C2, and the third resistor R3 is connected to the third capacitor C3, so as to form a three-stage filter circuit.

The three-stage filter circuit and the demodulation circuit are conducted through a fourth capacitor C4. Specifically, one end of the capacitor C4 is connected to the third resistor R3 in the three-stage filter circuit, and the other end is connected to the drain of the sixth transistor MOS6 in the demodulation circuit.

The demodulation circuit is specifically configured that the gates of a sixth MOS6, a seventh MOS7 and an eighth MOS8 are connected to the drains thereof, the source of a sixth MOS6 is connected to the drain of a seventh MOS7, the source of the seventh MOS7 is connected to the drain of the eighth MOS7, the source of the eighth MOS7 is grounded, the drain of the ninth MOS7 is connected to a sixth resistor R7, the other end of the sixth resistor R7 is connected to the gates of a seventh resistor R7 and a ninth MOS7, the other end of the seventh resistor R7 is connected to the gate of a tenth MOS7, the source of the ninth MOS7 is connected to a fourth resistor R7, the other end of the fourth resistor R7 is grounded, the sources of the tenth, eleventh, twelfth and thirteenth MOS7, the thirteenth MOS 72, the fifth MOS 72, the sixth, the eleventh, the twelfth, the fifteenth, the fifth, the twelfth, the fifteenth, the twelfth, the fifteenth, the eleventh, the fifth, the eleventh, the twelfth, the eleventh, the fifteenth, the eleventh, the twelfth, the eleventh, the twelfth.

In this embodiment, the transistors of the first transistor MOS1, the second transistor MOS2, the third transistor MOS3, the fourth transistor MOS4, and the fifth transistor MOS5 are NMOS transistors, and the rest are PMOS transistors.

External data, namely an input signal, is transmitted to a three-stage RC band-pass filter through a first input end signal-in a filtering demodulation unit circuit, clutter is filtered, a rising edge and a falling edge of the input signal are analyzed through a demodulation circuit, the rising edge in the analyzed signal is output through a first output end F L AF _ RISE end respectively, the falling edge in the analyzed signal is output through a second output end F L AF _ FA LL end, namely the rising edge and the falling edge of the signal are converted into triangular waves through a filtering demodulation module, then the rising edge and the falling edge are converted into digital signals through a later demodulation circuit, and data receiving is completed.

The load modulation unit, as shown in the load modulation unit circuit of the printing consumable chip of fig. 4, includes at least four selective breaking branches capable of being selectively opened and closed, which are the selective breaking branch 1, the selective breaking branch 2, the selective breaking branch 3, and the selective breaking branch 4, and the selective breaking branches are connected in parallel. Each of the selected breaking branches includes at least a resistor and a transistor. The resistors with different total resistance values are arranged on the selective-breaking branch, so that amplitude modulation can be carried out on the voltage of the antenna, and the data are transmitted to the reader from the communication module, so that the voltage on the antenna of the reader is changed, and accurate feedback of the output signal of the antenna unit is realized.

Specifically, the gate of the eighteenth transistor MOS18 connected to the DATA enable terminal DATA-EN, and the source of the eighteenth transistor MOS18 are connected to ground; the first control end T0, the second control end T1, the third control end T2 and the fourth control end T3 are respectively connected with the gates of a fourteenth transistor MOS14, a fifteenth transistor MOS15, a sixteenth transistor MOS16 and a seventeenth transistor MOS17, and the drain of the eighteenth transistor MOS18 is respectively connected with the sources of a fourteenth transistor MOS14, a fifteenth transistor MOS15, a sixteenth transistor MOS16 and a seventeenth transistor MOS 17; the drain electrode of the fourteenth transistor MOS14 is connected with an eighth resistor R8, and the other end of the eighth resistor R8 is connected with a MODV-IN end; the drain of the transistor MOS15 is connected IN series with a ninth resistor R9 and a tenth resistor R10, and the other end of the ninth resistor R9 is connected with MODV-IN; the drain of the sixteenth transistor MOS16 is connected IN series with an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13, and the other end of the eleventh resistor R11 is connected with a second input end MODV-IN; the drain of the seventeenth transistor MOS17 is connected IN series to a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a seventeenth resistor R17, and the other end of the fourteenth resistor R14 is connected to the second input terminal MODV-IN.

The transistors of the fourteenth transistor MOS14, the fifteenth transistor MOS15, the sixteenth transistor MOS16, the seventeenth transistor MOS17 and the eighteenth transistor MOS18 are PMOS transistors.

The load modulation unit principle is as follows: when the chip transmits data, a load modulation mode is adopted, and the transmitted data controls the on-off of the PMOSE tube through the high and low voltages of T0-T3, so that the on-off of the load voltage is controlled. The resistors with different total resistance values are arranged on different branches, so that the voltage of the antenna can be subjected to amplitude modulation, and the data are transmitted to the reader from the communication module, so that the voltage on the antenna of the reader is changed, and the data transmission is completed.

It can be understood that the printer comprises the reader, the consumable chip comprises the antenna module, and the printer can be wirelessly connected to the reader of the printer through the RFID, so that the communication between the printer and the consumable chip is realized.

When printing, the printer sends fixed sequence information to the consumable chip; the consumable chip feeds back the corresponding ID in the nonvolatile storage unit to the printer for ID identification; and the printer sends authentication information to the consumable chip after identifying the ID, an algorithm unit of the consumable chip feeds back the result of processing such as data received in the volatile storage unit, input data and the like to the printer for authentication, and conventional printing and other operations (reading and writing ink quantity of the ink box, reading and writing configuration information and the like) are carried out after the authentication is passed.

Taking the amount of ink to be read and written as an example: the printer reads the ink amount information of the ink box in the nonvolatile storage unit in the consumable chip, calculates the residual ink amount according to the printing amount and writes the residual ink amount back to the nonvolatile storage unit.

The utility model discloses in, the consumptive material chip includes: the consumable chip comprises a clock module, a central control module, a storage module, a communication module and a data protection module, wherein the modules are mutually connected and interacted, so that the consumable chip and the printer are normally interacted.

In this embodiment, when the chip operates, the clock module provides a clock for the chip to operate. The consumable chip is controlled by the central control module, information is read from the nonvolatile storage unit to the volatile storage unit, and the volatile storage unit is used for performing due initialization configuration on the chip, so that the chip reaches an initial working state. And then the chip receives corresponding information through the communication module, the central controller controls the verification of the received data, and if the verification is passed, the required next operation (such as data reading and writing, data processing and the like) is continued. When reading data, the data will read information from the non-volatile memory cells to the volatile memory cells and then from the communication module. When data is written, the data is received from the communication module and verified, then is sent to the volatile storage unit, and then is sent from the volatile storage unit to the nonvolatile storage unit for storage. When data protection, authentication and other processing are needed, the data can be correspondingly processed from the communication module and the volatile storage unit to the algorithm unit under the control of the central control module, and finally the processed data can be returned to the central control module and the communication module.

In summary, according to at least one embodiment, the problems of manufacturing cost, size and flexibility in installation and use of the chip are solved, and a more flexible scheme is provided for the design of the chip.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only represent some embodiments of the present invention, and the description thereof is specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (10)

1. A printing consumable chip comprises a clock module, a central control module, a random number module, a storage module, a communication module and a data protection module;

the central control module is respectively connected with the clock module, the random number module, the storage module, the communication module and the data protection module and is used for fetching and decoding and executing control on other modules;

the clock module is used for providing a clock for the chip;

the storage module is used for storing data written into the chip;

the data protection module is used for verifying and authenticating with the printer;

the random digital module is used for generating random data required by the data protection module;

the communication module is responsible for communicating with the host computer and is used for receiving or sending information communicated with the host computer, and the communication module is characterized by comprising an antenna unit.

2. The printing consumable chip of claim 1, wherein the communication module further comprises at least a filtering demodulation unit and a load modulation unit, and the filtering demodulation unit and the load modulation unit are respectively connected with the antenna unit.

3. The printing consumable chip of claim 2, wherein the filtering demodulation unit is comprised of a three-stage filtering circuit and a demodulation circuit, the three-stage filtering circuit being in series communication with the demodulation circuit.

4. The printing consumable chip of claim 3, wherein the demodulation circuit comprises: the grid electrodes and the drain electrodes of the sixth transistor, the seventh transistor and the eighth transistor are connected, the source electrode of the sixth transistor is connected with the drain electrode of the seventh transistor, the source electrode of the seventh transistor is connected with the drain electrode of the eighth transistor, and the source electrode of the eighth transistor is grounded; the drain electrode of the ninth transistor is connected with a sixth resistor, the other end of the sixth resistor is connected with a seventh resistor and the grid electrode of the ninth transistor, the other end of the seventh resistor is connected with the grid electrode of the tenth transistor, the source electrode of the ninth transistor is connected with a fourth resistor, and the other end of the fourth resistor is grounded; the sources of the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are respectively grounded, the drains of the tenth transistor, the eleventh transistor, the fourth transistor and the fifteenth transistor are respectively connected with the drains of the second transistor, the third transistor, the fourth transistor and the fifteenth transistor, the eleventh transistor is connected with the drain of the tenth transistor, and the gate of the thirteenth transistor is connected with the drain of the twelfth transistor; the grid electrodes of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are mutually connected, and the drain electrode of the first transistor is connected with the grid electrode of the first transistor; the sources of the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all grounded; the drain electrode of the third transistor is connected with the input end of a first inverter, and the output end of the first inverter is connected with a first output end; and the drain electrode of the fifth transistor is connected with the input end of the second phase inverter, and the output end of the second phase inverter is connected with the second output end.

5. The printing consumable chip of claim 2, wherein the load modulation unit comprises at least four selectively-on/off selective branches, and the selective branches are connected in parallel.

6. The printing consumable chip of claim 5, wherein the selective breaking branch comprises at least a resistor and a transistor, and the resistor and the transistor are connected in series.

7. The printing consumable chip of claim 1, wherein the data protection module comprises an algorithm unit and a data verification unit, wherein the algorithm unit is used for security authentication of the chip and read/write protection of data information; the data verification unit is used for verifying the authenticity of the input data information.

8. The printing consumable chip of claim 7, wherein the algorithm unit comprises an algorithm input, an algorithm main body and an algorithm output, wherein the algorithm main body comprises an algorithm check control group and an algorithm state control group, the algorithm check control group is composed of an exclusive-or gate check circuit, and the algorithm state control group is composed of a plurality of counters.

9. The printing consumable chip of claim 7, wherein the data check unit comprises at least one of a CRC data check and an ID data check.

10. The printing consumable chip of claim 1, wherein the memory module comprises at least one of a volatile memory unit and a non-volatile memory unit.

Images