CN211148784U - Circuit for load impedance framework measurement - Google Patents
Circuit for load impedance framework measurement Download PDFInfo
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- CN211148784U CN211148784U CN201921604137.2U CN201921604137U CN211148784U CN 211148784 U CN211148784 U CN 211148784U CN 201921604137 U CN201921604137 U CN 201921604137U CN 211148784 U CN211148784 U CN 211148784U
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- 238000005259 measurement Methods 0.000 title claims abstract description 16
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- 238000005070 sampling Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 26
- 238000006243 chemical reaction Methods 0.000 claims abstract description 10
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- 239000003990 capacitor Substances 0.000 claims description 46
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- 238000003745 diagnosis Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000005284 excitation Effects 0.000 description 3
- 238000002847 impedance measurement Methods 0.000 description 2
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Abstract
The utility model belongs to the technical field of circuit fault diagnosis and element detection application, and discloses a circuit for load impedance framework measurement, which comprises a power supply conversion circuit, an inverter circuit, an optical coupling isolation circuit, a CPU core module, a measurement circuit and a current acquisition circuit, wherein the inverter circuit is used for generating a 24V alternating current power supply and then supplying power to the measurement circuit, one end of the resistor R31 is connected with the output end of the inverter circuit, the other end of the resistor R32 is grounded, the input end R + of the sampling resistor R3I is connected with the output end of the inverter circuit, the output end R-is grounded through a load to be tested, the other end of the resistor R31 is connected with the input end of the CPU core module, the two ends of the sampling resistor R3I are connected with the input end of the CPU core module through a current acquisition circuit, and the SPWM signal output end of the CPU core module is connected with the control end of the inverter circuit after being isolated and amplified through an optical coupling isolation circuit. The utility model discloses with low costs, measurable impedance range is big, can be applied to circuit detection area.
Description
Technical Field
The utility model belongs to the technical field of circuit fault diagnosis and component detection are used, concretely relates to be used for load impedance framework measuring circuit.
Background
In circuit fault diagnosis and component detection applications, it is often necessary to measure the passive impedance characteristics of a component network between two points. In the prior art, when the impedance characteristic of the element network is measured, a DDS (digital signal generator) is generally used to generate an alternating current excitation signal to be applied to a load impedance, which is not only costly, but also cannot measure an impedance network with a small modulus value because the smaller the modulus value of the element is, the larger the current is required, and the larger the current is difficult to output by a general DDS (digital signal generator).
SUMMERY OF THE UTILITY MODEL
The utility model overcomes the deficiencies in the prior art, the technical problem who solves is: a circuit for load impedance architectural measurement is provided.
In order to solve the technical problem, the utility model discloses a technical scheme be for a circuit for load impedance framework measurement, including power conversion circuit, inverter circuit, opto-coupler isolation circuit, CPU core module, measuring circuit and current acquisition circuit, power conversion circuit is used for giving after converting external direct current voltage into 5V direct current voltage inverter circuit, CPU core module and current acquisition circuit power supply, inverter circuit gives after being used for producing 24V alternating current power supply measuring circuit power supply, measuring circuit includes resistance R31, resistance R32, sampling resistance R3I and resistance R3L, resistance R31's one end is connected with inverter circuit's output, and the other end is grounded behind resistance R32, sampling resistance R3I's input R + is connected with inverter circuit's output, and output R-is grounded behind resistance R3L, and the load that awaits measuring is parallelly connected with resistance R3L's both ends, resistance R31's the other end is connected with CPU core module's input, sampling resistance R3I's input R + and output R3L are connected with the core current acquisition circuit's output, the SPWM circuit is connected with the output of acquisition circuit after the SPWM module control input of isolation circuit the input end of CPU.
The measuring circuit comprises a plurality of sampling resistors R3I, the resistance range of the sampling resistors is 0.01-10 ohms, and the sampling resistors are arranged between an input end R + and an output end R-through jumpers.
The inverter circuit comprises a field effect transistor Q1, a field effect transistor Q2, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C10, an electrolytic capacitor C10, a diode D10 and a diode D10, wherein an external 24V direct-current voltage positive electrode is grounded through the electrolytic capacitor C10 and the electrolytic capacitor C10, and is also grounded through the electrolytic capacitor C10, the external 24V direct-current voltage positive electrode is connected with the drain electrode of the field effect transistor Q10 through an inductor 10 2, the source electrode of the field effect transistor Q10 is connected with the drain electrode of the field effect transistor Q10, the grid electrode of the field effect transistor Q10 is connected with the first signal output end of the optical coupling isolation circuit through the resistor R10, the diode D10 is reversely connected with two ends of the resistor R10, the resistor R10 and the drain electrode of the capacitor C10 are connected between the source electrode of the field effect transistor Q10 in parallel;
the grid of the field-effect transistor Q2 is connected with the second signal output end of the optical coupling isolation circuit through a resistor R8, the source of the field-effect transistor Q2 is grounded, a diode D5 is reversely connected with two ends of the resistor R8, the resistor R9 and a capacitor C11 are connected between the source and the grid of the field-effect transistor Q2 in parallel, the diode D7 is reversely connected between the drain and the source of the field-effect transistor Q2, one end of an inductor L1 is connected with the source of the field-effect transistor Q1, and the other end of the inductor L serves as the output of the inverter circuit and is connected with the.
The type of the field-effect transistor Q1 and the type of the field-effect transistor Q2 are IRF5440, the type of the diode D4, the type of the diode D5, the type of the diode D6 and the type of the diode D7 are IN4007, the resistance values of the resistor R7 and the resistor R8 are 100 ohms, the resistance values of the resistor R9 and the resistor R10 are 10k ohms, and the inductance values of the inductor L1 and the inductor L2 are 200 uH.
The current acquisition circuit comprises an operational amplification chip U3 with the model number of NR5532, a pin VIN1+ of the operational amplification chip U3 is connected with an output end R-of a sampling resistor R3I through a resistor R21, a pin VIN 1-is connected with an input end R + of the sampling resistor R3I through a resistor R22, a pin VIN 1-is grounded through a resistor R23, a pin VOUT1 is connected with an input end of a CPU core module through a capacitor C21, and a pin VOUT1 is connected with a pin VIN 1-through a resistor R24.
The optical coupler isolation circuit comprises an optical coupler U1 and an optical coupler U2 of which the models are T L P250, wherein the input end of the optical coupler U1 is connected with the SPWM1 signal output end of the CPU core module, the output end of the optical coupler U1 is connected with a resistor R7 as the first signal output end of the optical coupler isolation circuit, the input end of the optical coupler U2 is connected with the SPWM2 signal output end of the CPU core module, and the output end of the optical coupler U2 is connected with the resistor R8 as the second signal output end of the optical coupler isolation circuit.
The power conversion circuit comprises a power chip L M2596, a diode D5-1, a transient suppression diode TVS5-1, a transient suppression diode TVS5-2, a light emitting diode L ED5-1, a light emitting diode L0 ED5-2, an electrolytic capacitor C5-1, an electrolytic capacitor C5-3, a capacitor C5-2, a capacitor C5-4, a Schottky diode D5-2, an inductor L15-1, a resistor R5-1 and a resistor R5-2, wherein a pin IN of the power chip 5M 2596 is connected with an external direct current voltage positive electrode through a fuse PTC5-1 and a diode D5-1, the electrolytic capacitor C5-1, the capacitor C5-2 and the transient suppression diode 5-1 are connected between the pin of the power chip 5M 2596 and the ground, the resistor R5-1 and the light emitting diode D5-72-1 are connected IN series with a transient suppression diode output terminal of the TVS 5-72, the transient suppression diode after the transient suppression diode is connected with the PCT-72, the transient suppression diode is connected with the transient suppression diode after the transient suppression diode D-72 and the transient suppression diode is connected IN series, the PCT-72 and the transient suppression diode is connected IN parallel connection with the direct current output terminal of the PCT-72, the TVS-72, the transient suppression diode, the PCT-72, the transient suppression diode is connected IN parallel connection, and the post-72-.
Compared with the prior art, the utility model following beneficial effect has: the utility model provides a circuit for load impedance framework is measured, it produces through exchanging inverter circuit and measures required excitation source to reduce system cost, and can export great electric current, consequently increase impedance measurement range by a wide margin.
Drawings
Fig. 1 is a schematic block diagram of a circuit for load impedance measurement according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of an inverter circuit and a measuring circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a current collecting circuit according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of an optical coupling isolation circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a voltage converting circuit according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of the CPU core module according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention; based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
As shown in fig. 1-2, the embodiment of the utility model provides a be used for load impedance framework measuring circuit, including power conversion circuit, inverter circuit, opto-coupler isolation circuit, CPU core module, measuring circuit and current acquisition circuit, power conversion circuit is used for giving after converting external direct current voltage into 5V direct current voltage inverter circuit, CPU core module and current acquisition circuit power supply, inverter circuit gives after being used for producing 24V alternating current power supply measuring circuit power supply, measuring circuit includes resistance R31, resistance R32, sampling resistance R3I and resistance R3L, resistance R31's one end is connected with inverter circuit's output, and the other end is grounded behind resistance R32, sampling resistance R3I's input R + is connected with inverter circuit's output, and output R-is grounded behind resistance R3L, and the load that awaits measuring is parallelly connected with resistance R3L's both ends, resistance R31's the other end is connected with CPU core module's input, sampling resistance R3I's input R + and output R-current acquisition circuit are connected with the input of core current acquisition circuit, the output of SPWM electric current acquisition circuit is connected the output and the output of CPU core module is connected the control signal amplification circuit is connected after the input of CPU control module.
Furthermore, in the embodiment, the measuring circuit is provided with a plurality of sampling resistors R3I, the resistance range of the sampling resistors is 0.01-10 ohms, and the sampling resistors are arranged between the input end R + and the output end R-through jumpers. According to the magnitude of the load impedance, the sampling resistor R3I with different resistance values can be selected by a jumper wire, so that the measuring circuit of the embodiment has the advantage of large measuring range of the load impedance.
Specifically, as shown in fig. 2, the inverter circuit includes a field effect transistor Q1, a field effect transistor Q2, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C10, an electrolytic capacitor C10, a diode D10, and a diode D10, wherein an external 24V dc voltage anode is grounded through the electrolytic capacitor C10 and the electrolytic capacitor C10, and also grounded through the electrolytic capacitor C10, the external 24V dc voltage anode is connected to a drain of the field effect transistor Q10 through an inductor 10 2, a source of the field effect transistor Q10 is connected to a drain of the field effect transistor Q10, a gate of the field effect transistor Q10 is connected to the first signal output terminal of the optical coupling isolation circuit through the resistor R10, the diode D10 is connected in reverse direction across the resistor R10, the resistor R10 is connected in parallel with the source of the field effect transistor Q10, and the drain of the diode D10 is connected between the source.
Specifically, as shown in fig. 2, a gate of the field effect transistor Q2 is connected with the second signal output end of the optical coupling isolation circuit through a resistor R8, a source of the field effect transistor Q2 is grounded, a diode D5 is reversely connected to two ends of the resistor R8, the resistor R9 and a capacitor C11 are connected in parallel between the source and the gate of the field effect transistor Q2, the diode D7 is reversely connected between the drain and the source of the field effect transistor Q2, one end of an inductor L1 is connected with the source of the field effect transistor Q1, and the other end of the inductor L is connected with the measurement circuit as an output of the inverter circuit.
The inductor L2, the electrolytic capacitor C12, the electrolytic capacitor C13 and the electrolytic capacitor C14 are arranged at the power supply input end of the inverter circuit and play a role in filtering, the diode D4 and the resistor R7 play a role in current-limiting protection on the field-effect tube Q1, the SPWM1 signal output by the optical coupling isolation circuit to the inverter circuit is protected from damaging the field-effect tube Q1, the resistor R10 and the capacitor C10 form a bootstrap circuit and also play a role in protecting the field-effect tube Q1, the inductor L1 at the output end of the inverter circuit plays a role in energy storage, similarly, the diode D5 and the resistor R8 play a role in current-limiting protection on the field-effect tube Q2, the SPWM2 signal output by the optical coupling isolation circuit to the inverter circuit is protected from damaging the field-effect tube Q2, the resistor R9 and the capacitor C11 form a bootstrap circuit and also play a role in protecting the field-effect tube Q2;
specifically, IN this embodiment, the models of the fet Q1 and the fet Q2 are IRF5440, the models of the diode D4, the diode D5, the diode D6, and the diode D7 are IN4007, the resistances of the resistor R7 and the resistor R8 are 100 ohms, the resistances of the resistor R9 and the resistor R10 are 10k ohms, and the inductances of the inductor L1 and the inductor L2 are 200 uH.
As shown in fig. 3, in this embodiment, the current collecting circuit includes an operational amplifier chip U3 with a model NR5532, a pin VIN1+ of the operational amplifier chip U3 is connected to an output terminal R-of a sampling resistor R3I through a resistor R21, a pin VIN1 is connected to an input terminal R + of the sampling resistor R3I through a resistor R22, the pin VIN1 is also grounded through a resistor R23, the pin VOUT1 is connected to an input terminal of the CPU core module through a capacitor C21, and the pin VOUT1 is also connected to a pin VIN 1-through a resistor R24.
In this embodiment, the operational amplifier chip U3 in the current acquisition circuit is a equidirectional proportional amplifier circuit, and the input end of the operational amplifier chip U3 is connected to the two ends of the sampling resistor R3I, so that the operational amplifier chip U3 can acquire voltage signals at the two ends of the sampling resistor R3I, amplify the voltage signals and output the amplified voltage signals to the CPU core module, and because the sampling resistor R3I is a pure resistor and the current phase of the current is the same as the current phase of the load, the voltage signals acquired by the operational amplifier chip U3 are processed to obtain the current I and the phase of the load. The output end of the resistor R31 is connected with the CPU core module, so that the voltage input to the load and the phase thereof can be obtained, and the impedance value of the load can be obtained through equivalent replacement measurement.
Specifically, as shown in fig. 4, the optical coupler isolation circuit includes an optical coupler U1 and an optical coupler U2 of a model T L P250, an input end of the optical coupler U1 is connected with an SPWM1 signal output end of a CPU core module, an output end of the optical coupler isolation circuit is connected with a resistor R7 as a first signal output end PMW1 of the optical coupler isolation circuit, an input end of the optical coupler U2 is connected with an SPWM2 signal output end of the CPU core module, and an output end of the optical coupler U2 is connected with a resistor R8 as a second signal output end PMW2 of the optical coupler isolation circuit.
Specifically, as shown IN fig. 5, the power conversion circuit comprises a power chip L M2596, a diode D5-1, a transient suppression diode TVS5-1, a transient suppression diode TVS5-2, a light emitting diode L ED5-1, a light emitting diode L0 ED5-2, an electrolytic capacitor C5-1, an electrolytic capacitor C5-3, a capacitor C5-2, a capacitor C5-4, a schottky diode D5-2, an inductor 5-1, a resistor R5-1 and a resistor R5-2, wherein a pin IN of the power chip 5M 2596 is connected with an external direct current voltage positive electrode through a fuse PTC5-1 and a diode D5-1, the electrolytic capacitor C5-1, the capacitor C5-2 and the transient suppression diode TVS5-1 are connected IN parallel with a pin IN of the power chip 5M 2596 and an IN-ground, the fuse C5-1 and a light emitting diode D5-72-1 are connected IN parallel with a post-electrical connection after the transient suppression diode D5-5 is connected with a transient suppression diode D5-72, the transient suppression diode D5-72 is connected IN parallel with a post-5-3 n input terminal, the transient suppression diode is connected IN series with a post-72 and a post-72 direct current-72, the diode after the transient suppression diode is connected IN parallel with a diode D5 and a diode D5-72 and a diode-72, the transient suppression diode.
Specifically, as shown in fig. 6, the circuit schematic diagram of the CPU core module is shown, and in this embodiment, the model of the selected CPU core module is F407.
The utility model discloses a CPU core module sends 2 way SPWM signals, after the opto-coupler isolation enlargies, control inverter circuit's contravariant frequency inverter circuit's output, for the load power supply, the utility model discloses a half-wave sine exchanges, peak-to-peak value 24V, and the trough is the 0V (system circuit negative pole) of system's power supply, and the crest is 24V, and this circuit is through appling half-wave sine alternating voltage for the load to measure the alternating voltage of load, the parameter of electric current, include voltage amplitude U, current amplitude I, voltage current phase difference △ phi, judge the impedance characteristic of load.
1. If any alternating current is supplied, △ phi =0, which indicates that the voltage and the current of the load are in the same phase, and the load presents pure resistance characteristics, and the total resistance value R = U/I.
2. If any alternating current is supplied, △ phi =90oVoltage phase, lead current phase 90 of the loadoThe load exhibits pure inductive characteristics, and L = U/(ω I) — where ω =2 π f, f represents the frequency of the AC excitation source generated by the inverter circuit.
3. If any alternating current is suppliedAll have △ phi = -90oVoltage phase, lagging current phase 90 of the load is illustratedoThe load exhibits a purely capacitive characteristic, and C = (ω =)/U.
4. If any alternating current is supplied, the power has a diameter of △>0, voltage phase of load, leading current phase, inductive property of load, and changing different AC frequency omegaKAnd calculating the equation set:
the resistance R and inductance L of the load can be calculated, and the resistance R and inductance L of the load can be calculated by converting the ac frequency twice according to the above equation system with 2 unknowns, i.e., the resistance R and inductance L.
5. If any alternating current is supplied, the power has a diameter of △<0, voltage phase and lagging current phase of the load, the load presents capacitance characteristic, and different alternating current frequencies omega are convertedKAnd calculating a system of equations:
the resistance value R and the capacitance value C of the load can be calculated.
The utility model provides a circuit for load impedance framework is measured, its interchange inverter circuit through CPU module control realizes measuring required driving source to reduce system cost, and can export great electric current, increased load impedance's measuring range by a wide margin.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (7)
1. The utility model provides a circuit for load impedance framework measurement, its characterized in that, includes power conversion circuit, inverter circuit, opto-coupler isolation circuit, CPU core module, measuring circuit and current acquisition circuit, power conversion circuit gives after being used for converting external direct current voltage into 5V direct current voltage inverter circuit, CPU core module and current acquisition circuit power supply, inverter circuit gives after being used for producing 24V alternating current power supply measuring circuit power supply, measuring circuit includes resistance R31, resistance R32, sampling resistance R3I and resistance R3L, resistance R31's one end is connected with inverter circuit's output, and the other end is grounded behind resistance R32, sampling resistance R3I's input R + is connected with inverter circuit's output, and output R-is grounded behind resistance R3L, and the load that awaits measuring is parallelly connected with resistance R3L's both ends, resistance R31's the other end is connected with CPU core module's input, sampling resistance R3I's input R + and output R-are connected with current acquisition circuit's input, current acquisition circuit's output with SPWM circuit's input and CPU core module's input is connected with the control signal amplification end behind the SPWM circuit.
2. The circuit for the structural measurement of load impedance according to claim 1, wherein the measuring circuit comprises a plurality of sampling resistors R3I with the resistance value ranging from 0.01 to 10 ohms and arranged between the input end R + and the output end R-through a jumper.
3. A circuit for load impedance framework measurement according to claim 1, wherein the inverter circuit comprises a field effect transistor Q1, a field effect transistor Q2, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C10, an electrolytic capacitor C10, a diode D10 and a diode D10, an external 24V dc voltage anode is grounded through the electrolytic capacitor C10 and the electrolytic capacitor C10, and is also grounded through the electrolytic capacitor C10, an external 24V dc voltage anode is connected with a drain of the field effect transistor Q10 through an inductor 10 2, a source of the field effect transistor Q10 is connected with the drain of the field effect transistor Q10, a gate of the field effect transistor Q10 is connected with a first signal output end of the isolation circuit through the resistor R10, the diode D10 is connected in reverse direction between the resistor R10 and the drain of the field effect transistor Q10, and the drain of the field effect transistor Q10 are connected in parallel with the source of the field effect transistor Q10, and the diode D10;
the grid of the field-effect transistor Q2 is connected with the second signal output end of the optical coupling isolation circuit through a resistor R8, the source of the field-effect transistor Q2 is grounded, a diode D5 is reversely connected with two ends of the resistor R8, the resistor R9 and a capacitor C11 are connected between the source and the grid of the field-effect transistor Q2 in parallel, the diode D7 is reversely connected between the drain and the source of the field-effect transistor Q2, one end of an inductor L1 is connected with the source of the field-effect transistor Q1, and the other end of the inductor L serves as the output of the inverter circuit and is connected with the.
4. The circuit for load impedance architectural measurement according to claim 3, wherein the type of the FET Q1 and the FET Q2 is IRF5440, the type of the diode D4, the type of the diode D5, the type of the diode D6 and the type of the diode D7 are IN4007, the resistance values of the resistor R7 and the resistor R8 are 100 ohms, the resistance values of the resistor R9 and the resistor R10 are 10k ohms, and the inductance values of the inductor L1 and the inductor L2 are 200 uH.
5. The circuit for the framework measurement of the load impedance according to claim 1, wherein the current collection circuit comprises an operational amplifier chip U3 with the model number NR5532, a pin VIN1+ of the operational amplifier chip U3 is connected with an output end R-of a sampling resistor R3I through a resistor R21, a pin VIN 1-is connected with an input end R + of the sampling resistor R3I through a resistor R22, the pin VIN 1-is also grounded through a resistor R23, the pin VOUT1 is connected with an input end of a CPU core module through a capacitor C21, and the pin VOUT1 is also connected with a pin VIN 1-through a resistor R24.
6. The circuit for the load impedance architecture measurement as claimed in claim 1, wherein the optical coupler isolation circuit comprises an optical coupler U1 and an optical coupler U2 of type T L P250, an input end of the optical coupler U1 is connected with an SPWM1 signal output end of the CPU core module, an output end of the optical coupler U1 is connected with a resistor R7 as a first signal output end of the optical coupler isolation circuit, an input end of the optical coupler U2 is connected with an SPWM2 signal output end of the CPU core module, and an output end of the optical coupler U2 is connected with a resistor R8 as a second signal output end of the optical coupler isolation circuit.
7. A circuit for load impedance architecture measurement according to claim 1, wherein the power conversion circuit comprises a power chip L M2596, a diode D5-1, a transient suppression diode TVS5-1, a transient suppression diode TVS5-2, a light emitting diode L ED5-1, a light emitting diode L0 ED5-2, an electrolytic capacitor C5-1, an electrolytic capacitor C5-3, a capacitor C5-2, a capacitor C5-4, a Schottky diode D5-2, an inductor L15-1, a resistor R5-1 and a resistor R5-2, a pin IN of the power chip 5M 2596 is connected with an external direct current voltage through a fuse PTC5-1 and a diode D5-1, the electrolytic capacitor C5-1, the capacitor C5-2 and the transient suppression diode TVS5-1 are connected IN parallel with an anode of an external direct current voltage, the electrolytic capacitor C5-1, the transient suppression diode TVS 5-72-1 is connected IN parallel with a rear transient suppression diode output terminal of the PCT-5, the transient suppression diode TVS 5-72 is connected with a rear-5-6-72-2, a rear-T-72-3 series circuit, a transient suppression diode is connected with a rear-5-72-6-72-2 series circuit, a rear-three-terminal of the transient suppression diode.
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|---|---|---|---|
| CN201921604137.2U CN211148784U (en) | 2019-09-25 | 2019-09-25 | Circuit for load impedance framework measurement |
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| CN201921604137.2U CN211148784U (en) | 2019-09-25 | 2019-09-25 | Circuit for load impedance framework measurement |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113794261A (en) * | 2021-10-15 | 2021-12-14 | 东莞市腾威动力新能源有限公司 | Portable energy storage product |
| CN113890382A (en) * | 2021-09-22 | 2022-01-04 | 中建五局土木工程有限公司 | Adjustable CT transformation ratio digital controller based on secondary current sampling |
| CN115808582A (en) * | 2022-11-21 | 2023-03-17 | 深圳市索源科技有限公司 | Inverter load detection circuit |
-
2019
- 2019-09-25 CN CN201921604137.2U patent/CN211148784U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113890382A (en) * | 2021-09-22 | 2022-01-04 | 中建五局土木工程有限公司 | Adjustable CT transformation ratio digital controller based on secondary current sampling |
| CN113794261A (en) * | 2021-10-15 | 2021-12-14 | 东莞市腾威动力新能源有限公司 | Portable energy storage product |
| CN115808582A (en) * | 2022-11-21 | 2023-03-17 | 深圳市索源科技有限公司 | Inverter load detection circuit |
| CN115808582B (en) * | 2022-11-21 | 2023-12-26 | 深圳市索源科技有限公司 | Inverter load detection circuit |
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Granted publication date: 20200731 |