CN211127264U

CN211127264U - USB intelligent quick charging circuit

Info

Publication number: CN211127264U
Application number: CN201921445088.2U
Authority: CN
Inventors: 袁信江; 吴文桃
Original assignee: Etman Electric Changzhou Co Ltd
Current assignee: Etman Electric Changzhou Co Ltd
Priority date: 2019-09-02
Filing date: 2019-09-02
Publication date: 2020-07-28
Anticipated expiration: 2029-09-02

Abstract

The utility model relates to a USB intelligent quick charging circuit, which comprises a rectifying filter circuit, a starting circuit, an RCD absorption loop circuit, a transformer, a synchronous rectifying filter circuit, a PWM control loop circuit, an EMC filter circuit and a charging protocol intelligent identification circuit; the input end of the rectification filter circuit is connected with a power supply, and the output end of the rectification filter circuit is connected with the input end of the starting circuit and the input end of the RCD absorption loop circuit; the output end of the RCD absorption loop circuit is connected with the input end of the transformer; the output end of the transformer is connected with the input end of the synchronous rectification filter circuit, the output end of the synchronous rectification filter circuit is connected with the input end of the charging protocol intelligent identification circuit, and the output end of the charging protocol intelligent identification circuit is connected with the USB; the EMC filter circuit is respectively connected with the PWM control loop circuit and the RCD absorption loop circuit; the output end of the starting circuit is connected with the input end of the PWM control loop circuit. The utility model discloses circuit design area is little, can be used to the higher USB of the less power of volume fill soon in the device.

Description

USB intelligent quick charging circuit

Technical Field

The utility model relates to a USB intelligence fills circuit soon.

Background

With the increasing and the successive generations of electronic devices, people have more and more charging demands for the electronic devices. Meanwhile, people expect that the charging efficiency of electronic equipment can be greatly improved along with high-rhythm life and work. Improving the charging efficiency of an electronic device can improve an improved charging head in addition to the electronic device itself.

However, since the internal space of the charging head is limited, it is difficult to achieve small volume and high power. For example, 10W power is difficult to achieve at 174CC volume. Meanwhile, under the power, it is difficult to realize EMC standard reaching and allowance by using elements with increased volume such as common mode inductance, Y capacitance and the like. At this volume and with the need to achieve high insulation for the new IEC-62368-1 standard (two Y capacitors are used according to the standard), the internal space becomes a direct contradiction (because of insufficient spacing).

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a USB intelligence fills circuit soon, this circuit mainly fills the device to the intelligence of small volume high power soon and designs. The rectifier filter circuit is brand-new in design, and the volume of the rectifier filter circuit is greatly reduced by adopting a patch type arrangement bridge stack and a patch type winding inductor. And meanwhile, a large-size Y capacitor is removed, and the whole size is greatly reduced while the EMC result is improved through a brand new design of the EMC filter circuit.

Realize the utility model discloses the technical scheme of purpose is: the utility model comprises a rectifying and filtering circuit, a starting circuit, an RCD absorption loop circuit, a transformer, a synchronous rectifying and filtering circuit, a PWM control loop circuit, an EMC filtering circuit and a charging protocol intelligent identification circuit; the input end of the rectification filter circuit is connected with a power supply, and the output end of the rectification filter circuit is connected with the input end of the starting circuit and the input end of the RCD absorption loop circuit; the output end of the RCD absorption loop circuit is connected with the input end of the transformer; the output end of the transformer is connected with the input end of the synchronous rectification filter circuit, the output end of the synchronous rectification filter circuit is connected with the input end of the charging protocol intelligent identification circuit, and the output end of the charging protocol intelligent identification circuit is connected with the USB; the EMC filter circuit is respectively connected with the PWM control loop circuit and the RCD absorption loop circuit; the output end of the starting circuit is connected with the input end of the PWM control loop circuit.

The rectifying and filtering circuit comprises an FR resistance fuse, a sorting bridge stack, a first filtering capacitor, a second winding patch inductor and a third winding patch inductor, wherein a L wire is connected with one end of the FR resistance fuse, the other end of the FR resistance fuse is connected with the sorting bridge stack, an N wire is connected with the sorting bridge stack, the negative electrode of the sorting bridge stack is connected with one end of the third winding patch inductor and the positive electrode of the first filtering capacitor, the other end of the third winding patch inductor is connected with the input end of a starting circuit and the positive electrode of the second filtering capacitor, the negative electrode of the second filtering capacitor is connected with one end of the second winding patch inductor and grounded, the other end of the second winding patch inductor is connected with the positive electrode of the sorting bridge stack and the negative electrode of the first filtering capacitor, the FR resistance fuse is an anti-surge 2KV resistance fuse, and the sorting bridge stack is a patch-type sorting bridge stack.

The model of the second wire wound patch inductor and the model of the third wire wound patch inductor are both CMI322513X100KB-1210-10 uH.

The PWM control loop circuit comprises a PWM control chip and a line loss compensation circuit; a VDD interface of the PWM control chip is connected with the output end of the starting circuit, and a FB interface of the PWM control chip is connected with the line loss compensation circuit; the line loss compensation circuit comprises a sixth resistor and an eighth resistor which are connected in parallel.

The EMC filter circuit comprises an iron core inductance coil, a third capacitor and a fourth capacitor; one end of the iron core inductance coil is respectively connected with one end of the third capacitor and one end of the fourth capacitor and grounded, and the other end of the iron core inductance coil is connected with the other end of the third capacitor; the FB interface of the PWM control chip is connected with the other end of the iron core inductance coil, the drain electrode of the PWM control chip is connected with the other end of the fourth capacitor, the other end of the fourth capacitor is connected with the output end of the RCD absorption loop circuit, and the other end of the iron core inductance coil is connected with the VDD interface of the PWM control chip.

The third capacitor and the fourth capacitor are low-capacity capacitors.

The model of the PWM control chip is OB 2502.

The utility model discloses has positive effect: (1) the utility model discloses can realize 5V 2A's power when than the little 13% space of apple charger 1A 5V. Meanwhile, the energy rate reaches 6, the average efficiency is more than 78.7 percent, and the no-load power consumption is less than 100 mW.

(2) The utility model saves the work die inductance through the second winding chip inductance and the third winding chip inductance, and greatly reduces the circuit design space area; simultaneously can effectively solve the outward conduction and the radiation of CM, DM conduction radiation wave through second wire winding paster inductance and third wire winding paster inductance.

(3) The utility model discloses utilize SMD arrangement bridge rectifier also can reduce circuit space volume to a certain extent, provide technical support for the miniaturization.

(4) The utility model discloses a sixth resistance and eighth resistance among the line loss complementary circuit can be so that output load when the electric current increases, and voltage improves to effectively avoided the charging power that the on-line loss brought to descend, improved the charging speed.

(5) The design of the EMC filter circuit effectively improves the EMC result by bypassing the high-frequency harmonic to the ground through the third capacitor and the fourth capacitor; meanwhile, a Y capacitor is omitted, and technical support is provided for the reduction of the volume of the quick charging head.

(6) The utility model discloses do not have Y electric capacity in primary side and secondary side, insulation resistance is higher, and leakage current is littleer, says safelyr to the human body.

Drawings

In order that the present invention may be more readily and clearly understood, the following detailed description of the present invention is given in conjunction with the accompanying drawings, in which

Fig. 1 is a schematic diagram of the connection of the circuit module of the present invention;

FIG. 2 is a circuit diagram of the present invention;

fig. 3 is a rectifying and filtering circuit according to the present invention;

fig. 4 is a starting circuit of the present invention;

fig. 5 is an RCD absorption loop circuit of the present invention;

FIG. 6 shows a circuit of the PWM control circuit of the present invention;

fig. 7 is a middle synchronous rectification filter circuit of the present invention;

fig. 8 is an EMC filter circuit according to the present invention;

fig. 9 shows an intelligent recognition circuit for a charging protocol in the present invention;

fig. 10 is a voltage drop compensation test chart according to the present invention.

Detailed Description

Referring to fig. 1 to 9, the utility model comprises a rectifying and filtering circuit 1, a starting circuit 2, an RCD absorption loop circuit 3, a transformer 4, a synchronous rectifying and filtering circuit 5, a PWM control loop circuit 6, an EMC filtering circuit 7 and a charging protocol intelligent identification circuit 8; the input end of the rectification filter circuit 1 is connected with a power supply, and the output end of the rectification filter circuit 1 is connected with the input end of the starting circuit 2 and the input end of the RCD absorption loop circuit 3; the output end of the RCD absorption loop circuit 3 is connected with the input end of the transformer 4; the output end of the transformer 4 is connected with the input end of the synchronous rectification filter circuit 5, the output end of the synchronous rectification filter circuit 5 is connected with the input end of the charging protocol intelligent identification circuit 8, and the output end of the charging protocol intelligent identification circuit 8 is connected with the USB; the EMC filter circuit 7 is respectively connected with the PWM control circuit 6 and the RCD absorption circuit 3; the output end of the starting circuit 2 is connected with the input end of the PWM control loop circuit 6.

The rectifying and filtering circuit 1 comprises an FR resistance fuse, a sorting bridge stack BD1, a first filtering capacitor CE1, a second filtering capacitor CE2, a second wire-wound chip inductor L2 and a third wire-wound chip inductor L3, a L wire is connected with one end of the FR resistance fuse, the other end of the FR resistance fuse is connected with a sorting bridge stack BD1, an N wire is connected with a sorting bridge stack BD1, the negative electrode of the sorting bridge stack BD1 is connected with one end of a third wire-wound chip inductor L3 and the positive electrode of the first filtering capacitor CE1, the other end of the third wire-wound chip inductor L3 is connected with the input end of a starting circuit 2 and the positive electrode of the second filtering capacitor CE2, the negative electrode of the second filtering capacitor CE2 is connected with one end of the second wire-wound chip inductor L2 and grounded, the other end of the second wire-wound chip inductor L2 is connected with the positive electrode of the sorting bridge stack BD1 and the negative electrode of the first filtering capacitor CE1, the sorting bridge stack BD 2 is an anti-surge sorting bridge stack BD 2 sorting resistor BD 1.

The models of the second wire wound patch inductor L1 and the third wire wound patch inductor L2 are both CMI322513X100KB-1210-10 uH.

The PWM control loop circuit 6 comprises a PWM control chip U1 and a line loss compensation circuit 61; the model of the PWM control chip U1 is OB 2502; a VDD interface of the PWM control chip U1 is connected with the output end of the starting circuit 2, and a FB interface of the PWM control chip U1 is connected with the line loss compensation circuit 61; the line loss compensation circuit 61 comprises a sixth resistor R6 and an eighth resistor R8 which are connected in parallel; the sixth resistor R6 and the eighth resistor R8 which are connected in parallel are grounded; the CS interface of the PWM control chip U1 is connected to the two resistors R7 and R7A connected in parallel, and the two resistors R7 and R7A connected in parallel are grounded.

The EMC filter circuit 7 comprises a core inductance coil, a third capacitor C3 and a fourth capacitor C4; the third capacitor C3 and the fourth capacitor C4 are low-capacity capacitors; one end of the iron core inductance coil is respectively connected with one end of a third capacitor C3 and one end of a fourth capacitor C4 and is grounded, and the other end of the iron core inductance coil is connected with the other end of the third capacitor C3; the drain of the PWM control chip U1 is connected to the other end of the fourth capacitor C4, the other end of the fourth capacitor C4 is connected to the output end of the RCD absorption loop circuit 3, the sixth resistor R6 and the eighth resistor R8 are connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the other end of the iron core inductor; the other end of the iron core inductance coil is connected with the anode of a sixth diode D6, and the cathode of the sixth diode D6 is connected with the VDD interface of the PWM control chip U1.

The synchronous rectification filter circuit 5 comprises a control chip U2, and the model of the control chip U2 is DK45R 10.

The charging protocol intelligent identification circuit 8 comprises a control chip U3, and the model of the control chip U3 is SOT 23-6. Of course, the model of the control chip U3 can also be CW 3005.

Through the brand new design of the rectifier filter circuit 1 and the EMC filter circuit 7, common-mode-free inductance and Y capacitance are achieved. The volume reduction is really realized in space.

To the utility model discloses carried out functional test, can know through the test, the utility model discloses an electric energy conversion average efficiency is greater than 78.7%, generally can reach more than 79%. In addition the utility model discloses because EMC filter circuit 7's design to avoid Y electric capacity, consequently be 4.8 mu A ~ 5 mu A (being less than 10mA far away) through testing leakage current.

To the utility model discloses a voltage drop compensation test sees figure 10, when charging current increases, can produce great voltage drop on the charging line. In order to improve the charging efficiency, the loss generated on the charging line can be compensated by increasing the output voltage.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The utility model provides a USB intelligence fills circuit soon which characterized in that: the intelligent charging system comprises a rectifying and filtering circuit (1), a starting circuit (2), an RCD absorption loop circuit (3), a transformer (4), a synchronous rectifying and filtering circuit (5), a PWM control loop circuit (6), an EMC filtering circuit (7) and a charging protocol intelligent identification circuit (8); the input end of the rectification filter circuit (1) is connected with a power supply, and the output end of the rectification filter circuit (1) is connected with the input end of the starting circuit (2) and the input end of the RCD absorption loop circuit (3); the output end of the RCD absorption loop circuit (3) is connected with the input end of the transformer (4); the output end of the transformer (4) is connected with the input end of the synchronous rectification filter circuit (5), the output end of the synchronous rectification filter circuit (5) is connected with the input end of the charging protocol intelligent identification circuit (8), and the output end of the charging protocol intelligent identification circuit (8) is connected with the USB; the EMC filter circuit (7) is respectively connected with the PWM control circuit (6) and the RCD absorption circuit (3); the output end of the starting circuit (2) is connected with the input end of the PWM control loop circuit (6).

2. The USB intelligent quick charging circuit according to claim 1, wherein the rectifying and filtering circuit (1) comprises an FR resistance fuse, a trimming bridge stack (BD1), a first filter capacitor (CE1), a second filter capacitor (CE2), a second winding patch inductor (L), and a third winding patch inductor (L), a L wire is connected with one end of the FR resistance fuse, the other end of the FR resistance fuse is connected with the trimming bridge stack (BD1), an N wire is connected with the trimming bridge stack (BD1), a negative electrode of the trimming bridge stack (BD1) is connected with one end of the third winding patch inductor (L) and a positive electrode of the first filter capacitor (CE1), the other end of the third winding patch inductor (L) is connected with an input end of the starting circuit (2), a positive electrode of the second filter capacitor (CE2), a negative electrode of the second winding patch inductor (CE2) is connected with one end of the second winding patch inductor (CE L), and the trimming bridge stack (BD) is connected with a negative electrode of the first winding patch inductor (BD L), and a negative electrode of the trimming bridge stack (BD 638) is connected with a surge resistance fuse (FR 638).

3. The USB intelligent quick charging circuit according to claim 2, wherein the second wire wound patch inductor (L2) and the third wire wound patch inductor (L3) are of the type CMI322513X100KB-1210-10 uH.

4. The USB intelligent quick charging circuit according to claim 2 or 3, wherein: the PWM control loop circuit (6) comprises a PWM control chip (U1) and a line loss compensation circuit (61); a VDD interface of the PWM control chip (U1) is connected with the output end of the starting circuit (2), and a FB interface of the PWM control chip (U1) is connected with the line loss compensation circuit (61); the line loss compensation circuit (61) comprises a sixth resistor (R6) and an eighth resistor (R8) which are connected in parallel.

5. The USB intelligent quick charging circuit according to claim 4, wherein: the EMC filter circuit (7) comprises a core inductance coil, a third capacitor (C3) and a fourth capacitor (C4); one end of the iron core inductance coil is respectively connected with one end of a third capacitor (C3) and one end of a fourth capacitor (C4) and is grounded, and the other end of the iron core inductance coil is connected with the other end of the third capacitor (C3); the FB interface of the PWM control chip (U1) is connected with the other end of the iron core inductance coil, the drain electrode of the PWM control chip (U1) is connected with the other end of the fourth capacitor (C4), the other end of the fourth capacitor (C4) is connected with the output end of the RCD absorption loop circuit (3), and the other end of the iron core inductance coil is connected with the VDD interface of the PWM control chip (U1).

6. The USB intelligent quick charging circuit according to claim 5, wherein: the model of the PWM control chip (U1) is OB 2502.