CN211046480U - Novel overvoltage surge suppressor - Google Patents

Abstract

The utility model discloses a novel excessive pressure surge suppressor, including main control chip circuit, power input circuit, power output circuit, first chip peripheral circuit, second chip peripheral circuit and third chip peripheral circuit, power input circuit is connected with first chip peripheral circuit electricity, first chip peripheral circuit and main control chip circuit all are connected with power output circuit electricity, second chip peripheral circuit and third chip peripheral circuit all are connected with main control chip circuit electricity. The utility model discloses the interference killing feature is strong, power loss is lower, stability is good.

Description

Novel overvoltage surge suppressor

Technical Field

The utility model relates to a switching power supply technical field, in particular to novel excessive pressure surge suppressor.

Background

With the widespread use of computers and other electronic devices, the exposure of electronic devices to overvoltage hazards has attracted a great deal of attention. Circuits often produce high operating overvoltages in the event of lightning strikes and when inductive or large loads are switched on, off, such transient overvoltages (or overcurrents), known as surge voltages (or surge currents), are a type of transient disturbance. Overvoltage surge suppressor is mostly the surge overvoltage suppression to direct current voltage in the existing market, and exchange overvoltage surge suppressor few again, and most surge suppressor adopt overvoltage detection circuit more, when taking place overvoltage surge trouble, the output of cutoff voltage, the cut-off power supply, though protected consumer and avoided the damage of overvoltage phenomenon, can cause equipment to shut down, cause unnecessary trouble for production life. The result of this approach is that the efficiency of the power converter is reduced, and the power converter itself becomes very hot, making the power converter less functional and more costly. Thus, the approach of using a higher peak voltage rating main power switch and a higher peak voltage rating rectifier switch is impractical, and transient voltage spikes and transient voltage surges are extremely harmful to the electronic equipment.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in providing a novel excessive pressure surge suppressor, the interference killing feature is strong, power loss is lower, stability is good.

In order to solve the technical problem, the technical scheme of the utility model is that:

the utility model provides a novel excessive pressure surge suppressor, includes main control chip circuit, power input circuit, power output circuit, first chip peripheral circuit, second chip peripheral circuit and third chip peripheral circuit, power input circuit is connected with first chip peripheral circuit electricity, first chip peripheral circuit and main control chip circuit all are connected with power output circuit electricity, second chip peripheral circuit and third chip peripheral circuit all are connected with main control chip circuit electricity.

Preferably, the power input circuit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C5, and a diode T1, one end of the diode T1, one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the capacitor C4, and one end of the capacitor C5 are all connected to an input power, and the other end of the diode T1, the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4, and the other end of the capacitor C5 are all grounded.

Preferably, the power output circuit comprises a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12 and a capacitor C13, one end of the capacitor C6, one end of the capacitor C7, one end of the capacitor C8, one end of the capacitor C10, one end of the capacitor C11 and one end of the capacitor C12 are all connected with one end of the capacitor C13, and the other end of the capacitor C6, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the capacitor C10, the other end of the capacitor C11, the other end of the capacitor C12 and the other end of the capacitor C13 are all grounded.

Preferably, the main control chip circuit includes a main control chip U1, a resistor R3, a resistor R5, a resistor R6 and a capacitor C18, one end of the resistor R3 and one end of the resistor R5 are both connected to the fourth pin of the main control chip U1, the other end of the resistor R5 and one end of the capacitor C18 are both grounded, the other end of the capacitor C18 is connected to the sixth pin of the main control chip U1, and one end of the resistor R6 is connected to the eighth pin of the main control chip U1.

Preferably, the first chip peripheral circuit includes a resistor R1, a resistor R2, an inductor L, a transistor Q1, a transistor Q2, a diode D1, a capacitor C14, and a capacitor C14, one end of the resistor R14 and a drain of the transistor Q14 are connected to a fifteenth pin of the main control chip U14, the other end of the resistor R14 is connected to a seventeenth pin of the main control chip U14, a gate of the transistor Q14 is connected to a ninth pin of the main control chip U14, a source of the transistor Q14, a drain of the transistor Q14, an anode of the diode D14, one end of the inductor 14 1, and one end of the capacitor C14 are connected to a tenth pin of the main control chip U14, the other end of the capacitor C14 and a cathode of the diode D14 are connected to an eleventh pin of the main control chip U14, and the other end of the inductor 14, one end of the resistor R14, one end of the capacitor C14, and the other end of the resistor R14 are connected to the first pin of the main control chip U14 and the second pin of the capacitor C14.

Preferably, the second chip peripheral circuit includes a capacitor C16, a capacitor C17 and a resistor R4, one end of the capacitor C16 and an eighteenth pin of the main control chip U1 are both connected to a nineteenth pin of the main control chip U1, one end of the capacitor C17 is connected to a fourteenth pin of the main control chip U1, one end of the resistor R4 is connected to a seventh pin of the main control chip U1, and the other end of the capacitor C16, the other end of the capacitor C17 and the other end of the resistor R4 are all grounded.

Adopt above-mentioned technical scheme, the utility model provides a pair of novel excessive pressure surge suppressor, power input circuit in this novel excessive pressure surge suppressor is connected with first chip peripheral circuit electricity, first chip peripheral circuit and main control chip circuit all are connected with power output circuit electricity, second chip peripheral circuit and third chip peripheral circuit all are connected with main control chip circuit electricity, protection to the transient voltage surge through main control chip circuit, when taking place excessive pressure surge trouble, the output of cut-off voltage promotes this novel excessive pressure surge suppressor's interference killing feature greatly, and ensure to function reliably at this in-process, and stability is good.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a schematic circuit diagram of the present invention

In the figure, 1-power input circuit, 2-first chip peripheral circuit, 3-main control chip circuit, 4-power output circuit, 5-second chip peripheral circuit and 6-third chip peripheral circuit.

Detailed Description

The following describes the present invention with reference to the accompanying drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features related to the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

As shown in fig. 1, the structure diagram of the utility model discloses an among this novel excessive pressure surge suppressor, this novel excessive pressure surge suppressor includes main control chip circuit, power input circuit 1, first chip peripheral circuit 2, main control chip circuit 3, power output circuit 4, second chip peripheral circuit 5 and third chip peripheral circuit 6, this power input circuit 1 is connected with first chip peripheral circuit 2 electricity, this first chip peripheral circuit 2 and main control chip circuit 3 all are connected with power output circuit 4 electricity, this second chip peripheral circuit 5 and third chip peripheral circuit 6 all are connected with main control chip circuit 3 electricity. It can be understood that, the power input circuit 1 is connected to an input power, and enters the main control chip circuit 3 through the first chip peripheral circuit 2, and when the main control chip circuit 3 is subjected to a high-energy transient overvoltage pulse under a specified reverse application condition, the working impedance thereof can be immediately reduced to a very low value to allow a large current to pass through, and the voltage is clamped at a predetermined level and is output through the power output circuit 4, thereby effectively protecting precise components in an electronic product from being damaged.

Specifically, fig. 2 is a circuit schematic diagram of the present invention, with reference to fig. 1 and 2, the power input circuit 1 includes a capacitor C, and a diode T, one end of the capacitor C, and one end of the capacitor C are all connected to an input power source, the other end of the diode T, the other end of the capacitor C, and the other end of the capacitor C are all grounded, the main control chip circuit 3 includes a main control chip U, a resistor R, and a capacitor C, one end of the resistor R and one end of the main control chip U are all connected to a fourth pin of the main control chip U, the other end of the resistor R and one end of the capacitor C are all grounded, one end of the capacitor C, a resistor Q, the other end of the main control chip C is connected to a sixth pin of the main control chip U, one end of the main control chip U, the capacitor C is connected to a resistor C, a resistor C is connected to a resistor C.

It can be understood, the utility model relates to a rationally, the structure is unique, through main control chip circuit 3 control power input circuit 1 respectively, first chip peripheral circuit 2, power output circuit 4, second chip peripheral circuit 5 and third chip peripheral circuit 6 processing input power, thereby restrain instantaneous voltage peak and instantaneous voltage surge, not only be favorable to releasing rapidly of surge voltage, prevent that surge voltage from causing the impact to the consumer, reach the purpose of protection consumer, make consumption greatly reduced moreover, power loss is lower. In addition, the novel overvoltage surge suppressor has small leakage current, so the novel overvoltage surge suppressor has small influence on a line.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made in the embodiments without departing from the principles and spirit of the invention, and the scope of the invention is to be accorded the full scope of the claims.

Claims (6)

1. A novel overvoltage surge suppressor is characterized in that: the power supply comprises a main control chip circuit, a power input circuit, a power output circuit, a first chip peripheral circuit, a second chip peripheral circuit and a third chip peripheral circuit, wherein the power input circuit is electrically connected with the first chip peripheral circuit, the first chip peripheral circuit and the main control chip circuit are electrically connected with the power output circuit, and the second chip peripheral circuit and the third chip peripheral circuit are electrically connected with the main control chip circuit.

2. The novel overvoltage surge suppressor of claim 1, wherein: the power input circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C5 and a diode T1, one end of the diode T1, one end of the capacitor C1, one end of the capacitor C2, one end of the capacitor C3, one end of the capacitor C4 and one end of the capacitor C5 are all connected with an input power supply, and the other end of the diode T1, the other end of the capacitor C1, the other end of the capacitor C2, the other end of the capacitor C3, the other end of the capacitor C4 and the other end of the capacitor C5 are all grounded.

3. The novel overvoltage surge suppressor of claim 1, wherein: the power output circuit comprises a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12 and a capacitor C13, wherein one end of the capacitor C6, one end of the capacitor C7, one end of the capacitor C8, one end of the capacitor C10, one end of the capacitor C11 and one end of the capacitor C12 are all connected with one end of the capacitor C13, and the other end of the capacitor C6, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the capacitor C10, the other end of the capacitor C11, the other end of the capacitor C12 and the other end of the capacitor C13 are all grounded.

4. The novel overvoltage surge suppressor of claim 1, wherein: the main control chip circuit comprises a main control chip U1, a resistor R3, a resistor R5, a resistor R6 and a capacitor C18, one end of the resistor R3 and one end of the resistor R5 are connected with a fourth pin of the main control chip U1, the other end of the resistor R5 and one end of the capacitor C18 are grounded, the other end of the capacitor C18 is connected with a sixth pin of the main control chip U1, and one end of the resistor R6 is connected with an eighth pin of the main control chip U1.

5. The novel overvoltage surge suppressor according to claim 4, wherein the first chip peripheral circuit comprises a resistor R1, a resistor R2, an inductor L, a transistor Q1, a transistor Q2, a diode D1, a capacitor C14 and a capacitor C14, one end of the resistor R14 and a drain of the transistor Q14 are connected with a fifteenth pin of the main control chip U14, the other end of the resistor R14 is connected with a seventeenth pin of the main control chip U14, a gate of the transistor Q14 is connected with a ninth pin of the main control chip U14, a source of the transistor Q14, a drain of the transistor Q14, an anode of the diode D14, one end of the inductor 14 and one end of the capacitor C14 are connected with the tenth pin of the main control chip U14, the other end of the capacitor C14 and a cathode of the diode D14 are connected with the eleventh pin of the main control chip U14, and the other end of the inductor R14, one end of the resistor R14 and one end of the capacitor C14 are connected with the first pin of the capacitor C14 and the other end of the capacitor R14 are connected with the first pin of the main control chip U14.

6. The novel overvoltage surge suppressor of claim 4, wherein: the second chip peripheral circuit comprises a capacitor C16, a capacitor C17 and a resistor R4, wherein one end of the capacitor C16 and an eighteenth pin of the main control chip U1 are connected with a nineteenth pin of the main control chip U1, one end of the capacitor C17 is connected with a fourteenth pin of the main control chip U1, one end of the resistor R4 is connected with a seventh pin of the main control chip U1, and the other end of the capacitor C16, the other end of the capacitor C17 and the other end of the resistor R4 are all grounded.

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