CN211043578U - Semiconductor test box with temperature control function - Google Patents
Semiconductor test box with temperature control function Download PDFInfo
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- CN211043578U CN211043578U CN201921648858.3U CN201921648858U CN211043578U CN 211043578 U CN211043578 U CN 211043578U CN 201921648858 U CN201921648858 U CN 201921648858U CN 211043578 U CN211043578 U CN 211043578U
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Abstract
The utility model discloses a semiconductor test box with temperature control function, which comprises a chip clamp, a test board, a drive circuit board and a battery, wherein the chip clamp, the test board, the drive circuit board and the battery are arranged in a box body; the box body positioned at the side of the driving cavity is provided with a plurality of fans, and the box body is also provided with air holes corresponding to the fans. The utility model discloses it passes through baffle separation test area territory and drive area territory, fan and wind hole in hot plate and heating panel, the drive chamber in the cooperation test chamber for the test box can realize the subregion accuse temperature, avoids the heat that each components and parts produced to influence each other, thereby stabilizes the test temperature, improves the measuring accuracy, simultaneously, can also protect drive components and parts increase of service life.
Description
Technical Field
The utility model relates to a semiconductor test box with control by temperature change function belongs to chip test technical field.
Background
The quality and reliability determine the service life of a chip product to a certain extent, and in order to ensure the reliability of the chip product, an aging test is often required to detect the chip after the chip is manufactured, wherein the aging test of the chip is an electrical stress test method for accelerating electrical faults of devices by adopting voltage and high temperature, and the aging test simulates the whole service life of the chip so as to expose the defects in the chip as early as possible; in the testing process, even if a certain temperature environment is provided for the tested chip to finish the testing work, then the tested chip, the testing component, the battery and other components can generate heat when being electrified, the temperature environment provided in advance is influenced, the temperature fluctuates, and the testing precision of the chip is influenced.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a semiconductor test box with control by temperature change function, this semiconductor test box have solved in the chip testing process, and test environment temperature produces undulantly, leads to the problem that the measuring accuracy descends.
In order to achieve the above purpose, the utility model adopts the technical scheme that: a semiconductor test box with a temperature control function comprises a chip clamp, a test board, a driving circuit board and a battery which are arranged in a box body, wherein a partition board is arranged in the box body and divides the space in the box body into a test cavity and a driving cavity;
the chip clamp comprises a heating plate, a chip carrier plate and a chip circuit board, wherein the chip carrier plate is arranged on the heating plate and is provided with a chip groove for embedding a chip, the chip circuit board is arranged on the chip carrier plate and is provided with a chip probe electrically connected with the chip, and the chip circuit board is also provided with an external contact point electrically connected with the chip probe;
the test board is provided with a plurality of clamp grooves, the chip clamps are embedded in the clamp grooves, an integrated circuit board is mounted on the test board, the integrated circuit board is provided with integrated probes electrically connected with external contacts and a test plug electrically connected with the integrated probes, and the test plug is connected with the drive circuit board;
the test board is provided with a cavity communicated with the outside, the clamp groove is communicated with the cavity, a heat dissipation plate corresponding to the clamp groove is arranged in the cavity, and the heating plate is arranged on the heat dissipation plate;
the box body positioned at the side of the driving cavity is provided with a plurality of fans, and the box body is also provided with air holes corresponding to the fans.
The further improved scheme in the technical scheme is as follows:
1. in the scheme, a battery plate is installed in the heating plate.
2. In the above scheme, the number of the test boards and the number of the driving circuit boards are 4, and the test boards correspond to the driving circuit boards one to one.
3. In the above scheme, the heat dissipation plate is a heat dissipation fin.
4. In the above scheme, the fan is located on one side of the driving circuit board, which is far away from the test cavity.
5. In the above scheme, the driving circuit board is installed in the box body through the bracket, and a gap is reserved between the driving circuit board and the inner wall of the box body.
Because of above-mentioned technical scheme's application, compared with the prior art, the utility model have the following advantage:
the utility model discloses semiconductor test box with control by temperature change function, it passes through baffle separation test area territory and drive area territory, and fan and wind hole in hot plate and heating panel, the drive chamber in the cooperation test chamber for the test box can realize the subregion accuse temperature, avoids the heat that each components and parts produced to influence each other, thereby stabilizes the test temperature, improves the measuring accuracy, simultaneously, can also protect drive components and parts, increase of service life.
Drawings
FIG. 1 is a schematic view of the overall structure of the semiconductor test box with temperature control function of the present invention;
FIG. 2 is a schematic view of a test board;
FIG. 3 is a schematic structural view of a cavity portion;
FIG. 4 is a schematic view of a chip holder;
FIG. 5 is a schematic view of another view of the chip holder.
In the above drawings: 1. a box body; 11. a partition plate; 12. a test chamber; 13. a drive chamber; 2. a chip clamp; 21. heating plates; 22. a chip carrier plate; 221. a chip slot; 23. a chip circuit board; 231. A chip probe; 232. an outer contact point; 3. a test board; 31. a clamp groove; 32. an integrated circuit board; 321. integrating the probe; 322. testing the plug; 33. a cavity; 34. a heat dissipation plate; 4. a drive circuit board; 5. a battery; 9. a fan; 91. and (4) air holes.
Detailed Description
In the description of this patent, it is noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention; the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, as they may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The meaning of the above terms in this patent may be specifically understood by those of ordinary skill in the art.
Example 1: a semiconductor test box with a temperature control function refers to the attached figures 1-5, and comprises a chip clamp 2, a test board 3, a driving circuit board 4 and a battery 5 which are arranged in a box body 1, wherein a partition plate 11 is arranged in the box body 1, the space in the box body 1 is divided into a test cavity 12 and a driving cavity 13 by the partition plate 11, the chip clamp 2 and the test board 3 are arranged in the test cavity 12, and the driving circuit board 4 and the battery 5 are arranged in the driving cavity 13;
the chip clamp 2 comprises a heating plate 21, a chip carrier plate 22 and a chip circuit board 23, wherein the chip carrier plate 22 is mounted on the heating plate 21 and provided with a chip slot 221 for embedding a chip, the chip circuit board 23 is mounted on the chip carrier plate 22 and provided with a chip probe 231 electrically connected with the chip, and the chip circuit board 23 is also provided with an external contact point 232 electrically connected with the chip probe 231;
the test board 3 is provided with a plurality of clamp grooves 31, the chip clamps 2 are embedded in the clamp grooves 31, the test board 3 is provided with an integrated circuit board 32, the integrated circuit board 32 is provided with integrated probes 321 electrically connected with the outer contact points 232 and test plugs 322 electrically connected with the integrated probes 321, and the test plugs 322 are connected with the drive circuit board 4;
the test board 3 is provided with a cavity 33 communicated with the outside, the clamp groove 31 is communicated with the cavity 33, a heat dissipation plate 34 corresponding to the clamp groove 31 is arranged in the cavity 33, and the heating plate 21 is arranged on the heat dissipation plate 34;
the box body 1 on the side of the driving cavity 13 is provided with a plurality of fans 9, and the box body 1 is also provided with air holes 91 corresponding to the fans 9.
A battery plate is arranged in the heating plate 21; the number of the test boards 3 and the number of the drive circuit boards 4 are 4, and the test boards 3 correspond to the drive circuit boards 4 one by one; the heat dissipation plate 34 is a heat dissipation fin.
The fan 9 is positioned on one side of the drive circuit board 4 far away from the test chamber 12; the driving circuit board 4 is installed in the box body 1 through a bracket, and a gap is reserved between the driving circuit board 4 and the inner wall of the box body 1.
Example 2: a semiconductor test box with a temperature control function refers to the attached figures 1-5, and comprises a chip clamp 2, a test board 3, a driving circuit board 4 and a battery 5 which are arranged in a box body 1, wherein a partition plate 11 is arranged in the box body 1, the space in the box body 1 is divided into a test cavity 12 and a driving cavity 13 by the partition plate 11, the chip clamp 2 and the test board 3 are arranged in the test cavity 12, and the driving circuit board 4 and the battery 5 are arranged in the driving cavity 13;
the chip clamp 2 comprises a heating plate 21, a chip carrier plate 22 and a chip circuit board 23, wherein the chip carrier plate 22 is mounted on the heating plate 21 and provided with a chip slot 221 for embedding a chip, the chip circuit board 23 is mounted on the chip carrier plate 22 and provided with a chip probe 231 electrically connected with the chip, and the chip circuit board 23 is also provided with an external contact point 232 electrically connected with the chip probe 231;
the test board 3 is provided with a plurality of clamp grooves 31, the chip clamps 2 are embedded in the clamp grooves 31, the test board 3 is provided with an integrated circuit board 32, the integrated circuit board 32 is provided with integrated probes 321 electrically connected with the outer contact points 232 and test plugs 322 electrically connected with the integrated probes 321, and the test plugs 322 are connected with the drive circuit board 4;
the test board 3 is provided with a cavity 33 communicated with the outside, the clamp groove 31 is communicated with the cavity 33, a heat dissipation plate 34 corresponding to the clamp groove 31 is arranged in the cavity 33, and the heating plate 21 is arranged on the heat dissipation plate 34;
the box body 1 on the side of the driving cavity 13 is provided with a plurality of fans 9, and the box body 1 is also provided with air holes 91 corresponding to the fans 9.
A battery plate is arranged in the heating plate 21; the number of the test boards 3 and the number of the drive circuit boards 4 are 4, and the test boards 3 correspond to the drive circuit boards 4 one by one; the heat dissipation plate 34 is a heat dissipation fin.
When the semiconductor test box with the temperature control function is adopted, the test box is separated from the drive area through the partition plate, the heating plate in the test cavity is matched with the fan and the air hole in the heating plate, the heating plate and the air hole in the drive cavity, so that the test box can realize partition temperature control, the heat generated by each component is prevented from influencing each other, the test temperature is stabilized, the test precision is improved, meanwhile, the drive component can be protected, and the service life is prolonged.
The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose of the embodiments is to enable people skilled in the art to understand the contents of the present invention and to implement the present invention, which cannot limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered by the protection scope of the present invention.
Claims (6)
1. The utility model provides a semiconductor test box with control by temperature change function which characterized in that: the device comprises a chip clamp (2), a test board (3), a driving circuit board (4) and a battery (5) which are arranged in a box body (1), wherein a partition board (11) is arranged in the box body (1), the space in the box body (1) is divided into a test cavity (12) and a driving cavity (13) by the partition board (11), the chip clamp (2) and the test board (3) are arranged in the test cavity (12), and the driving circuit board (4) and the battery (5) are arranged in the driving cavity (13);
the chip clamp (2) comprises a heating plate (21), a chip carrier plate (22) and a chip circuit board (23), wherein the chip carrier plate (22) is arranged on the heating plate (21) and is provided with a chip groove (221) for embedding a chip, the chip circuit board (23) is arranged on the chip carrier plate (22) and is provided with a chip probe (231) electrically connected with the chip, and the chip circuit board (23) is also provided with an outer contact point (232) electrically connected with the chip probe (231);
the testing board (3) is provided with a plurality of clamp grooves (31), the chip clamps (2) are embedded in the clamp grooves (31), the testing board (3) is provided with an integrated circuit board (32), the integrated circuit board (32) is provided with integrated probes (321) electrically connected with the outer contact points (232) and testing plugs (322) electrically connected with the integrated probes (321), and the testing plugs (322) are connected with the driving circuit board (4);
the test board (3) is internally provided with a cavity (33) communicated with the outside, the clamp groove (31) is communicated with the cavity (33), a heat dissipation plate (34) corresponding to the clamp groove (31) is arranged in the cavity (33), and the heating board (21) is arranged on the heat dissipation plate (34);
a plurality of fans (9) are installed on the box body (1) located on the side of the driving cavity (13), and air holes (91) corresponding to the fans (9) are further formed in the box body (1).
2. The semiconductor test box with temperature control function of claim 1, wherein: the heating plate (21) is internally provided with a battery plate.
3. The semiconductor test box with temperature control function of claim 1, wherein: the number of the test boards (3) and the number of the drive circuit boards (4) are 4, and the test boards (3) correspond to the drive circuit boards (4) one by one.
4. The semiconductor test box with temperature control function of claim 1, wherein: the heat dissipation plate (34) is a heat dissipation fin.
5. The semiconductor test box with temperature control function of claim 1, wherein: the fan (9) is positioned on one side of the driving circuit board (4) far away from the testing cavity (12).
6. The semiconductor test box with temperature control function of claim 1, wherein: the driving circuit board (4) is arranged in the box body (1) through a support, and a gap is reserved between the driving circuit board (4) and the inner wall of the box body (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921648858.3U CN211043578U (en) | 2019-09-30 | 2019-09-30 | Semiconductor test box with temperature control function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921648858.3U CN211043578U (en) | 2019-09-30 | 2019-09-30 | Semiconductor test box with temperature control function |
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| Publication Number | Publication Date |
|---|---|
| CN211043578U true CN211043578U (en) | 2020-07-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921648858.3U Active CN211043578U (en) | 2019-09-30 | 2019-09-30 | Semiconductor test box with temperature control function |
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| CN (1) | CN211043578U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114324457A (en) * | 2021-12-22 | 2022-04-12 | 惠州锂威新能源科技有限公司 | Battery material testing system and method |
-
2019
- 2019-09-30 CN CN201921648858.3U patent/CN211043578U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114324457A (en) * | 2021-12-22 | 2022-04-12 | 惠州锂威新能源科技有限公司 | Battery material testing system and method |
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Address after: Building 5, No. 1508, Xiangjiang Road, Suzhou High-tech Zone, Suzhou City, Jiangsu Province 215129 Patentee after: Suzhou Lianxun Instrument Co.,Ltd. Address before: 215011 Building 5, no.1508 Xiangjiang Road, high tech Zone, Suzhou City, Jiangsu Province Patentee before: STELIGHT INSTRUMENT Inc. |