CN211019039U

CN211019039U - Audio and video synchronization circuit

Info

Publication number: CN211019039U
Application number: CN202020134958.0U
Authority: CN
Inventors: 占杰; 邹伟华; 李伟
Original assignee: WELLAV TECHNOLOGIES Ltd
Current assignee: WELLAV TECHNOLOGIES Ltd
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2020-07-14
Anticipated expiration: 2030-01-21

Abstract

The application relates to an audio and video synchronization circuit, which comprises a ZYNQ module, an FPGA chip, a PCM catcher and a timer, wherein the PCM catcher is connected with the FPGA chip, and the timer is arranged in the FPGA chip; the Haesi processing module comprises a Haesi chip, and a video encoder and a Muxer multiplexer are arranged in the Haesi chip; the Haesi chip is connected with the FPGA chip and is used for acquiring an audio coding frame of the ZYNQ module and sending a PCR value to the FPGA chip; the timer arranged in the FPGA chip is used for storing a PCR value; the ZYNQ module and the Haisi processing module are synchronized through PCR values. The beneficial effects are that: the synchronous output of the audio data of the ZYNQ module and the video data of the Haisi processing module is realized, and a good audio-visual effect is achieved.

Description

Audio and video synchronization circuit

Technical Field

The application relates to the technical field of data processing, in particular to an audio and video synchronization circuit.

Background

The audio and video synchronization control is a research hotspot in the field of video conferences, and whether the audio and video synchronization is carried out or not has great influence on the experience of the video conferences. At present, a plurality of schemes for solving the problem of audio and video asynchronism exist, such as a multiplexing method (audio and video frame packing transmission), a synchronization marking method (marking the relevant audio and video frames and playing according to the labels during playing) and the like.

Regarding that audio and video coding is completed under two different systems, the audio and video coding involves an audio and video synchronization scheme processing, even if clocks under the two systems are both 27MHz, because the two clocks are not homologous, the deviation value of the two clocks will become larger along with the longer running time of the system, and finally the audio and video are out of synchronization.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, the present application provides an audio and video synchronization circuit, which includes

The ZYNQ module comprises an FPGA chip, a PCM catcher and a timer, wherein the PCM catcher is connected with the FPGA chip, and the timer is arranged in the FPGA chip;

the Haesi processing module comprises a Haesi chip, and a video encoder and a Muxer multiplexer are arranged in the Haesi chip;

the Haesi chip is connected with the FPGA chip and is used for acquiring an audio coding frame of the ZYNQ module and sending a PCR value to the FPGA chip; the timer arranged in the FPGA chip is used for storing a PCR value; the ZYNQ module and the Haisi processing module are synchronized through PCR values.

Optionally, an audio encoder is further arranged between the FPGA chip and the haisi chip, and the audio encoder is arranged in the ZYNQ module; the audio encoder acquires PCM data through connection with the PCM capturer and compression encodes the PCM data; the audio encoder is connected with the timer to obtain an audio frame PTS, and the output end of the audio encoder is connected with the Haisi chip and outputs an audio encoding frame to the Haisi chip.

Optionally, the Muxer multiplexer is connected to the video encoder, and the Muxer multiplexer is disposed at an interface of the haisi chip and connected to the audio encoder; the Muxer multiplexer integrates a video frame PTS of a video encoder and an audio frame PTS of an audio encoder, and performs synchronous output.

Optionally, the FPGA chip model is XC7Z010-1C L G484C.

Optionally, the PCM trap includes a PCM chip, the PCM chip is provided with a connection end and a communication end, the communication end is connected with the FPGA chip through a resistor, and a capacitor is further connected between the connection end and the external VGA interface.

Optionally, the PCM chip model is PCM 1864.

Optionally, the system further comprises a 27MHZ oscillator, the power supply input end of the 27MHZ oscillator further comprises at least one filter capacitor, and the output end of the 27MHZ oscillator is connected with a timer arranged in the FPGA.

Optionally, the haisi chip model is a HI3521AV100 chip.

According to the audio and video synchronization circuit, the Haesi processing module is connected with the ZYNQ module, and the Haesi chip is used for acquiring an audio coding frame of the ZYNQ module and sending a PCR value and a video frame PTS to the FPGA chip; the timer arranged in the FPGA chip is used for storing the PCR value; and the ZYNQ module and the Haisi processing module are synchronized through PCR values. The beneficial effects are that: the synchronous output of the audio data of the ZYNQ module and the video data of the Haisi processing module is realized, and a good audio-visual effect is achieved.

Drawings

Fig. 1 is a schematic diagram of the present circuit according to an embodiment of the present application.

Fig. 2 is a schematic diagram of an FPGA chip according to an embodiment of the present application.

Fig. 3 is a schematic diagram of a haisi chip according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a PCM chip according to an embodiment of the present application.

FIG. 5 is a schematic diagram of a 27MHz oscillator according to an embodiment of the application.

Detailed Description

The following detailed description of the preferred embodiments of the present application, taken in conjunction with the accompanying drawings, will make the advantages and features of the present application more readily appreciated by those skilled in the art, and thus will more clearly define the scope of the invention.

In an embodiment as shown in fig. 1-5, the present application provides an audio-video synchronization circuit comprising

The ZYNQ module comprises an FPGA chip U1, a PCM catcher and a timer, wherein the PCM catcher is connected with the FPGA chip U1, and the timer is arranged in the FPGA chip U1;

the Haesi processing module comprises a Haesi chip U2, and a video encoder and a Muxer multiplexer are arranged in the Haesi chip U2;

the Haisi chip U2 is connected with the FPGA chip U1, and the Haisi chip U2 is used for acquiring an audio coding frame of the ZYNQ module and sending a PCR value to the FPGA chip U1; the timer arranged in the FPGA chip U1 is used for storing the PCR value; and the ZYNQ module and the Haisi processing module are synchronized through PCR values.

In this embodiment, the FPGA chip U1, the PCM catcher, and the timer are disposed in the ZYNQ system, the PCM catcher is in communication connection with the FPGA chip U1, and the timer is further disposed in the FPGA chip U1; and the Haas chip U2 of the Haas processing module is used for the Muxer multiplexing of video coding and audio and video through a video coder and the Muxer multiplexing. The PCR value of the audio encoder synchronous Haisi chip U2 through the FPGA is synchronized, and in order to obtain the accurate PCR value of the Haisi chip U2, the error caused by the PTS of the individual video frame is reduced, and the error can be obtained by adopting the average value of the PTS of the video frame. Monitoring a frame after video coding, simultaneously acquiring corresponding video frame PTS, counting values of real-time continuous 8 video frame PTS, and calculating the average value to obtain a synchronous PCR value. Then, the Zynq module initiates a PCR acquisition request frame to a Muxer multiplexer of the Haisi chip U2 within a certain time, the Zynq module acquires that a PCR value is set in a timer of the FPGA chip U1, and the timer module recalculates the audio frame PTS of the audio encoder. The synchronous output of the audio PTS of the ZYNQ module and the video PTS of the Haisi processing module is realized, and a good audio-visual effect is achieved.

In an implementation manner of the above embodiment, an audio encoder is further disposed between the FPGA chip U1 and the haisi chip U2, and the audio encoder is disposed in the ZYNQ module; the audio encoder acquires PCM data through connecting with the PCM capturer and performs compression coding on the PCM data; the audio encoder is connected with the timer to obtain the audio frame PTS, and the output end of the audio encoder is connected with the Haisi chip U2 and outputs the audio encoding frame to the Haisi chip U2. The Muxer multiplexer is connected with the video encoder, and is arranged on an interface of the Haisi chip U2 and connected with the audio encoder; the Muxer multiplexer integrates a video frame PTS of a video encoder and an audio frame PTS of an audio encoder, and synchronously outputs. In this embodiment, the audio encoder of the ZYNQ module initiates a PCR acquisition request to the Muxer multiplexer of the haisi chip U2 every 3 minutes, and the haisi chip U2 sends back the synchronized PCR value to the audio encoder of the ZYNQ module; the audio encoder writes the obtained PCR value to a timer of the FPGA chip U1 through a register; the audio encoder counts the PTS value of the audio frame again and gives the PTS value to the PCM capturer, the FPGA chip U1 obtains the audio PCM, and simultaneously, the current timer, namely the audio frame PTS, is synchronously written into a latch register; the audio encoder captures PCM data by the PCM capturer for compression encoding, binds corresponding audio frame PTS at the same time, and then sends the PCM data to a Muxer multiplexer of a Haisi chip U2, and the Muxer multiplexer acquires ES and PTS of the integrated video encoder and ES and PTS of the audio encoder and multiplexes the ES and PTS into TS output. And synchronous output of the audio PTS of the ZYNQ module and the video PTS of the Haisi processing module is realized.

In some embodiments, the FPGA chip U1 may be a model XC7Z010-1C L G484C chip.

In some embodiments, the PCM trap includes a PCM chip U3, the PCM chip U3 is provided with a connection terminal and a communication terminal, the communication terminal is connected to the FPGA chip U1 through a resistor, and a capacitor is further connected between the connection terminal and the external VGA interface. In this embodiment, the PCM chip model may be PCM 1864.

In some embodiments, the system further comprises a 27MHZ oscillator OSC, the power supply input of the 27MHZ oscillator OSC further comprises at least one filter capacitor for filtering noise, and the output of the 27MHZ oscillator OSC is connected to a timer provided in the FPGA. The 27MHZ oscillator OSC provides a clock signal to the timer.

In some embodiments, Haesi chip U2 is a HI3521AV100 chip.

According to the audio and video synchronization circuit, the Haesi processing module is connected with the ZYNQ module, and the Haesi chip U2 is used for acquiring an audio coding frame of the ZYNQ module and sending a PCR value and a video frame PTS to the FPGA chip U1; the timer arranged in the FPGA chip U1 is used for storing the PCR value; and the ZYNQ module and the Haisi processing module are synchronized through PCR values. The synchronous output of the audio PTS of the ZYNQ module and the video PTS of the Haisi processing module is realized, and a good audio-visual effect is achieved.

In the description of the embodiments of the present application, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the exemplary embodiments of the present application, and are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An audio and video synchronization circuit is characterized by comprising

2. The audio and video synchronization circuit according to claim 1, wherein an audio encoder is further disposed between the FPGA chip and the haisi chip, and the audio encoder is disposed in the ZYNQ module; the audio encoder acquires PCM data through connection with the PCM capturer and compression encodes the PCM data; the audio encoder is connected with the timer to obtain an audio frame PTS, and the output end of the audio encoder is connected with the Haisi chip and outputs an audio encoding frame to the Haisi chip.

3. The audio-video synchronization circuit according to claim 2, wherein the Muxer multiplexer is connected to the video encoder, and the Muxer multiplexer is disposed at an interface of the haisi chip and connected to the audio encoder; the Muxer multiplexer integrates a video frame PTS of a video encoder and an audio frame PTS of an audio encoder, and performs synchronous output.

4. The audio-video synchronization circuit according to claim 1, wherein the FPGA chip has a model of XC7Z010-1C L G484C.

5. The audio and video synchronization circuit of claim 1, wherein the PCM capturer comprises a PCM chip, the PCM chip is provided with a connecting end and a communication end, the communication end is connected with the FPGA chip through a resistor, and a capacitor is further connected between the connecting end and an external VGA interface.

6. The audio-video synchronization circuit as claimed in claim 5, wherein the PCM chip model is PCM 1864.

7. The audio-video synchronization circuit according to claim 1, further comprising a 27MHZ oscillator, wherein the power input terminal of the 27MHZ oscillator further comprises at least one filter capacitor, and the output terminal of the 27MHZ oscillator is connected to a timer disposed in the FPGA.

8. The audio-video synchronization circuit of claim 1, wherein the Haesi chip is a HI3521AV100 chip.