CN211018784U - Time delay circuit and electronic device - Google Patents
Time delay circuit and electronic device Download PDFInfo
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- CN211018784U CN211018784U CN201922293780.4U CN201922293780U CN211018784U CN 211018784 U CN211018784 U CN 211018784U CN 201922293780 U CN201922293780 U CN 201922293780U CN 211018784 U CN211018784 U CN 211018784U
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Abstract
The utility model provides a delay circuit and electronic equipment, the delay circuit includes first triode, second triode, third triode, first diode and first electric capacity; the emitter of the first triode is connected with a power supply, the base of the first triode is respectively connected with the anode of the first diode and the base of the second triode, and the collector of the first triode is connected with the collector of the second triode; the cathode of the first diode is respectively connected with the first end of the first capacitor and the emitter of the second triode, and the second end of the first capacitor is grounded; the emitter of the second triode is connected with the base of the first triode, and the collector of the second triode is connected with the base of the third triode; and an emitting electrode of the third triode is grounded, and a collecting electrode of the third triode is respectively connected with the control system and the chip. The utility model discloses an above-mentioned configuration realizes going up the electric time delay when last power-on, realizes falling the electric time delay when falling the power failure, guarantees electronic equipment at last power-on in the twinkling of an eye and fall the electric safety in the twinkling of an eye.
Description
Technical Field
The utility model relates to the technical field of circuits, especially, relate to a delay circuit and electronic equipment.
Background
At present, in the moment of power-on or power-off of many electronic devices, due to lack of corresponding protection circuits, the devices are powered on too fast or discharged too fast, which easily causes damage or failure of the electronic devices. For example, when audio equipment such as a sound box and a microphone is powered on or powered off, noise is easy to appear; when the display equipment such as a television, a liquid crystal display screen and the like is powered on or powered off, the display screen is easy to be turned; some high-power devices may cause damage to internal circuits when suddenly powered on or powered off, thereby causing damage to the devices.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at provides a delay circuit and electronic equipment, aims at solving current electronic equipment and at last electric or fall the power failure in the twinkling of an eye, the technical problem who breaks down easily.
In order to achieve the above object, the present invention provides a delay circuit and an electronic device, wherein the delay circuit comprises a first triode, a second triode, a third triode, a first diode and a first capacitor;
an emitting electrode of the first triode is connected with a power supply, a base electrode of the first triode is respectively connected with an anode of the first diode and a base electrode of the second triode, and a collector electrode of the first triode is connected with a collector electrode of the second triode;
the cathode of the first diode is respectively connected with the first end of the first capacitor and the emitter of the second triode, and the second end of the first capacitor is grounded;
the emitter of the second triode is also connected with the base of the first triode, and the collector of the second triode is connected with the base of the third triode;
and the emitter of the third triode is grounded, and the collector of the third triode is respectively connected with the control system and the chip.
Optionally, the delay circuit further comprises a first resistor;
the first end of the first resistor is respectively connected with the power supply and the emitting electrode of the first triode, and the second end of the first resistor is grounded.
Optionally, the delay circuit further comprises a second resistor;
the first end of the second resistor is respectively connected with the emitting electrode of the first triode and the first end of the first resistor, and the second end of the second resistor is connected with the base electrode of the first triode.
Optionally, the delay circuit further comprises a third resistor;
and the first end of the third resistor is respectively connected with the second end of the second resistor and the anode of the first diode, and the second end of the third resistor is connected with the base of the second triode.
Optionally, the delay circuit further comprises a fourth resistor;
and a first end of the fourth resistor is respectively connected with an emitter of the second triode and a cathode of the first diode, and a second end of the fourth resistor is connected with a first end of the first capacitor.
Optionally, the delay circuit further comprises a fifth resistor;
and the first end of the fifth resistor is respectively connected with the collector electrode of the first triode and the collector electrode of the second triode, and the second end of the fifth resistor is connected with the base electrode of the third triode.
Optionally, the delay circuit further comprises a sixth resistor;
and the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is grounded.
Optionally, the delay circuit further includes a seventh resistor;
and the first end of the seventh resistor is connected with the control system, and the second end of the seventh resistor is respectively connected with the collector of the third triode and the chip.
Optionally, the delay circuit further comprises a second capacitor;
the first end of the second capacitor is connected with the chip, and the second end of the second capacitor is grounded.
Further, in order to achieve the above object, the present invention provides an electronic device including a delay circuit configured as the delay circuit described above.
The utility model provides a delay circuit and electronic equipment, the delay circuit includes first triode, second triode, third triode, first diode and first electric capacity; the emitter of the first triode is connected with a power supply, the base of the first triode is respectively connected with the anode of the first diode and the base of the second triode, and the collector of the first triode is connected with the collector of the second triode; the cathode of the first diode is respectively connected with the first end of the first capacitor and the emitter of the second triode, and the second end of the first capacitor is grounded; the emitter of the second triode is also connected with the base of the first triode, and the collector of the second triode is connected with the base of the third triode; and an emitting electrode of the third triode is grounded, and a collecting electrode of the third triode is respectively connected with the control system and the chip.
When the time delay circuit is powered on, the power supply charges the first capacitor through the first diode, the output voltage is transmitted to the first triode to enable the first triode to be conducted, the corresponding third triode is conducted to lower the level of an enabling signal sent to the chip by the control system, so that the chip stops working, and the enabling signal is gradually pulled high until the first capacitor is charged; when the delay circuit is powered down, the first capacitor discharges to conduct the second triode, and the corresponding third triode is conducted to pull down the level of the enabling signal sent to the chip by the control system, so that the chip stops working, and the enabling signal is gradually pulled up until the first capacitor finishes discharging. By the above mode, the power-on delay is realized when the delay circuit is powered on, and the power-off delay is realized when the delay circuit is powered off, so that the safety of the electronic equipment at the moment of power-on and the moment of power-off is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of an embodiment of the delay circuit of the present invention.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
The reference numbers illustrate:
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a delay circuit please see fig. 1, fig. 1 is the circuit structure schematic diagram of an embodiment of the utility model of delay circuit. The time delay circuit comprises a first triode Q1, a second triode Q2, a third triode Q3, a first diode D1 and a first capacitor C1; an emitter of the first triode Q1 is connected with the power supply 10, a base of the first triode Q1 is respectively connected with an anode of the first diode D1 and a base of the second triode Q2, and a collector of the first triode Q1 is connected with a collector of the second triode Q2; the cathode of the first diode D1 is respectively connected with the first end of the first capacitor C1 and the emitter of the second triode Q2, and the second end of the first capacitor C1 is grounded; the emitter of the second triode Q2 is also connected with the base of the first triode Q1, and the collector of the second triode Q2 is connected with the base of the third triode Q3; the emitter of the third transistor Q3 is grounded, and the collector of the third transistor Q3 is connected to the control system 20 and the chip 30, respectively.
The control system 20 in the delay circuit provided in this embodiment sends an enable signal to the enable terminal of the chip 30, and it should be understood that if the enable signal received by the chip 30 is a high-level signal, the chip 30 can normally operate; if the enable signal received by the chip 30 is a low level signal, the chip 30 enters a sleep state and does not operate. When the power supply is powered on, the power supply 10 outputs voltage to charge the first capacitor C1, and the first triode Q1 is turned on, so that the third triode is correspondingly turned on after the first triode Q1 is turned on; correspondingly, after the third triode Q3 is turned on, the level of the enable signal is pulled low, and the chip 30 is controlled to be in a sleep state, so that the delayed operation of the chip 30 is realized. When the first capacitor C1 is charged, the first transistor Q1 is turned off, and the third transistor Q3 is also correspondingly turned off, and correspondingly, after the third transistor Q3 is turned off, the enable signal is restored to a high level signal, and the enable terminal of the chip 30 receives the enable signal, so that the chip 30 enters a working state. As an alternative, when the voltage output by the power supply 10 is 12V, the first capacitor C1 needs to be charged to about 11V, the third transistor Q3 is turned off, and the power-on delay of about 1 second can be realized when the circuit is powered on.
When the power is off, the first capacitor C1 discharges to the second triode Q2, the second triode Q2 is turned on, the third triode Q3 is correspondingly turned on, and correspondingly, after the third triode Q3 is turned on, the level of the enable signal is pulled down, so that the control chip 30 is in a dormant state, and the delayed operation of the chip 30 is realized. When the first capacitor C1 finishes discharging, the second diode is turned off, the third transistor Q3 is also correspondingly turned off, and correspondingly, after the third transistor Q3 is turned off, the enable signal is restored to a high-level signal, the enable end of the chip 30 receives the enable signal, and the chip 30 enters a working state. As an alternative, if the capacitance value of the first capacitor C1 is 10 μ F, the discharge time of the first capacitor C1 needs about 1 second, and the third transistor Q3 is turned off, so that a power-down delay of about 1 second can be realized when the circuit is powered down.
When the delay circuit provided by this embodiment is powered on, the power supply 10 charges the first capacitor C1 through the first diode D1, and outputs a voltage to the first triode Q1 to turn on the first triode Q1, so that the corresponding third triode Q3 is turned on to pull down the level of the enable signal sent to the chip 30 by the control system 20, so that the chip 30 stops working, and the enable signal is gradually pulled up until the first capacitor C1 is charged; when the delay circuit is powered down, the first capacitor C1 discharges, the second triode Q2 is turned on, and the corresponding third triode Q3 is turned on to lower the level of the enable signal sent to the chip 30 by the control system 20, so that the chip 30 stops working, and the enable signal is gradually raised until the first capacitor C1 finishes discharging. By the above mode, the power-on delay is realized when the delay circuit is powered on, and the power-off delay is realized when the delay circuit is powered off, so that the safety of the electronic equipment at the moment of power-on and the moment of power-off is ensured.
Further, with continued reference to fig. 1, the delay circuit further includes a first resistor R1; a first end of the first resistor R1 is connected to the power supply 10 and the emitter of the first transistor Q1, respectively, and a second end of the first resistor R1 is grounded.
Further, the delay circuit further comprises a second resistor R2; a first end of the second resistor R2 is connected to an emitter of the first transistor Q1 and a first end of the first resistor R1, respectively, and a second end of the second resistor R2 is connected to a base of the first transistor Q1.
Further, the delay circuit further comprises a third resistor R3; a first end of the third resistor R3 is connected to the second end of the second resistor R2 and the anode of the first diode D1, respectively, and a second end of the third resistor R3 is connected to the base of the second transistor Q2.
Further, the delay circuit further comprises a fourth resistor R4; a first end of the fourth resistor R4 is connected to the emitter of the second transistor Q2 and the cathode of the first diode D1, respectively, and a second end of the fourth resistor R4 is connected to the first end of the first capacitor C1.
Further, the delay circuit further comprises a fifth resistor R5; a first end of the fifth resistor R5 is connected to the collector of the first transistor Q1 and the collector of the second transistor Q2, respectively, and a second end of the fifth resistor R5 is connected to the base of the third transistor Q3.
Further, the delay circuit further comprises a sixth resistor R6; the first end of the sixth resistor R6 is connected to the second end of the fifth resistor R5, and the second end of the sixth resistor R6 is grounded.
When the circuit is powered on, the output current of the power supply 10 charges the first capacitor C1 through the second resistor R2, the first diode D1 and the fourth resistor R4, so as to implement power-on delay. After the first transistor Q1 is turned on, the output current of the power supply 10 reaches the third transistor Q3 through the fifth resistor R5 and the sixth resistor R6, so as to turn on the third transistor Q3.
When the circuit is powered off, the discharge current of the first capacitor C1 is discharged to the ground line through the fourth resistor R4, the second triode Q2, the third resistor R3, the second resistor R2 and the first resistor R1; the first capacitor C1 can also be discharged through a path of the fourth resistor R4, the second transistor Q2, the fifth resistor R5 and the sixth resistor R6.
Further, with continued reference to fig. 1, the delay circuit further includes a seventh resistor R7; a first end of the seventh resistor R7 is connected to the control system 20, and a second end of the seventh resistor R7 is connected to the collector of the third transistor Q3 and the chip 30, respectively.
Further, with continued reference to fig. 1, the delay circuit further includes a second capacitor C2; the first terminal of the second capacitor C2 is connected to the chip 30, and the second terminal of the second capacitor C2 is grounded.
In this embodiment, the seventh resistor R7 may be a pull-up resistor, and when the circuit operates, the control system 20 sends an enable signal to the chip 30 through the pull-up resistor, so that the chip 30 operates normally.
In this embodiment, a second capacitor C2 is further provided, and preferably, the second capacitor C2 is a filter capacitor for filtering out an alternating current component in the current.
The utility model also provides an electronic equipment, this electronic equipment include delay circuit, and above-mentioned embodiment can be referred to this delay circuit's structure, no longer gives unnecessary details here. It should be understood that, because the electronic device of the present embodiment adopts the technical solution of the above-mentioned delay circuit, the electronic device has all the beneficial effects of the above-mentioned delay circuit.
The above is only the optional embodiment of the present invention, and not therefore the scope of the present invention is limited, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the same way in the protection scope of the present invention.
Claims (10)
1. A time delay circuit is characterized by comprising a first triode, a second triode, a third triode, a first diode and a first capacitor;
an emitting electrode of the first triode is connected with a power supply, a base electrode of the first triode is respectively connected with an anode of the first diode and a base electrode of the second triode, and a collector electrode of the first triode is connected with a collector electrode of the second triode;
the cathode of the first diode is respectively connected with the first end of the first capacitor and the emitter of the second triode, and the second end of the first capacitor is grounded;
the emitter of the second triode is also connected with the base of the first triode, and the collector of the second triode is connected with the base of the third triode;
and the emitter of the third triode is grounded, and the collector of the third triode is respectively connected with the control system and the chip.
2. The delay circuit of claim 1, wherein the delay circuit further comprises a first resistor;
the first end of the first resistor is respectively connected with the power supply and the emitting electrode of the first triode, and the second end of the first resistor is grounded.
3. The delay circuit of claim 2, wherein the delay circuit further comprises a second resistor;
the first end of the second resistor is respectively connected with the emitting electrode of the first triode and the first end of the first resistor, and the second end of the second resistor is connected with the base electrode of the first triode.
4. The delay circuit of claim 3, further comprising a third resistor;
and the first end of the third resistor is respectively connected with the second end of the second resistor and the anode of the first diode, and the second end of the third resistor is connected with the base of the second triode.
5. The delay circuit of claim 4, wherein the delay circuit further comprises a fourth resistor;
and a first end of the fourth resistor is respectively connected with an emitter of the second triode and a cathode of the first diode, and a second end of the fourth resistor is connected with a first end of the first capacitor.
6. The delay circuit of claim 5, wherein the delay circuit further comprises a fifth resistor;
and the first end of the fifth resistor is respectively connected with the collector electrode of the first triode and the collector electrode of the second triode, and the second end of the fifth resistor is connected with the base electrode of the third triode.
7. The delay circuit of claim 6, wherein the delay circuit further comprises a sixth resistor;
and the first end of the sixth resistor is connected with the second end of the fifth resistor, and the second end of the sixth resistor is grounded.
8. The delay circuit of claim 7, wherein the delay circuit further comprises a seventh resistor;
and the first end of the seventh resistor is connected with the control system, and the second end of the seventh resistor is respectively connected with the collector of the third triode and the chip.
9. The delay circuit of claim 8, further comprising a second capacitance;
the first end of the second capacitor is connected with the chip, and the second end of the second capacitor is grounded.
10. An electronic device, characterized in that the electronic device comprises a delay circuit, wherein the delay circuit is configured as the delay circuit of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922293780.4U CN211018784U (en) | 2019-12-18 | 2019-12-18 | Time delay circuit and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922293780.4U CN211018784U (en) | 2019-12-18 | 2019-12-18 | Time delay circuit and electronic device |
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| Publication Number | Publication Date |
|---|---|
| CN211018784U true CN211018784U (en) | 2020-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922293780.4U Active CN211018784U (en) | 2019-12-18 | 2019-12-18 | Time delay circuit and electronic device |
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|---|---|
| CN (1) | CN211018784U (en) |
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- 2019-12-18 CN CN201922293780.4U patent/CN211018784U/en active Active
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