CN210927651U - Power receiving equipment supporting double-network-port Ethernet power receiving and power receiving system - Google Patents
Power receiving equipment supporting double-network-port Ethernet power receiving and power receiving system Download PDFInfo
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- CN210927651U CN210927651U CN202020363280.3U CN202020363280U CN210927651U CN 210927651 U CN210927651 U CN 210927651U CN 202020363280 U CN202020363280 U CN 202020363280U CN 210927651 U CN210927651 U CN 210927651U
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Abstract
The utility model discloses a support powered device of two net gapes ethernet power-receiving, including a power receiving detection chip, a first power receiving return circuit, a second power receiving return circuit and a delay switch-on circuit. Through the technical scheme, the problem of mutual competition of detection signals in power supply of the double network ports is solved, the two network ports in the powered device can support Ethernet power supply at the same time, the situation that two sets of powered circuits are used to cause overhigh equipment cost is avoided, and the use range and the user experience of the powered device are improved.
Description
Technical Field
The utility model relates to a power over Ethernet field especially relates to a support powered device and powered system of two net gapes ethernet powered.
Background
The Ethernet power supply is a technology which can transmit power and data to equipment through a twisted pair in the Ethernet, and the equipment comprising a network telephone, a wireless base station, a camera, a concentrator, a computer and the like can be powered by the Ethernet power supply technology through the technology; because the electronic equipment which can obtain power supply by the Ethernet can be used without an extra power socket, the time and money for configuring a power line can be saved, and the cost of the whole equipment system is relatively reduced; at present, RJ-45 network sockets are commonly adopted all over the world, so that various Ethernet devices have compatibility; the technology can operate without changing the cable structure of the Ethernet, so the adoption of the Ethernet power supply system not only saves the cost and is easy to wire and install, but also has the capacity of remote power-on and power-off.
A typical power over ethernet system includes power sourcing equipment (PSE devices), powered devices (PD devices), and a network cable. The power supply device includes POE switch, POE injector, and other product forms, and the powered device includes AP (wireless access point), IP Camera, IP telephone, and other product forms.
In some forms of powered devices, there are 2 or more ethernet ports, and users want both ports to support the ethernet powered function. Therefore, when one network port fails, the other network port can obtain power supply through Ethernet power supply, namely the powered device supports dual-network-port Ethernet power receiving.
As shown in fig. 1 of the accompanying drawings, the current typical design uses two sets of power receiving detection circuits, and each network port uses a separate power receiving detection chip, so that when two network ports simultaneously perform power over ethernet tests, the problem of detection competition is not generated, but the current typical design has the disadvantages that the configuration cost of equipment and the use space of a PCB are increased, and simultaneously, an elbow is formed on the appearance design of a product, thereby restricting the application range of the product.
If a set of power receiving detection circuit can be shared by the dual-network interface, the product cost is greatly reduced, the application range is expanded, but the design of the circuit for sharing a set of power receiving detection circuit by the dual-network interface in the current industry has defects, when two network interfaces simultaneously carry out power receiving detection, the power receiving detection result is in an invalid state due to competition of two detection signals, and further the power receiving equipment is powered on unsuccessfully, and the result is unacceptable in product commercial application, as shown in figure 2 of the attached drawing of the specification, another typical design is that the Ethernet power supply function of one network interface is temporarily closed at the power supply equipment side, and only the power supply of the single network interface is reserved at the same moment.
Disclosure of Invention
To solve the above problems in the prior art, a powered device supporting dual-port ethernet power receiving is provided, and a specific technical solution is as follows:
a powered device supporting dual-port ethernet powered, comprising:
a power receiving detection chip;
the first power receiving loop is connected between a first power receiving port and the power receiving detection chip;
the second power receiving loop is connected between a second power receiving port and the power receiving detection chip;
the first power receiving loop comprises a first forward path and a first return path;
the second power receiving circuit comprises a second forward path and a second return path;
the delay conducting circuit is arranged on the first current loop and the second current loop so as to enable the first power receiving loop to be conducted later than the second power receiving loop, and the first power receiving loop is prevented from being conducted when the second power receiving loop is conducted.
Preferably, the first power receiving loop includes a first rectifying circuit, configured to convert the external direct current with different polarities received by the first power receiving port into direct current with the same polarity;
the second power receiving loop comprises a second rectifying circuit which is used for converting the direct current with different polarities received by the second power receiving port into the direct current with the same polarity.
Further preferably, in the power receiving apparatus, the first rectifying circuit is a bridge rectifying circuit, and the first rectifying circuit includes two rectifying bridges connected in parallel;
the second rectifying circuit has the same structure as the first rectifying circuit.
Preferably, the power receiving apparatus, wherein the delay conducting circuit includes a diode, a three-terminal delay switching element, and a voltage management circuit;
a first node is arranged on the first forward path;
a second node is arranged on the first circulating path;
the voltage management circuit is connected in series between the first node and the second node and also comprises a voltage output branch circuit;
the three-terminal delay switch element is arranged on the first circulation path and is positively connected between the second node and the negative electrode port of the power receiving detection chip, and the control end of the three-terminal delay switch element is connected with the voltage output branch circuit;
a third node is arranged between the control end of the three-end time delay switch element and the voltage output branch circuit;
a fourth node is arranged on the second backflow passage and is also connected with the third node;
the diode is arranged on the second circulation path and is positively connected between the fourth node and the negative electrode port of the power receiving detection chip;
preferably, the power receiving apparatus is one in which the diode is a schottky diode.
Preferably, in the power receiving apparatus, the three-terminal delay switching element is an N-channel MOS transistor;
the source electrode of the N-channel MOS tube is close to the negative electrode port of the power receiving detection chip, the drain electrode of the N-channel MOS tube is close to the second node, and the grid electrode of the N-channel MOS tube is connected with the voltage output branch circuit.
Further preferably, the power receiving apparatus, wherein the voltage management circuit includes a first voltage-dividing resistor and a voltage-regulator tube, and the first voltage-dividing resistor and the voltage-regulator tube are connected in series;
and a fifth node is arranged between the first divider resistor and the voltage stabilizing tube, and the voltage output branch is led out from the fifth node.
Preferably, the power receiving apparatus, wherein the triac is a thyristor;
the anode of the controlled silicon is close to the negative port of the power receiving detection chip, the cathode of the controlled silicon is close to the second node, and the control electrode of the controlled silicon is connected with the voltage output branch circuit.
Further preferably, the power receiving apparatus, wherein the voltage management circuit includes a second voltage dividing resistor and a third voltage dividing resistor, and the second voltage dividing resistor and the third voltage dividing resistor are connected in series;
and a sixth node is arranged between the second voltage-dividing resistor and the third voltage-dividing resistor, and the voltage output branch is led out from the sixth node.
A powered system supporting dual-port ethernet power reception, comprising a powered device as described above;
the power receiving system also comprises a power supply device, wherein the power supply device comprises a first power supply port and a second power supply port and is used for sending a power receiving detection signal to the power receiving device and providing 36-57V direct current;
the first power supply end network port is correspondingly connected with the first power receiving end network port through a network cable;
the second power supply end network port is correspondingly connected with the second power receiving end network port through a network cable.
The technical scheme has the following advantages or beneficial effects:
this technical scheme is applicable to Endpoint type (Endpoint type) ethernet power supply equipment and Midspan type (well striding formula) ethernet power supply equipment simultaneously, through this technical scheme, has solved the mutual competition problem of detection signal in the power supply of dual network mouth, can make two net gapes in the powered device all support the ethernet power supply simultaneously, and then has avoided using two sets of powered circuits to cause the too high condition of equipment cost to take place, has improved this kind of powered device's application range and user experience.
Drawings
Fig. 1 is a schematic structural diagram of a power over ethernet system supporting dual-port power receiving in the prior art;
fig. 2 is a schematic structural diagram of a power over ethernet system supporting single-port power receiving in the prior art;
fig. 3 is a schematic structural diagram of an ethernet power supply system in a powered device and a powered system supporting dual-port ethernet power reception according to the present invention in a first embodiment;
fig. 4 is a schematic structural diagram of an ethernet power supply system in a powered device and a powered system supporting dual-port ethernet power reception according to the present invention.
Wherein:
00 is power supply equipment, 001 is a first power supply port network port, and 002 is a second power supply port network port;
01 is a power receiving device, 011 is a first power receiving port, and 012 is a second power receiving port;
a first rectifying circuit 11 and a second rectifying circuit 12;
2 is a power receiving detection chip;
3 is a voltage regulator;
4 is a diode;
51 is an N-channel MOS tube, S is a source electrode, D is a drain electrode, and G1 is a grid electrode;
52 is a thyristor, A is an anode, K is a cathode, and G2 is a control electrode;
6 is a voltage dividing circuit, 61 is a first voltage dividing resistor, 62 is a voltage regulator tube, 63 is a second voltage dividing resistor, and 64 is a third voltage dividing resistor;
a is a first node, b is a second node, c is a third node, d is a fourth node, e is a fifth node, and f is a sixth node.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention will be further described with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto.
To solve the above problems in the prior art, a powered device supporting dual-port ethernet power receiving is provided, and a specific technical solution is as follows:
a powered device 01 supporting dual-port ethernet power receiving, which is applied in an ethernet power supply system, as shown in fig. 3-4, the ethernet power supply system further includes a power supply device 00, where the power supply device 00 includes a first power port 001 and a second power port 002;
this power receiving apparatus 01 specifically includes:
the first power receiving end network port 011 is electrically connected with the first power supply end network port 001 through a network cable;
the second receiving port 012, the second receiving port 012 is electrically connected to the second power supply port 002 through a network cable;
a power receiving detection chip 2;
the first power receiving port 011 is connected with the power receiving detection chip 2 through a first rectification circuit 11, and the first power receiving port 011, the first rectification circuit 11 and the power receiving detection chip 2 form a first power receiving loop;
the second power receiving port 012 is connected to the power receiving detection chip 2 through a second rectifier circuit 12, and the second power receiving port 012, the second rectifier circuit 12 and the power receiving detection chip 2 form a second power receiving loop;
a third node c and a diode 4 are arranged between the negative terminal of the power receiving detection chip 2 and the second rectification circuit 12, the diode 4 is connected in series between the third node c and the negative terminal of the power receiving detection chip 2, and the negative electrode of the diode 4 is close to the third node c;
a first node a and a second node b are arranged between the power receiving detection chip 2 and the first rectification circuit, a voltage management circuit 6 is arranged between the first node a and the second node b, and the voltage management circuit 6 comprises a voltage output branch circuit;
a delay switch element is connected in series between the negative electrode port of the power receiving detection chip 2 and the second node b, the delay switch element comprises a control electrode, and the control electrode is connected with the voltage output branch circuit;
and a fourth node d is arranged between the voltage output branch and the control electrode, and the fourth node d is connected with the third node c.
The utility model discloses a in a preferred embodiment, for solving one set of ethernet power supply detecting system of dual net gape sharing and then produce the problem of detecting signal competition and proposed a solution, through establish a delay switch circuit on the ethernet powered path of the same kind at powered device for another ethernet powered path's detecting signal can arrive the powered detection chip earlier and accomplish the testing process and go up in advance, thereby has avoided the competition conflict of two way detecting signal.
In the above preferred embodiment, the powered device is applied to a power over ethernet system, the power over ethernet system further includes a power sourcing equipment 00, the power sourcing equipment 00 includes a first power port 001 and a second power port 002 for performing power sourcing and power sourcing detection: when the power supply device 00 is powered on again, the power supply device 00 determines that the single-port power supply operation or the double-port power supply operation needs to be executed according to a preset rule inside the device or an instruction given by an external person; when the power supply device 00 executes a single-port power supply operation, the to-be-supplied port first transmits a detection waveform once every predetermined time interval, detects whether the powered device 01 completes normal docking with the to-be-supplied port, and stops transmitting the detection waveform and continuously maintains a power-on state until the powered device 01 completes normal docking; when the power supply device 00 needs to perform the dual-port power supply operation, the first power supply port 001 and the second power supply port 002 simultaneously transmit the detection waveform once every predetermined time interval, detect whether the power receiving port in the butt joint with the first power supply port is in normal butt joint, stop transmitting the detection waveform after learning that any power receiving port is in normal butt joint, and continuously keep the power-on state to the power receiving port.
In the above preferred embodiment, the power supply network port of the power supply apparatus 00 and the power receiving network port of the power receiving apparatus 01 are connected by using five types of twisted pairs.
As shown in fig. 3-4, in the above preferred embodiment, the delay switch circuit includes a diode 4, a voltage management circuit 6 and a delay switch element, when the power supply apparatus 00 needs to perform the dual-port power supply operation, the second return path with the diode 4 will be turned on first, and the first return path with the delay switch element will be turned on in a delayed manner, so that the detected waveforms of the return flows will not generate contention conflict, and meanwhile, the dual-port power receiving function can be fully automatically implemented without human intervention, so that the problems in the prior art are effectively solved.
In the power receiving apparatus 01, the first rectifier circuit 11 and the second rectifier circuit 12 have the same structure.
Further, in the power receiving apparatus 01, the first rectification circuit 11 is a bridge rectification circuit, and the first rectification circuit 11 includes two rectification bridges connected in parallel.
In another preferred embodiment of the present invention, as shown in fig. 3-4, the first rectification circuit 11 and the second rectification circuit 12 have the same structure, and are bridge rectification circuits, and two parallel rectifier bridges are formed by eight diodes, so that the dc power with different polarities supplied by the power supply device can be efficiently converted into dc power with fixed polarity, and the dc power supply device has the characteristics of small volume and convenient use.
In a preferred embodiment, in the power receiving apparatus 01, the diode 4 is a schottky diode.
In another preferred embodiment of the present invention, a schottky diode is adopted, which has the advantages of high switching frequency and low forward voltage drop, and is suitable for use as high-frequency rectification in low-voltage and high-current output occasions, and is used as an application scenario that perfectly fits the technical solution in a preferred selection.
In a preferred embodiment, the power receiving apparatus 01 further includes a voltage regulator 3; the voltage regulator 3 is connected to the power receiving detection chip 2. After the power receiving detection is completed, the power supply device 00 can supply power to the power receiving device 01 through the ethernet, and the direct current with fixed polarity obtained through the rectifying circuit is subjected to voltage regulation through the voltage regulator and then is supplied to specific devices for power use.
Two specific examples are now provided to further illustrate and explain the present solution:
in the first embodiment of the present invention, as shown in fig. 3, the delay switch element adopts an N-channel MOS transistor 51, as shown in fig. 3, a source S of the N-channel MOS transistor is close to a negative port of the power receiving detection chip 2, a drain D of the N-channel MOS transistor is close to the second node b, and a gate G1 of the N-channel MOS transistor is connected to the voltage output branch; meanwhile, the voltage management circuit 6 is composed of a first voltage-dividing resistor 61 and a voltage-regulator tube 62, wherein the first voltage-dividing resistor 61 and the voltage-regulator tube 62 are connected in series; a fifth node e is disposed between the first voltage dividing resistor 61 and the voltage regulator 62, and the voltage output branch is led out from the fifth node e.
In the first embodiment, after the power supply apparatus 00 is powered up again, if only the first power receiving port 011 needs to be powered up according to the setting, the first power supplying port 001 sends out the detection waveform, the detection waveform is rectified by the first rectifying circuit and then reaches the power receiving detection chip to complete detection and then flows back, at this time, the voltage management circuit 6 composed of the first voltage dividing resistor 61 and the voltage regulator 62 provides the gate G1 of the N-channel MOS transistor 51 with the on-state voltage, so that the N-channel MOS transistor 51 can be smoothly turned on, the first power receiving loop is turned on to complete power receiving detection, and at this time, the first power receiving port 011 completes the power-up process and maintains the power-up state.
In the first embodiment, after the power supply apparatus 00 is powered up again, if only the second power receiving port 012 needs to be powered up according to the setting, since the diode 4 can be directly conducted, the second power receiving loop can be directly conducted to complete power receiving detection, and at this time, the second power receiving port 012 completes the power up process and maintains the power up state.
In the first embodiment, after the power supply device 00 is powered on again, if the power supply device 00 simultaneously supplies power to the first receiving port 011 and the second receiving port 012 according to the setting requirement, the power supply device 00 synchronously sends the detection waveform once at intervals of a predetermined time through the first power supply port 001 and the second power supply port 002: because the N-channel MOS 51 makes the first return path to be connected later than the second return path, and as the second return path is connected, the potentials of the third node c and the fourth node d are the same, the gate voltage is directly pulled down, so that the gate G1 cannot be turned on, and at this time, the second power receiving port 012 smoothly completes the power-on process and maintains the power supply state until the second power receiving port fails and the first power receiving port can be reconnected due to the recovery of the gate voltage when the dual-channel power receiving needs to be switched.
In a second embodiment of the present invention, as shown in fig. 4, different from the first embodiment: the time delay switch element adopts a controlled silicon 52 to replace an N-channel MOS tube, the anode A of the controlled silicon 52 is close to the negative electrode port of the power receiving detection chip 2, the cathode K of the controlled silicon 52 is close to the second node b, and the control electrode G2 of the controlled silicon 52 is connected with a voltage output branch circuit; meanwhile, the voltage management circuit 6 instead includes a second voltage-dividing resistor 63 and a third voltage-dividing resistor 64, the second voltage-dividing resistor 63 and the third voltage-dividing resistor 64 are connected in series, a sixth node f is disposed between the second voltage-dividing resistor 63 and the third voltage-dividing resistor 64, and the voltage output branch is led out from the sixth node f.
In the second embodiment, the thyristor 52 is used as a delay switch element, which has the advantages of small volume, high efficiency and long service life; the power receiving detection flow after the power supply apparatus 00 is powered on again is the same as that in the first embodiment, regardless of whether the power is received through the single port or the dual port, and will not be described here in detail.
In summary, the technical scheme is suitable for both an Endpoint-type (end-point-type) ethernet power supply device and a Midspan-type (mid-span-type) ethernet power supply device, and by the technical scheme, the problem of mutual competition of detection signals in dual-network-port power supply is solved, two network ports in a powered device can all support ethernet power supply simultaneously, so that the situation that two sets of powered circuits are used to cause too high device cost is avoided, and the use range and user experience of the powered device are improved.
The above description is only an example of the preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and those skilled in the art should be able to realize the equivalent alternatives and obvious variations of the present invention.
Claims (10)
1. A powered device supporting dual-port ethernet powered, comprising:
a power receiving detection chip;
the first power receiving loop is connected between a first power receiving port and the power receiving detection chip;
the second power receiving loop is connected between a second power receiving port and the power receiving detection chip;
the first power receiving loop comprises a first forward path and a first return path;
the second power receiving circuit comprises a second forward path and a second return path;
the power receiving circuit further comprises a delay conducting circuit, wherein the delay conducting circuit is arranged on the first current path and the second current path, so that the first power receiving circuit is conducted later than the second power receiving circuit, and the first power receiving circuit is prevented from being conducted when the second power receiving circuit is conducted.
2. The powered device of claim 1, wherein the first powered loop comprises a first rectifying circuit and the second powered loop comprises a second rectifying circuit.
3. The powered device of claim 2, wherein the first rectification circuit is a bridge rectification circuit comprising two rectification bridges connected in parallel;
the second rectifying circuit has the same structure as the first rectifying circuit.
4. The powered device of claim 1, wherein the delay-on circuit comprises a diode, a three-terminal delay switch element, and a voltage management circuit;
a first node is arranged on the first forward path;
a second node is arranged on the first circulation path;
the voltage management circuit is connected between the first node and the second node in series, and the voltage management circuit further comprises a voltage output branch circuit;
the three-terminal delay switch element is arranged on the first circulation path and is positively connected between the second node and the negative electrode port of the power receiving detection chip, and the control end of the three-terminal delay switch element is connected with the voltage output branch circuit;
a third node is arranged between the control end of the three-end time delay switch element and the voltage output branch circuit;
a fourth node is arranged on the second backflow passage and is also connected with the third node;
the diode is arranged on the second loop current path and is positively connected between the fourth node and the negative electrode port of the power receiving detection chip.
5. The powered device of claim 4, wherein the diode is a Schottky diode.
6. The power receiving device according to claim 4, wherein the three-terminal delay switching element is an N-channel MOS transistor;
the source electrode of the N-channel MOS tube is close to the negative electrode port of the power receiving detection chip, the drain electrode of the N-channel MOS tube is close to the second node, and the grid electrode of the N-channel MOS tube is connected with the voltage output branch.
7. The powered device of claim 6, wherein the voltage management circuit comprises a first voltage-dividing resistor and a voltage-regulator tube, the first voltage-dividing resistor and the voltage-regulator tube being connected in series;
and a fifth node is arranged between the first voltage dividing resistor and the voltage stabilizing tube, and the voltage output branch is led out from the fifth node.
8. The powered device of claim 4, wherein the triac is a thyristor;
the anode of the controlled silicon is close to the negative port of the power receiving detection chip, the cathode of the controlled silicon is close to the second node, and the control electrode of the controlled silicon is connected with the voltage output branch circuit.
9. The powered device of claim 8, wherein the voltage management circuit comprises a second voltage-dividing resistor and a third voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor being connected in series;
a sixth node is arranged between the second voltage-dividing resistor and the third voltage-dividing resistor, and the voltage output branch is led out from the sixth node.
10. A powered system supporting dual-port ethernet power reception, comprising a powered device according to any one of claims 1-9;
the power receiving system further comprises a power supply device, wherein the power supply device comprises a first power supply port and a second power supply port, and is used for sending a power receiving detection signal to the power receiving device and providing 36-57V direct current;
the first power supply port is correspondingly connected with the first power receiving port through a network cable;
and the second power supply end network port is correspondingly connected with the second power receiving end network port through a network cable.
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| CN202020363280.3U CN210927651U (en) | 2020-03-20 | 2020-03-20 | Power receiving equipment supporting double-network-port Ethernet power receiving and power receiving system |
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| CN202020363280.3U CN210927651U (en) | 2020-03-20 | 2020-03-20 | Power receiving equipment supporting double-network-port Ethernet power receiving and power receiving system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111245628A (en) * | 2020-03-20 | 2020-06-05 | 北京华信傲天网络技术有限公司 | Power receiving equipment supporting double-network-port Ethernet power receiving and power receiving system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111245628A (en) * | 2020-03-20 | 2020-06-05 | 北京华信傲天网络技术有限公司 | Power receiving equipment supporting double-network-port Ethernet power receiving and power receiving system |
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