CN210923928U - 1553B network bus fault point detection system - Google Patents
1553B network bus fault point detection system Download PDFInfo
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- CN210923928U CN210923928U CN201921532892.4U CN201921532892U CN210923928U CN 210923928 U CN210923928 U CN 210923928U CN 201921532892 U CN201921532892 U CN 201921532892U CN 210923928 U CN210923928 U CN 210923928U
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Abstract
The utility model discloses a 1553B network bus fault point detection system, which comprises a processor, wherein the signal input end of the processor is connected with a constant current source circuit through a controllable gain A/D converter and a preamplifier, and the constant current source circuit is connected with a 1553B bus to be detected; the utility model discloses a system can accurate detection surveyed the port voltage of the bus of MIL-STD-1553B bus network, combines its inside relevant mathematical model that presets to fix a position the fault point of common bus faults such as survey MIL-STD-1553B network bus terminal bus open circuit, bus short circuit, bus and shielding layer short circuit fast, still can be through the audio-visual demonstration of display screen with the trouble position.
Description
[ technical field ] A method for producing a semiconductor device
The utility model belongs to the technical field of MIL-STD-1553B communication network branch, especially, relate to a 1553B network bus fault point detecting system.
[ background of the invention ]
The MIL-STD-1553B bus network has strong confidentiality and high reliability, and is widely applied to the fields of spaceflight and navigation.
Common faults of the MIL-STD-1553B bus network in daily maintenance are divided into sub-line faults and bus faults, and the specific sub-line faults are as follows:
a) opening a sub-line;
b) sub-line short circuit;
c) the high end of the sub-line is in short circuit with the shielding layer;
d) the lower end of the sub-line is in short connection with the shielding layer;
e) the high/low ends of the sub-lines are connected in a staggered manner;
f) the insertion loss between sub-line ports increases.
The specific bus faults are generally as follows:
a) the bus is open;
b) short-circuiting the bus;
c) the high end of the bus is in short circuit with the shielding layer;
d) the low end of the bus is in short circuit with the shielding layer;
e) the termination resistance varies (becomes larger or smaller).
According to the technology disclosed by Chinese patent with the patent number of ZL.2018.2.0852790.X and the name of a 1553B bus network testing system, the fault can be detected, and the sub-line fault point of the MIL-STD-1553B bus network can be directly positioned. However, for faults such as open circuit of the bus, short circuit of the high end of the bus and the shielding layer, short circuit of the low end of the bus and the shielding layer, and the like, because the bus is laid in the rack, fault points are difficult to locate, the bus needs to be completely disassembled for section-by-section troubleshooting, and the daily maintenance and fault removal efficiency of the MIL-STD-1553B bus network is greatly influenced.
[ Utility model ] content
The utility model aims at providing a 1553B network bus fault point detecting system can fix a position the fault point of bus fault under the condition that need not unpack the bus apart.
The utility model adopts the following technical scheme: the 1553B network bus fault point detection system comprises a processor, wherein a signal input end of the processor is connected with a constant current source circuit through a controllable gain A/D converter and a preamplifier, and the constant current source circuit is connected with a 1553B bus to be detected.
Further, the constant current source circuit comprises a constant current source, a load switching circuit and a four-wire detection circuit;
the constant current source comprises a constant current source chip U1 and a peripheral circuit thereof;
a third pin of the constant current source chip U1 is respectively connected with +5V, one end of a capacitor C1 and one end of a capacitor C2; the other end of the capacitor C1 is grounded; the other end of the capacitor C2 is connected with a second pin of the constant current source chip U1 and one end of the resistor R2 after being connected with the resistor R4 in series, the other end of the resistor R2 is connected with a resistor R3 and then connected with one end of the resistor R1 and one end of the resistor R5, the other end of the resistor R1 is connected with a first pin of the constant current source chip U1, and the other end of the resistor R5 is connected with a load switching circuit;
the load switching circuit comprises a first relay JK1 and a second relay JK 2;
a first pin of the first relay JK1 is connected with +5V and the cathode of the diode D3;
a second pin and a seventeenth pin of the first relay JK1 are both connected to the four-wire detection circuit;
a third pin of the first relay JK1 is connected to a 1553B bus to be detected;
a fourth pin and a fifth pin of the first relay JK1 are both connected to a shielding layer of a 1553B bus to be detected;
the sixth pin of the first relay JK1 is grounded;
an eighth pin of the first relay JK1 is respectively connected with the anode of the diode D3 and the collector of the triode Q2; the emitter of the triode Q2 is grounded and connected with one end of the resistor R8, the base of the triode Q2 is connected with the other end of the resistor R8 and one end of the resistor R6, and the other end of the resistor R6 is connected with a second control signal end of the processor;
a first pin of the second relay JK2 is connected with +5V and the cathode of the diode D2;
a second pin and a seventeenth pin of the second relay JK2 are both connected to the four-wire detection circuit;
a third pin of the second relay JK2 is connected to a 1553B bus to be detected;
a fourth pin and a fifth pin of the second relay JK2 are respectively connected to a shielding layer of a 1553B bus to be detected and a grounding wire of the first connecting interface;
a sixth pin of the second relay JK2 is connected with the other end of the resistor R5;
an eighth pin of the second relay JK2 is respectively connected with the anode of the diode D2 and the collector of the triode Q1; an emitter of the triode Q1 is grounded and connected with one end of the resistor R9, a base of the triode Q1 is connected with the other end of the resistor R9 and one end of the resistor R7, and the other end of the resistor R7 is connected with a first control signal end of the processor;
the four-wire detection circuit comprises a first connection interface used for being connected with the preamplifier, the positive voltage end of the first connection interface is respectively connected with the second pin and the seven-earth pin of the second relay JK2, the negative voltage end is respectively connected with the second pin and the seven-earth pin of the first relay JK1, and the grounding end is connected with the shielding layer of the 1553B bus to be detected and the fourth pin and the fifth pin of the second relay JK 2.
Further, the preamplifier includes an AD623 chip and its peripheral circuits;
a second pin of the AD623 chip is connected with a resistor R10 in series and then is connected with a negative voltage end of the first connection interface;
a third pin of the AD623 chip is connected with a resistor R11 in series and then is connected with a positive voltage end of the first connection interface;
a sixth pin of the AD623 chip is an analog signal output positive terminal and is connected with an analog signal input positive terminal of the controllable gain A/D converter;
a fifth pin of the AD623 chip is an analog signal output negative terminal and is connected with an analog signal input negative terminal of the controllable gain A/D converter;
the controllable gain A/D converter consists of a chip U3 and a peripheral circuit thereof;
a fourth pin of the chip U3 is a data pin of the communication interface and is connected to a data input pin of the processor;
a third pin of the chip U3 is a clock pin of the communication interface and is connected to a clock pin of the processor;
a first pin of the chip U3 is an analog signal input positive terminal and is connected to an output positive terminal of the preamplifier;
the sixth pin of the chip U3 is the negative input terminal of the analog signal and is connected to the negative output terminal of the preamplifier.
Further, the processor consists of an STM32F103CBT6 chip and peripheral circuits thereof;
the thirty-second pin of the STM32F103CBT6 chip is a control pin for switching the detection line type, and is connected with a control key KE1 for switching between a bus short circuit, a bus open circuit, a short circuit of the bus Hi and a shield line and a short circuit of the bus Lo and the shield line respectively;
the twenty-first pin of the STM32F103CBT6 chip is connected with the third pin of the controllable gain A/D converter chip U3;
the twenty-second pin of the STM32F103CBT6 chip is connected with the fourth pin of the controllable gain A/D converter chip U3;
the STM32F103CBT6 chip sends the calculation result information to external equipment through a third connection interface JZ 3;
the STM32F103CBT6 chip displays the calculation result on an external display device through a second connection interface JZ 2.
The utility model has the advantages that: the utility model discloses a system can accurate detection surveyed the port voltage of the bus of MIL-STD-1553B bus network, combines its inside relevant mathematical model that presets to fix a position the fault point of common bus faults such as survey MIL-STD-1553B network bus terminal bus open circuit, bus short circuit, bus and shielding layer short circuit fast, still can be through the audio-visual demonstration of display screen with the trouble position.
[ description of the drawings ]
Fig. 1 is a schematic block diagram of a fault point detection system of an MIL-STD-1553B bus network according to an embodiment of the present invention;
fig. 2 is a physical topology of an MIL-STD-1553B bus network in an embodiment of the present invention;
fig. 3 is a schematic diagram of a constant current source circuit in a fault point detection system of an MIL-STD-1553B bus network according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a preamplifier in a fault point detection system of an MIL-STD-1553B bus network according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a controllable gain A/D converter in a MIL-STD-1553B bus network fault point detection system according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a single chip microcomputer circuit in a fault point detection system of an MIL-STD-1553B bus network according to the present invention.
[ detailed description ] embodiments
The present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
The embodiment of the utility model discloses 1553B network bus fault point detecting system, as shown in figure 1, including foretell treater, the signal input part of treater is connected with constant current source circuit through controllable gain AD converter, preamplifier, constant current source circuit with wait to detect 1553B bus connection. Through the system, measurement, conversion, gain adjustment, calculation and the like of the 1553B bus resistor can be realized, so that a more accurate resistance value is obtained, and the specific position of a fault point is obtained through calculation.
The embodiment of the utility model provides an in constant current source circuit includes constant current source, load switching circuit and four-wire detection circuitry.
The constant current source includes a constant current source chip U1 and its peripheral circuits.
A third pin of the constant current source chip U1 is respectively connected with +5V, one end of a capacitor C1 and one end of a capacitor C2; the other end of the capacitor C1 is grounded; the other end of the capacitor C2 is connected in series with a resistor R4 and then connected with a second pin of the constant current source chip U1 and one end of the resistor R2, the other end of the resistor R2 is connected in series with a resistor R3 and then connected with one end of a resistor R1 and one end of a resistor R5, the other end of the resistor R1 is connected with a first pin of the constant current source chip U1, and the other end of the resistor R5 is connected with a load switching circuit.
The constant current source circuit is formed by using a constant current source device, and in the present embodiment, as shown in fig. 3, the constant current source circuit is formed by a linear constant current power source chip of linear technology and a peripheral circuit thereof.
U1 is a typical constant current source chip, in order to suppress noise on the power supply line, a decoupling capacitor C1 is connected in parallel between the third pin of the input terminal and ground (AGND), R1, R2, R3 are constant current setting resistors, and the relation with the set constant current is that
In the present embodiment, Isource is 5 mA.
C2, R4 form a series RC network connected across the two terminals of the current source for substantially suppressing possible instabilities in the constant current source circuit. And R5 is connected in series between the constant current output and the detection circuit and is used for keeping the constant current source stable when the detection circuit corrects zero.
The load switching circuit comprises a first relay JK1 and a second relay JK 2;
a first pin of the first relay JK1 is connected with +5V and the cathode of the diode D3;
a second pin and a seventeenth pin of the first relay JK1 are both connected to the four-wire detection circuit;
a third pin of the first relay JK1 is connected to a 1553B bus to be detected;
a fourth pin and a fifth pin of the first relay JK1 are both connected to a shielding layer of a 1553B bus to be detected;
the sixth pin of the first relay JK1 is grounded;
an eighth pin of the first relay JK1 is respectively connected with the anode of the diode D3 and the collector of the triode Q2; the emitter of the triode Q2 is grounded and connected with one end of the resistor R8, the base of the triode Q2 is connected with the other end of the resistor R8 and one end of the resistor R6, the other end of the resistor R6 is connected to the second control signal end of the processor, and the other end of the resistor R8 is grounded.
A first pin of the second relay JK2 is connected with +5V and the cathode of the diode D2;
a second pin and a seventh pin of the second relay JK2 are both connected to the four-wire detection circuit;
a third pin of the second relay JK2 is connected to a 1553B bus to be detected;
a fourth pin and a fifth pin of the second relay JK2 are respectively connected to a shielding layer of a 1553B bus to be detected and a grounding wire of the first connecting interface;
a sixth pin of the second relay JK2 is connected with the other end of the resistor R5;
an eighth pin of the second relay JK2 is respectively connected with the anode of the diode D2 and the collector of the triode Q1; the emitter of the triode Q1 is grounded and connected with one end of the resistor R9, the base of the triode Q1 is connected with the other end of the resistor R9 and one end of the resistor R7, the other end of the resistor R7 is connected to a first control signal end of the processor, and the other end of the resistor R9 is grounded.
The load switching circuit consists of relays JK1 and JK2, switches of the relays are driven by triodes Q1 and Q2, R6 and R7 are current-limiting resistors of Q1 and Q2, R8 and R9 are false-action-preventing resistors of Q1 and Q2, and D2 and D3 are surge voltage absorption diodes of relay wire packages.
The constant current output is connected to the sixth pin of the relay JK1 via R5, and the ground is connected to the sixth pin of the relay JK 2.
When the processor executes bus signal line detection, Ctrl1 and Ctrl2 are both low level, JK1 and JK2 are not attracted, and constant current flows into the signal line through JK1:7 (namely the seventh pin of JK1) and returns to the ground line through JK2: 7. The voltage drop on the signal line is transferred to pin JK1:3 via pin JK1: 2; the voltage signals are transmitted to JK2:3 pins through JK2:2 pins, and JK1 and JK2 are detected voltage signals. On the premise that the current is known, the resistance on the signal line can be tested by applying ohm's law. After the processing of the rear circuit, the short circuit of the sub-line node of the signal line open circuit point behind the Nth sub-line node or the sub-line node of the signal line distance detection point L meters can be displayed on the LCD.
When the processor executes the detection of the short circuit between the bus signal line and the shield, if the low end (Lo) of the test bus is short-circuited with the shield, Ctrl1 is at low level, Ctrl2 is at high level, JK1 is not attracted, JK2 is attracted, constant current flows into the high end of the signal line through JK1:7, and returns to the ground line through the JK2:5 of the shield line. The voltage drop on the signal line is transferred via pin JK1:2 to pin JK1:3 (JK 1); through JK2:4 pins to JK2:3 pins.
If the high end (Hi) of the test bus is short-circuited with the shield, Ctrl is high level, Ctr2 is low level, JK1 attracts and JK2 does not attract, constant current flows into the shield wire through JK1:5 and returns to the ground wire through JK2: 7. The voltage drop on the signal line is transferred via pins JK1:4 to pins JK1:3 (JK 1); through JK2:2 pins to JK2:3 pins. JK1, JK2 are detected voltage signals. On the premise that the current is known, the resistance on the signal line can be tested by applying ohm's law. After the processing of the rear circuit, the fact that the signal line and the sub-line node of the shielding layer at a position L meters away from the detection point are short-circuited is displayed on the LCD.
For more accurate measurement, when the computer is started, the processor sends out an instruction, Ctrl1 and Ctrl2 are both high level and are equivalent to short circuit between JK1 and JK2, at this time, the voltage measured by the controllable gain A/D converter is drift voltage, the voltage is used as zero voltage, compensation is given in subsequent test, and the test precision can be effectively improved.
The four-wire detection circuit comprises a first connection interface used for being connected with the preamplifier, the positive voltage end of the first connection interface is respectively connected with the second pin and the seven-earth pin of the second relay JK2, the negative voltage end is respectively connected with the second pin and the seven-earth pin of the first relay JK1, and the grounding end is connected with the shielding layer of the 1553B bus to be detected and the fourth pin and the fifth pin of the second relay JK 2.
In order to eliminate measurement errors caused by voltage drop due to current flowing through the wire, the present embodiment adopts a four-wire test method: the test currents flow from the out1 and the out3, while the test lines are out2 and the out4, and no test current flows from the out2 and the out4, so voltage drops generated by the currents flowing through the out1 and the out3 do not affect the test result, and the test result is only the line voltage drop on the MIL-STD-1553B bus network to be tested and the resistance value on the MIL-STD-1553B bus network.
As shown in fig. 4, in the embodiment of the present invention, the preamplifier includes an AD623 chip and its peripheral circuit;
a second pin of the AD623 chip is connected with a resistor R10 in series and then is connected with a negative voltage end of the first connection interface;
a third pin of the AD623 chip is connected with a resistor R11 in series and then is connected with a positive voltage end of the first connection interface;
a sixth pin of the AD623 chip is an analog signal output positive terminal and is connected with an analog signal input positive terminal of the controllable gain A/D converter;
and a fifth pin of the AD623 chip is an analog signal output negative terminal and is connected with an analog signal input negative terminal of the controllable gain A/D converter.
According to the above analysis, when the signal line is open, the resistance is the largest, when the signal line is open after the first section, the resistance is 113 Ω, and the maximum resistance is 120 Ω; when the signal wire is in short circuit, the resistance value is minimum, when the signal wire is in open circuit at the end of the first section sub-wire, the resistance value is close to 0 omega, and the minimum distinguishable resistance value is positioned at 10m omega in consideration of the tolerance of +/-0.5 m.
The pre-amplifying circuit is used for amplifying the voltage value of the MIL-STD-1553B bus network to be measured to the maximum extent that the subsequent A/D converter can identify the voltage conversion, converting the voltage value into a resistance value signal, and finally determining a fault point through operation.
The measurement of the tiny resistance is required, so that the amplifier is required to have high resolution, good linearity, high input impedance, low drift, noise suppression and strong anti-interference capability.
According to the design requirement, when the test resistance is 120 omega at most and the test current is 5mA, the voltage formed on the tested resistance is Vx-I × Rx-5 × 10-3×120＝0.6V。
If the maximum input voltage of the A/D converter is 2.048V, the maximum input voltage Vmax is set to 2V, and the basic amplification gain is calculated according to the maximum input voltage Vmax
The AD623 is a low cost, high precision instrumentation amplifier that requires only one external resistor to set the gain, which ranges from 1 to 10,000. The AD623 has the characteristics of high precision (maximum nonlinearity of 40ppm), low offset voltage (maximum 50 muV) and low offset drift (maximum 0.6 muV/DEG C), and is an ideal choice for a preamplifier of a precision data acquisition system such as a tiny signal.
The amplification factor of AD623 is determined by the following equation
G is known to be 3.333, so:
considering that the goal of this embodiment is to test the resistance of the 1553B bus, the test accuracy should be improved as much as possible.
For this purpose, R isGThe half is divided into two parts, wherein R12 is 20.5K, and R13 is 22.6K omega.
All instrumentation amplifiers rectify the out-of-band small signals. This disturbance may appear as a small dc voltage offset. For this purpose, a low-pass R-C network is designed at the preamplifier input to filter out high-frequency signals. The low-pass filter limits the input signal according to the following relation
In the formula, CDAffecting the differential signal, Cc affects the common mode signal, and any mismatch of R x, Cc will degrade CMRR (common mode rejection ratio) performance of AD 623. To avoid inadvertently degrading CMRR-bandwidth performance, it is ensured that Cc is at least an order of magnitude smaller than CD. CDThe larger the Cc ratio, the less the effect of mismatch Cc.
Considering that 1553B is frequently used in an aircraft system, in which an rf power source is most likely to interfere with the circuit under test, the cutoff frequency is set to 400Hz, and according to the requirement, the input resistor R10-R11-3.9K Ω is set, and accordingly C4-0.047 uF and C3-C5-1000 pF are calculated.
The controllable gain A/D converter consists of a chip U3 and a peripheral circuit thereof;
a fourth pin of the chip U3 is a data pin of the communication interface and is connected to a data input pin of the processor;
a third pin of the chip U3 is a clock pin of the communication interface and is connected to a clock pin of the processor;
a first pin of the chip U3 is an analog signal input positive terminal and is connected to an output positive terminal of the preamplifier; the sixth pin of the chip U3 is the negative input terminal of the analog signal and is connected to the negative output terminal of the preamplifier.
The controllable gain A/D converter converts the analog signal into digital signal for the processor to analyze and process. The controllable gain A/D converter is formed by MCP3425 and its peripheral circuits. As shown in fig. 5, C8 and C9 are decoupling capacitors connected in parallel between VDD and VSS of U3; r14 and R15 are pull-up resistors of the communication interface, wherein one end of R14 is connected with a +5V power supply, and the other end is connected with a pin U3: 4; one end of R15 is connected with +5V power supply, and the other end is connected with U3:3 pin; the U3:4 pin is a data pin of a communication interface and is connected with a data pin of a processor, and the U3:3 pin is a clock pin of the communication interface and is connected with a clock pin of the processor; u3:3 is the analog signal input + terminal connected to the AD _ IN + of the preamplifier, and U3:6 is the analog signal input-terminal connected to the AD _ IN-of the preamplifier.
U3 MCP3425 is a single-channel low-noise high-precision delta-sigma A/D converter packaged by SOT-23-6, and the input end of the converter adopts differential input and the resolution is as high as 16 bits. The chip-embedded precision is 2.048V reference voltage, and the input range is enabled to be +/-2.048V difference (voltage is 4.096V). The device adopts a double-wire I2The C is compatible with a serial interface, and the power supply range of the power supply is 2.7V to 5.5V. The MCP3425 device may perform conversion at a rate of 15, 60 or 240 per second (SPS), depending on the use of the two-wire I2The device has an on-board Programmable Gain Amplifier (PGA) the PGA gain of × 1, × 2, × 4, or × 8 may be selected prior to analog-to-digital conversion, which enables the MCP3425 device to convert high resolution smaller input signals.
When the input of the MCP3425 device is 2.048V, the minimum resolution is considered to be one of the 16 bits as the sign bit
When the minimum value of the measuring resistor is 10m omega, the voltage of the measuring resistor at the input end of the MCP3425 device is Vin-Ix × Rx × 20-1 × 10-3×10×10-3×20＝200×10-6V＝200uV。
The MCP3425 device front end has an on-board Programmable Gain Amplifier (PGA), and the PGA gain of × 1, × 2, × 4 or × 8 can be selected before analog-to-digital conversion, if 8 times the gain is selected when testing a tiny resistor, the minimum voltage input to the a/D converter is Vin-200 uV × 8-1600 uV, which can greatly reduce the influence of quantization error on the measurement accuracy.
In the embodiment of the present invention, as shown in fig. 6, the processor is composed of an STM32F103CBT6 chip and its peripheral circuits;
the thirty-second pin of the STM32F103CBT6 chip is a control pin for switching the detection line type, and is connected with a control key KE1 for switching between a bus short circuit, a bus open circuit, a short circuit of the bus Hi and a shield line and a short circuit of the bus Lo and the shield line respectively;
the twenty-first pin of the STM32F103CBT6 chip is connected with the third pin of the controllable gain A/D converter chip U3;
the twenty-second pin of the STM32F103CBT6 chip is connected with the fourth pin of the controllable gain A/D converter chip U3;
the STM32F103CBT6 chip sends the calculation result information to external equipment through a third connection interface JZ 3; JZ3 is the serial communication interface of STM32F103CBT6 chip.
The STM32F103CBT6 chip displays the calculation result on an external display device through a second connection interface JZ 2.
The tasks that the processor needs to perform are:
1. after power-on, through I2C bus, initialize U3, set U3 to 16 bit A/D conversion, gain timesThe number is set to 8.
2. Reading the data of U3, and reducing the gain multiple by half when U3 overflows until U3 does not overflow; or when the U3 data is less than 10% of the full scale of the gear, the gain factor is amplified by one time until the U3 output data is proper.
3. When the gain is 1, if the U3 still overflows, fault information is displayed on an LCD screen, and if necessary, a fault signal is transmitted to an upper computer through an RS232 communication interface.
4. When the gain is 8, if the data of U3 still does not satisfy 10% of the full range of the gear, the fault information is displayed on the LCD screen, and if necessary, a fault signal is transmitted to the upper computer through the RS232 communication interface.
5. And when the single chip microcomputer correctly reads the U3 data, calculating the corresponding measured resistance value.
And KEY _ C is a test function selection KEY, and functions are switched respectively between a signal line short circuit, a signal line open circuit, a signal line Hi and shield short circuit and a signal line Lo and shield short circuit when the functions are switched once.
7. And the singlechip calculates the position of the fault point according to the setting of the state key and displays the position on the LCD.
8. If the upper computer has requirements, the test data is uploaded to the upper computer through the RS232 communication interface.
In the embodiment, the processor selects a medium-capacity enhanced type of the middle ST company, a 32-bit microcontroller with a 64 or 128K byte flash memory based on an ARM core, and an STM32F103CBT6 chip with 7 timers, 2 ADCs and 9 communication interfaces capable of realizing communication such as USB and CAN.
The STM32F103xx enhanced family has a built-in ARM core, so it is compatible with all ARM tools and software. Cortex of ARMTMThe M3 processor is a latest generation of embedded ARM processor that provides a low cost platform, reduced pin count, reduced system power consumption for the needs of MCU implementation, while providing excellent computational performance and advanced interrupt system response. Cortex of ARMTMM3 is a 32-bit RISC processor, providing additional code efficiency, leveraging AR on the memory space of typical 8 and 16-bit systemsHigh performance of the M core. Because this design does not have too high requirement to the functioning speed of singlechip, its task work volume is also little, and this kind of singlechip can satisfy the designing requirement.
JTAG _ M1 is a firmware loading interface, the single chip microcomputer communicates with a U3 through SDA, SCA, and communicates with an upper computer through JZ3 to realize serial port communication, and test results are displayed on an LCD screen through JZ 2. C10, C11, C12 and C13 are decoupling capacitors of U4 and are respectively connected in parallel between VBAT, VDD-1, VDD-2, VDD-3 and VSS pins of U4.
In order to improve the stability of the system, an external active crystal oscillator Y1 is adopted, Y1:4 and Y1:2 are power supply pins of the active crystal oscillator, a decoupling capacitor C16 is added on the power supply pins, Y1:3 is an output pin of the active crystal oscillator, and the output pin is connected to a U4:5 pin and provides a clock signal of 8MHz for the single chip microcomputer. JTAG _ M1, R16, R17, R18, R19, R20, R32 and C15 form a firmware loading interface, and are convenient for writing firmware into the single chip microcomputer. U4:32 is used to read key information for different processing of test information.
When the bus fault is confirmed to be the signal line open circuit, Ctr1 and Ctr2 are at low level, and the signal line open circuit resistance is tested.
When the bus fault is confirmed to be the signal line short circuit, Ctr1 and Ctr2 are at low level, and the signal line short circuit resistance is tested.
When the bus fault is confirmed to be the short circuit between the signal line Hi and the shield, Ctr1 is at high level, Ctr2 is at low level, and the short circuit resistance between the signal line Hi and the shield is tested.
When the bus fault is confirmed to be the short circuit between the signal line Lo and the shield, Ctr1 is at low level, Ctr2 is at high level, and the short circuit resistance between the signal line Hi and the shield is tested.
U4:21, U4:22 for I2C communication for communicating with U3, setting the gain of U3 and reading the test result of U3. The device code of U3 is 1101, its address code is 000, its configuration to registers should be done at firmware programming with reference to the AD620 data book.
When the processor reads the conversion data Vi of U3, the voltage Vx at the input is first calculated according to,
in the formula, Av is the amplification factor of the preamplifier, is set to be 3.333, β is the amplification factor of the programmable amplifier in U3, and is set by the processor, after Vx is calculated, the measured resistance can be calculated according to the following formula
If the fault point is an open-circuit fault point of the test signal wire, the fault point is
And displaying on a display screen, wherein the bus open circuit fault of the Nth terminal port from the detection point is checked.
If the fault point is a short-circuit fault point of the test signal line, the fault point is
And (5) displaying on a display screen, wherein the bus short-circuit fault of the sub-line port is checked to be about L meters away from the detection point.
If the test signal line is short-circuited with the shield, the fault point is
And (5) displaying on a display screen, wherein the bus and the shielding short-circuit fault of the sub-line port are checked to be L meters away from the detection point.
In the embodiment, the communication interface can be further connected, the U4 is that STM32F103CBT6 realizes serial port communication with an upper computer through U4:30 USART1_ TX and U4:31USART1_ RX, in order to improve the communication reliability, the U5: MAX3232CSE chip is adopted as a driving chip for serial port communication, wherein C19, C20, C21, C22 and C23 are capacitors configured according to data provided by a chip manufacturer, and U5:7DEBUG _ RX and U5:8DEBUG _ TX communicate with the upper computer through an interface JZ 3.
The working method of the processor in this embodiment is as follows:
firstly, receiving a known bus fault type of a 1553B bus to be detected; known types of bus faults include bus shorts, bus opens, and bus to shield shorts, among others.
For a sub-line fault point of an MIL-STD-1553B bus network, a technology disclosed by Chinese patent with the patent number of ZL.2018.2.0852790.X and the name of a 1553B bus network testing system is adopted, so that the fault point can be directly positioned, but for the bus fault point, only the fault type can be judged, and the fault point cannot be positioned.
Switching the detection line type on a 1553B bus to be detected according to the known bus fault type; the detection line type comprises detection between buses and detection between the buses and the shielding layer.
Then, the actual time resistance value of the detection line type is obtained.
And finally, calculating the relative position between the fault point of the 1553B bus to be detected and the detection point according to the actual resistance value.
The embodiment of the utility model provides a through unifying the trouble of MIL-STD-1553B bus network to the change of direct current resistance, through the invariable and known constant current source of electric current, make it flow through the bus of MIL-STD-1553B bus network, the port resistance after the bus that simultaneously accurate detection it and surveyed MIL-STD-1553B bus network links to each other, combine the relevant mathematical model of preset, thereby fix a position fast and surveyed MIL-STD-1553B network bus terminal bus open circuit, the fault point of bus short circuit, common bus faults such as bus and shielding layer short circuit.
The utility model discloses an on utilizing the technique that chinese patent promulgated who adopts patent number ZL.2018.2.0852790.X, the utility model name is "a 1553B bus network test system", detecting that bus network has had bus open circuit, bus short circuit, the high-end and shielding layer short circuit of bus, fault basis such as bus low side and shielding layer short circuit, utilize the change at bus network port detection bus network direct current resistance, carry out intelligent analysis to these changes to confirm the fault point position. The utility model discloses with succinct topology, lower cost, reach fast to bus open circuit, bus short circuit, the high-end and shielding layer short circuit of bus, bus low side and shielding layer short circuit etc. fault location's effect, improve the efficiency of MIL-STD-1553B bus network routine maintenance and troubleshooting.
In the embodiment of the present invention, for different types of bus faults, different methods for detecting the fault type (i.e. switching the connection line type with the bus) are involved in the corresponding process. The physical topology structure of the MIL-STD-1553B bus network may be equivalent to the circuit shown in fig. 2 according to the specification of "GJB 289A-971553B digital time division command-response type multiplexed data bus", and the specific method for switching and detecting the fault type is as follows:
when the fault type is bus short circuit, selecting a bus high end and a bus low end at one end of a 1553B bus to be detected for detection;
when the fault type is bus open circuit, selecting a bus high end and a bus low end at one end of a 1553B bus to be detected for detection;
and when the fault type is short circuit of the bus and the shielding wire, selecting the high end/the low end of the bus at one end of the 1553B bus to be detected and the corresponding shielding layer to detect.
Additionally, the embodiment of the utility model provides a bus fault type according to the difference has still designed different calculation methods, and is different according to the actual resistance value that measures, judges the concrete relative position between fault point and the check point.
When the fault type is bus short circuit, the fault model is measured from one end of the bus and is the product of the resistivity and the length of the signal wire. Its mathematical expression is Zo ═ lambda1× L, where λ1Is the resistivity of a 1553B bus, L is the distance value between a fault point and a detection point, Zo is the resistance value,
checking the resistivity of 1553B bus network bus as lambda1Considering that the current is flowing twice the length of the signal line, when the type of the fault is determined to be a bus short and the short-circuit resistance is measured at the bus port, the distance from the short-circuit fault point to the measurement point can be calculated according to the following formula.
Then there are:
namely by
Calculating to obtain a fault pointA distance value from the detection point.
When the fault type is bus open circuit, the fault model is measured from one end of the bus and is a parallel value of a plurality of double isolating resistors connected with secondary coil resistors in series, and the mathematical expression is
N is the number of sub-line nodes between the fault point and the detection point, R is the isolation resistance value, and R is the resistance value of the coupling transformer coil.
According to the specification of "GJB 289A-971553 b digital time-division command-response type multiplexed data bus", R is 56 Ω and R is less than 5 Ω (based on the actual measurement result, R is 1 Ω).
Thus, when the determined fault type is an open bus, and the open resistance is measured at the bus port, the open fault point at the nth sub-line node from the measurement point can be calculated according to the following equation.
I.e. measuring the resistance at the bus port by
And calculating to obtain the number of sub-line nodes between the fault point and the detection point.
When the fault type is short circuit between the bus and the shielding line, no matter the high end of the bus is short circuit with the shielding layer or the low end of the bus is short circuit with the shielding layer, the fault model is measured between the signal line at one end of the bus and the shielding layer and is the product of the resistivity and the length of the bus plus the product of the resistivity and the length of the shielding layer, and the mathematical expression is Zo ═ lambda (lambda is1×L)+(λ2×L)＝L(λ1+λ2)，λ2Is the resistivity of the shield layer.
Looking up the resistivity of a 1553B bus network signal line as lambda10.08 omega/m, the resistivity of the 1553B bus network shielding layer is lambda20.03 Ω/m, therefore, when it is determined that the type of the fault is a short circuit between the bus signal line and the shield layer, the bus port is measured for the signal line andthe short-circuit resistance of the shielding layer can calculate the distance from the short-circuit fault point to the measuring point according to the following formula;
namely by
And calculating to obtain a distance value between the fault point and the detection point.
Claims (4)
1.1553B network bus fault point detection system, which is characterized in that the system comprises a processor, the signal input end of the processor is connected with a constant current source circuit through a controllable gain A/D converter and a preamplifier, and the constant current source circuit is connected with a 1553B bus to be detected.
2. The 1553B network bus point of failure detection system of claim 1, wherein the constant current source circuit comprises a constant current source, a load switching circuit and a four-wire detection circuit;
the constant current source comprises a constant current source chip U1 and peripheral circuits thereof;
a third pin of the constant current source chip U1 is respectively connected with +5V, one end of a capacitor C1 and one end of a capacitor C2; the other end of the capacitor C1 is grounded; the other end of the capacitor C2 is connected in series with a resistor R4 and then is connected with a second pin of the constant current source chip U1 and one end of a resistor R2, the other end of the resistor R2 is connected in series with a resistor R3 and then is connected with one end of a resistor R1 and one end of a resistor R5, the other end of the resistor R1 is connected with a first pin of the constant current source chip U1, and the other end of the resistor R5 is connected with the load switching circuit;
the load switching circuit comprises a first relay JK1 and a second relay JK 2;
a first pin of the first relay JK1 is connected with +5V and the cathode of a diode D3;
a second pin and a seventeenth pin of the first relay JK1 are both connected to the four-wire detection circuit;
a third pin of the first relay JK1 is connected to a 1553B bus to be detected;
a fourth pin and a fifth pin of the first relay JK1 are both connected to a shielding layer of the 1553B bus to be detected;
a sixth pin of the first relay JK1 is grounded;
an eighth pin of the first relay JK1 is respectively connected with the anode of a diode D3 and the collector of a triode Q2; the emitter of the triode Q2 is grounded, the base of the triode Q2 is respectively connected with one end of a resistor R8 and one end of a resistor R6, and the other end of the resistor R6 is connected to a second control signal end of the processor;
a first pin of the second relay JK2 is connected with +5V and the cathode of a diode D2;
a second pin and a seventeenth pin of the second relay JK2 are both connected to the four-wire detection circuit;
a third pin of the second relay JK2 is connected to a 1553B bus to be detected;
a fourth pin and a fifth pin of the second relay JK2 are respectively connected to a shielding layer of the 1553B bus to be detected and a grounding wire of the first connecting interface;
a sixth pin of the second relay JK2 is connected with the other end of the resistor R5;
an eighth pin of the second relay JK2 is respectively connected with the anode of a diode D2 and the collector of a triode Q1; the emitter of the transistor Q1 is grounded, the base of the transistor Q1 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with a first control signal end of the processor;
the four-wire detection circuit comprises a first connection interface used for being connected with a preamplifier, a positive voltage end of the first connection interface is respectively connected with a second pin and a seventh pin of a second relay JK2, a negative voltage end of the first connection interface is respectively connected with a second pin and a seventh pin of a first relay JK1, and a ground end of the first connection interface is connected with a shielding layer of a 1553B bus to be detected and a fourth pin and a fifth pin of a second relay JK 2.
3. The 1553B network bus failure point detection system of claim 2, wherein the preamplifier includes an AD623 chip and its peripheral circuits;
a second pin of the AD623 chip is connected with a resistor R10 in series and then connected with a negative voltage end of the first connection interface;
a third pin of the AD623 chip is connected with a resistor R11 in series and then is connected with a positive voltage end of the first connection interface;
a sixth pin of the AD623 chip is an analog signal output positive terminal and is connected with an analog signal input positive terminal of the controllable gain A/D converter;
a fifth pin of the AD623 chip is an analog signal output negative terminal and is connected with an analog signal input negative terminal of the controllable gain A/D converter;
the controllable gain A/D converter consists of a chip U3 and a peripheral circuit thereof;
a fourth pin of the chip U3 is a data pin of a communication interface and is connected to a data input pin of the processor;
a third pin of the chip U3 is a clock pin of a communication interface and is connected to a clock pin of the processor;
the first pin of the chip U3 is an analog signal input positive terminal and is connected to an output positive terminal of the preamplifier;
the sixth pin of the chip U3 is the negative terminal of the analog signal input, and is connected to the negative terminal of the output of the preamplifier.
4. The 1553B network bus failure point detection system of claim 3, wherein the processor consists of an STM32F103CBT6 chip and its peripheral circuits;
the thirty-second pin of the STM32F103CBT6 chip is a control pin for switching a detection line type, and is connected with a control key KE1 for switching between a bus short circuit, a bus open circuit, a short circuit of the bus Hi and a shield line and a short circuit of the bus Lo and the shield line respectively;
the twenty-first pin of the STM32F103CBT6 chip is connected with the third pin of the controllable gain A/D converter chip U3;
a twenty-second pin of the STM32F103CBT6 chip is connected with a fourth pin of the controllable gain A/D converter chip U3;
the STM32F103CBT6 chip sends calculation result information to external equipment through a third connection interface JZ 3; the STM32F103CBT6 chip displays the calculation result on an external display device through a second connection interface JZ 2.
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| CN110456210A (en) * | 2019-09-16 | 2019-11-15 | 西安太世德航空电器有限公司 | 1553B network-bus trouble point checking method, apparatus and system |
| CN110456210B (en) * | 2019-09-16 | 2024-03-26 | 西安太世德航空电器有限公司 | 1553B network bus fault point detection method, device and system |
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