CN210912091U - Battery management unit for sending pulse width modulation signal to detect high-voltage interlock - Google Patents
Battery management unit for sending pulse width modulation signal to detect high-voltage interlock Download PDFInfo
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- CN210912091U CN210912091U CN201921643543.XU CN201921643543U CN210912091U CN 210912091 U CN210912091 U CN 210912091U CN 201921643543 U CN201921643543 U CN 201921643543U CN 210912091 U CN210912091 U CN 210912091U
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 abstract description 3
- 238000001514 detection method Methods 0.000 description 10
- 230000002159 abnormal effect Effects 0.000 description 2
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- 238000005070 sampling Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
- Y02T10/00—Road transport of goods or passengers
- Y02T10/60—Other road transportation technologies with climate change mitigation effect
- Y02T10/70—Energy storage systems for electromobility, e.g. batteries
Abstract
The utility model discloses a battery management unit for sending pulse width modulation signals to detect high-voltage interlocking, wherein a first IO port (111) of a singlechip (11) is communicated with a switch control end (131) of a high-frequency switch circuit (13), and a power supply port (121) of a system basic chip (12) is communicated with a high-level input end (132) of the high-frequency switch circuit; and a level output end (133) of the high-frequency switch circuit is communicated with one end of a low-voltage line of the external high-voltage interlocking circuit, and the other end of the low-voltage line of the external high-voltage interlocking circuit is communicated with a third IO port (113) of the single chip microcomputer. And a second IO port (112) of the singlechip is communicated with the level output end of the high-frequency switching circuit. The single chip microcomputer controls the high-frequency switch circuit to send out PWM signals, and the signals are used for detecting the high-voltage interlocking loop, a special PWM signal generation sending circuit is not needed to be arranged in an electric loop, and the electric complexity and the production cost are reduced.
Description
Technical Field
The utility model relates to a battery management system in electric automobile's the power battery package especially relates to a send pulse width modulation signal to detect battery management unit of high-pressure interlocking.
Background
The HVIL is English abbreviation of High Voltage Inter-lock, and is named as High-Voltage interlock in Chinese, and is a safety design method for monitoring the integrity of a High-Voltage circuit by using a low-Voltage signal.
The BMU is an english abbreviation of Battery Management Unit, and is named as a Battery Management Unit in chinese, and functions of the BMU include single Battery voltage detection, Battery temperature detection, balance control fan, heating control, and the like.
The MCU is an English abbreviation of a Microcontroller Unit, and the Chinese name is a micro control Unit or a single chip microcomputer.
Herein, the SBC is an english abbreviation of System Basis Chips, and is named as a System base chip in chinese. The SBC is an integrated component, and combines common system functions required by an automotive onboard computer, such as: communication transceivers, voltage regulators, diagnostic and monitoring functions, switching and wake-up inputs, and the like.
The PWM is an english abbreviation of Pulse width modulation, and is called Pulse width modulation in chinese, and the PWM signal is a signal for detecting the high-voltage interlock loop.
The existing electric automobile is internally provided with a high-voltage electric system loop, and due to the fact that voltage in the loop is high, serious consequences can be caused if abnormal conditions occur in the loop, for example, poor contact and abnormal disconnection of a connector can generate electric arcs to cause open fire, or short circuit occurs in the loop, and instant explosion of battery energy can be caused. Therefore, in order to improve the safety of electric vehicles, HVIL is often used in conventional electric vehicles. The HVIL detects the connection status of all the branches connected to the high voltage bus on the electric vehicle by using the low voltage signal, including whether the electrical connections of the entire battery system, wires, connectors, motor controller, high voltage box and protective cover are intact.
At present, one of the many detection methods is to use the PWM signal as an output to detect the loop signal, which has a good detection effect, but needs to configure an additional PWM signal generating circuit, which not only increases the electrical complexity in the vehicle, but also increases the production cost.
Disclosure of Invention
An object of the utility model is to provide a battery management unit who sends pulse width modulation signal detection high pressure interlocking sends the PWM signal by this battery management unit to the realization is to the detection in high pressure interlocking return circuit.
In order to realize the technical purpose, the utility model adopts the following technical scheme:
a battery management unit for sending pulse width modulation signals to detect high-voltage interlocking comprises a single chip microcomputer and a system basic chip; the single chip microcomputer comprises a first IO port, a second IO port and a third IO port, and the system basic chip comprises a power supply port; the battery management unit also comprises a high-frequency switch circuit, wherein the high-frequency switch circuit comprises a switch control end, a high-level input end and a level output end; a first IO port of the single chip microcomputer is communicated with a switch control end of the high-frequency switch circuit, and a power supply port of the system basic chip is communicated with a high-level input end of the high-frequency switch circuit; the level output end of the high-frequency switch circuit is communicated with one end of a low-voltage circuit of the external high-voltage interlocking circuit, and the other end of the low-voltage circuit of the external high-voltage interlocking circuit is communicated with a third IO port of the single chip microcomputer.
Further, a second IO port of the single chip microcomputer is communicated with a level output end of the high-frequency switch circuit.
Further, the battery management unit further comprises a filtering module, and the other end of the low-voltage line of the external high-voltage interlocking loop is communicated with a third IO port of the single chip microcomputer through the filtering module.
The utility model discloses a be provided with a high frequency switch circuit among the battery management unit, then send the PWM signal by single chip microcomputer control high frequency switch circuit to be used for the detection in high-pressure interlocking return circuit with this signal. Compared with the prior art, a special PWM signal generation sending circuit is not required to be arranged in the electric loop, so that the electric arrangement space is saved, the electric complexity is reduced, and the production cost is also reduced.
Drawings
Fig. 1 is a schematic diagram of the connection between the battery management unit for sending pwm signals to detect high-voltage interlock and the external high-voltage interlock loop of the present invention.
In the figure: the system comprises a battery management unit 10, a single chip microcomputer 11, a first IO port 111, a second IO port 112, a third IO port 113, a system basic chip 12, a power supply port 121, a high-frequency switching circuit 13, a switch control end 131, a high-level input end 132, a level output end 133, a filtering module 14 and a high-voltage electrical module 20.
Detailed Description
The invention will be further described with reference to the following drawings and specific embodiments:
referring to fig. 1, the present embodiment includes a battery management unit 10 and a set of high-voltage electrical modules 20, wherein the battery management unit 10 is a specific implementation of the present invention, and the high-voltage electrical modules 20 refer to each electrical module in the high-voltage circuit, such as a battery system, a wire, a connector, a motor controller, a high-voltage box, and the like.
The high-voltage electrical module 20 and the high-voltage electrical module 20 are connected in series through a high-voltage connector, so as to form a high-voltage interlocking loop. The high-voltage connector comprises a high-voltage line connecting pin and a low-voltage line connecting pin, the structure of the high-voltage connector is specially designed, and the low-voltage line connecting pin is shorter than the high-voltage line connecting pin, so that the high-voltage line connecting pin can be ensured to be in good contact with the low-voltage line connecting pin under the condition that the low-voltage line connecting pin is in good contact with the high-voltage line connecting pin. High voltage power required for normal operation is transmitted between the high voltage electrical module 20 and the high voltage electrical module 20 via high voltage lines, while a loop formed by low voltage lines is used to transmit test signals to check the integrity of the lines.
The battery management unit 10 includes a single chip microcomputer 11, a system base chip 12, and a high frequency switching circuit 13.
The single chip microcomputer 11 includes a first IO port 111, a second IO port 112, and a third IO port 113, where the three ports are IO ports of the single chip microcomputer 11, the first IO port 111 is used to send a waveform control signal to the high frequency switch circuit 13, the second IO port 112 is used to receive PWM waveform feedback sent by the high frequency switch circuit 13, and the third IO port 113 receives a PWM waveform signal passing through the interlock loop.
The system base chip 12 includes a power supply port 121, and the power supply port 121 is used for providing a high-level input for the high-frequency switch circuit 13.
The high-frequency switch circuit 13 comprises a switch control end 131, a high-level input end 132 and a level output end 133, a high-frequency switch is arranged in the high-frequency switch circuit 13, the switch control end 131 is used for controlling the switch state of the high-frequency switch, one end of the high-frequency switch is grounded, the other end of the switch is divided into two paths, one path is communicated with the high-level input end 132 through a series resistor, and the other path is communicated with the level output end 133 through the series resistor; electrically, when the switch control terminal 131 controls the switch to be turned on, the switch pulls the level on the level output terminal 133 low, the level output terminal 133 outputs a low level, and when the switch control terminal 131 controls the switch to be turned off, the high level input terminal 132 pulls the level on the level output terminal 133 high, and the level output terminal 133 outputs a high level.
A first IO port 111 of the single chip microcomputer 11 is communicated with a switch control end 131 of the high-frequency switch circuit 13, and a power supply port 121 of the system base chip 12 is communicated with a high-level input end 132 of the high-frequency switch circuit 13; the level output end 133 of the high-frequency switch circuit 13 is communicated with one end of the low-voltage line of the external high-voltage interlocking circuit, and the other end of the low-voltage line of the external high-voltage interlocking circuit is communicated with the third IO port 113 of the single chip microcomputer 11.
When line detection is performed, the system base chip 12 in the battery management unit 10 outputs a 5V power signal from the power supply port 121 to the high-level input end 132 of the high-frequency switch circuit 13, the single chip microcomputer 11 outputs a waveform signal with a specific frequency duty ratio to the switch control end 131 of the high-frequency switch circuit 13 through the first IO port 111, the two signals are modulated by the high-frequency switch circuit 13 and then output a PWM waveform signal for testing from the level output end 133, the signal is sent to the low-voltage line for transmission, the PWM signal is finally sent back to the third IO port 113 of the single chip microcomputer 11 through the low-voltage line, and finally the single chip microcomputer 11 identifies the characteristics of the frequency, the duty ratio and the like of the returned signal to determine whether the high-voltage interlock loop fails.
According to practical situations, a resistor voltage-dividing circuit is usually arranged before the third IO port 113 of the single chip microcomputer 11 to avoid the damage of the single chip microcomputer 11 due to the excessively high voltage in the PWM signal returned by the low-voltage line.
In the present embodiment, the PWM signal is not generated by a dedicated PWM signal generating circuit, but a high frequency switch circuit 13 is added to the battery management unit 10, and then the single chip microcomputer 11 controls the high frequency switch circuit 13 to generate the PWM signal, and uses the PWM signal for the detection of the high voltage interlock loop. Compared with the prior art, a special PWM signal generation sending circuit is not required to be arranged in the electric loop, so that the electric arrangement space is saved, the electric complexity is reduced, and the production cost is also reduced.
In addition, in order to ensure that the PWM waveform signal output by the level output terminal 133 of the high frequency switch circuit 13 is normal, in the battery management unit 10, the second IO port 112 of the single chip microcomputer 11 is communicated with the level output terminal 133 of the high frequency switch circuit 13, the single chip microcomputer 11 samples the PWM waveform signal output by the level output terminal 133 of the high frequency switch circuit 13 through the second IO port 112, and the single chip microcomputer 11 can adjust and optimize the PWM waveform signal output by the first IO port 111 according to the analysis and sampling result. According to practical conditions, a resistance voltage dividing circuit is usually arranged on the sampling line to avoid the damage of the singlechip 11 due to the overhigh voltage in the PWM signal.
The battery management unit 10 further includes a filtering module 14, and the other end of the low-voltage line of the external high-voltage interlock loop is communicated with the third IO port 113 of the single chip microcomputer 11 through the filtering module 14, so as to filter out clutter components in the detection signal waveform.
In the present embodiment, the high-frequency switch circuit 13 is a VNN1NV04 chip.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, therefore, any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (3)
1. A battery management unit for sending pulse width modulation signals to detect high-voltage interlocking is disclosed, wherein the battery management unit (10) comprises a single chip microcomputer (11) and a system base chip (12); the single chip microcomputer (11) comprises a first IO port (111), a second IO port (112) and a third IO port (113), and the system base chip (12) comprises a power supply port (121);
the method is characterized in that: the battery management unit (10) further comprises a high-frequency switch circuit (13), wherein the high-frequency switch circuit (13) comprises a switch control end (131), a high-level input end (132) and a level output end (133);
a first IO port (111) of the single chip microcomputer (11) is communicated with a switch control end (131) of the high-frequency switch circuit (13), and a power supply port (121) of the system basic chip (12) is communicated with a high-level input end (132) of the high-frequency switch circuit (13);
and a level output end (133) of the high-frequency switch circuit (13) is communicated with one end of a low-voltage line of an external high-voltage interlocking circuit, and the other end of the low-voltage line of the external high-voltage interlocking circuit is communicated with a third IO port (113) of the single chip microcomputer (11).
2. The battery management unit for transmitting pwm signals to detect high voltage interlocks of claim 1, wherein: and a second IO port (112) of the singlechip (11) is communicated with a level output end (133) of the high-frequency switch circuit (13).
3. The battery management unit for transmitting pwm signals to detect high voltage interlock according to claim 1 or 2, wherein: the battery management unit (10) further comprises a filtering module (14), and the other end of the low-voltage line of the external high-voltage interlocking loop is communicated with a third IO port (113) of the single chip microcomputer (11) through the filtering module (14).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921643543.XU CN210912091U (en) | 2019-09-29 | 2019-09-29 | Battery management unit for sending pulse width modulation signal to detect high-voltage interlock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921643543.XU CN210912091U (en) | 2019-09-29 | 2019-09-29 | Battery management unit for sending pulse width modulation signal to detect high-voltage interlock |
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| Publication Number | Publication Date |
|---|---|
| CN210912091U true CN210912091U (en) | 2020-07-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921643543.XU Active CN210912091U (en) | 2019-09-29 | 2019-09-29 | Battery management unit for sending pulse width modulation signal to detect high-voltage interlock |
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| Country | Link |
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| CN (1) | CN210912091U (en) |
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- 2019-09-29 CN CN201921643543.XU patent/CN210912091U/en active Active
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| GR01 | Patent grant | ||
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Address after: Room 1001, 10 / F, office building, Shihu Jinling Plaza, 88 Nanxijiang Road, Yuexi, Wuzhong District, Suzhou City, Jiangsu Province, 215128 Patentee after: DuPu (Suzhou) New Energy Technology Co.,Ltd. Patentee after: JIANGSU DUPU NEW ENERGY TECHNOLOGY Co.,Ltd. Address before: 201804 room 108, floor 1, building 1, No. 6988, Jiasong North Road, Anting Town, Jiading District, Shanghai J67 Patentee before: SHANGHAI DUPU NEW ENERGY TECHNOLOGY Co.,Ltd. Patentee before: JIANGSU DUPU NEW ENERGY TECHNOLOGY Co.,Ltd. |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Battery management unit for transmitting pulse width modulation signal to detect high voltage interlock Effective date of registration: 20220114 Granted publication date: 20200703 Pledgee: Industrial and Commercial Bank of China Limited Suzhou Wuzhong sub branch Pledgor: DuPu (Suzhou) New Energy Technology Co.,Ltd. Registration number: Y2022320010022 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20230202 Granted publication date: 20200703 Pledgee: Industrial and Commercial Bank of China Limited Suzhou Wuzhong sub branch Pledgor: DuPu (Suzhou) New Energy Technology Co.,Ltd. Registration number: Y2022320010022 |
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| TR01 | Transfer of patent right | ||
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Effective date of registration: 20231127 Address after: Room 1001, 10 / F, office building, Shihu Jinling Plaza, 88 Nanxijiang Road, Yuexi, Wuzhong District, Suzhou City, Jiangsu Province, 215128 Patentee after: DuPu (Suzhou) New Energy Technology Co.,Ltd. Patentee after: VOLKSWAGEN AG Address before: Room 1001, 10 / F, office building, Shihu Jinling Plaza, 88 Nanxijiang Road, Yuexi, Wuzhong District, Suzhou City, Jiangsu Province, 215128 Patentee before: DuPu (Suzhou) New Energy Technology Co.,Ltd. Patentee before: JIANGSU DUPU NEW ENERGY TECHNOLOGY Co.,Ltd. |