CN210899108U

CN210899108U - Four-phase clock generation circuit suitable for high-speed clock scene

Info

Publication number: CN210899108U
Application number: CN201922024009.7U
Authority: CN
Inventors: 郭啸峰; 陈润; 陈勇刚; 陈振骐
Original assignee: Shenzhen Nuoruixin Technology Co ltd
Current assignee: Shenzhen Nuoruixin Technology Co ltd
Priority date: 2019-11-21
Filing date: 2019-11-21
Publication date: 2020-06-30
Anticipated expiration: 2029-11-21

Abstract

The utility model relates to a four-phase clock produces circuit suitable for high-speed clock scene belongs to integrated circuit design technical field. The four-phase clock generation circuit consists of a 50% duty ratio clock generation circuit, a phase separation circuit, an 1/2 frequency multiplication frequency divider with symmetrical output and a symmetrical input AND gate which are connected in sequence; the phase separation circuit is composed of 10 inverters. The circuit of the utility model is hardly affected by process angle deviation and temperature, and can further reduce the system phase error of the four-phase generating circuit by using the symmetrical input AND gate, so that the circuit can be suitable for high-speed clock scenes in an open-loop structure without using a more complex closed-loop structure to meet the requirement of the high-speed clock scenes; the method has the advantages of smaller systematic delay error and smaller phase error of the four-phase clock, thereby being applicable to high-speed clock scenes.

Description

Four-phase clock generation circuit suitable for high-speed clock scene

Technical Field

The utility model belongs to the technical field of the integrated circuit design, in particular to four-phase clock produces circuit suitable for high-speed clock scene.

Background

High-speed clocks (clock frequencies greater than 5GHz) are mainly used to generate four-phase output clocks, such clocks being used in mixers (mixers) and time-interleaved modules.

The four-phase clock refers to four clocks with 4 cycles being the same, the duty ratios being 25%, the initial phases being 0 °, 90 °, 180 °, 270 °, and the application scenarios thereof are generally modules such as a mixer in a radio frequency SoC chip, for a low-speed system, the four-phase clock of a traditional open-loop (closed-loop corresponding to a feedback system, open-loop corresponding to a non-feedback system) structure is generally used for a low-speed clock scenario, as shown in fig. 1, the circuit is composed of a 50% duty ratio clock generating circuit, an inverter, an 1/2 frequency multiplier and an and gate which are connected in sequence. The principle is as follows: a clock CLK with 50% duty ratio is generated by a clock generating circuit with 50% duty ratio, then 0-degree and 180-degree phase clocks CLKA and CLKB are obtained by an inverter, the CLKA and CLKB are obtained by an 1/2 frequency multiplication frequency divider, the CLKA/CLKAB with the frequency of 1/2, the phases of 0-degree and 180-degree (obtained by dividing 0-degree by 1/2) and the CLKAA/CLKAB with the phases of 90-degree and 270-degree (obtained by dividing 180-degree by 1/2) are obtained, and then the CLKAA/CLKAB are output by an AND gate to obtain a four-phase clock with the frequency of 1/2, the duty ratio of 25 percent and the initial phases of 0, 90, 180 and 270 degrees.

In the current industry or published patent literature, the four-phase clock is generated by using the method in the low-speed clock scene, because the four-phase clock is a combinational logic circuit with an open-loop structure, the four-phase clock has the advantages of high reliability and simple implementation, and the defect of systematic phase delay error in the implementation mode. For a high-speed system (the frequency of a master clock is more than 5GHz), the requirement on the delay error of a four-phase clock is more strict (the phase error is equal to the delay error divided by the clock period, because the clock period becomes smaller, and the phase error caused by the same delay error is larger), the generation of CLKA and CLKB by using a conventional inverter circuit can have the systematic error of one inverter delay, meanwhile, an asymmetric AND gate design can also introduce additional errors, the delay error of the finally generated four-phase output can reach more than 1 inverter delay (for processes of 28nm and above, the delay of 1 inverter is at least 10pS, and the finally generated phase error is often more than this value), for a high-speed clock (the clock frequency is more than 5GHz, and the corresponding period is less than 200pS), the generated phase error is difficult to accept (the delay error of 10pS is equivalent to the phase error of 18 DEG relative to the clock scene of 5GHz, this is a relatively large value) which is why the current high-speed clock scenario uses almost no such open-loop structure to generate the four-phase clock.

Disclosure of Invention

The utility model aims at overcoming the weak point of prior art, provide a four phase clock production circuit suitable for high-speed clock scene. The utility model has the advantages of systematic time delay error is littleer, therefore the phase error of four-phase clock is littleer can be suitable for with the high-speed clock scene.

The utility model provides a four phase clock generating circuit suitable for high speed clock scene, which is characterized in that the circuit is composed of a 50% duty ratio clock generating circuit, a phase separation circuit, an 1/2 frequency multiplication frequency divider with symmetrical output and a symmetrical input AND gate which are connected in sequence; the phase separation circuit consists of 10 inverters, wherein the output end of the 50% duty ratio clock generation circuit is sequentially connected with the first inverter to the fifth inverter; the input end of a sixth inverter (6) is connected between the output end of the first inverter (1) and the input end of the second inverter (2), and the output end of the sixth inverter (6) is connected between the output end of the fourth inverter (4) and the input end of the fifth inverter (5); the input end of the seventh inverter (7) is connected with the output end of the fifth inverter (5); the eighth inverter (8) and the ninth inverter (9) are connected in series, the input end of the eighth inverter (8) is connected between the output end of the second inverter (2) and the input end of the third inverter (3), the output end of the tenth inverter (10) is connected between the output end of the fifth inverter (5) and the input end of the seventh inverter (7), and the input end of the tenth inverter (10) is connected between the output end of the seventh inverter (7) and the output end of the ninth inverter (9); the output end of the ninth inverter (9) and the output end of the seventh inverter (7) output CLKA together, and the output end of the fifth inverter (5) and the output end of the tenth inverter (10) output CLKB together.

The utility model discloses a characteristics and beneficial effect:

in the conventional inverter structure, the 180 ° phase signal is obtained by passing the 0 ° phase signal through an inverter, so that there is an inherent systematic phase delay error. The utility model discloses based on the conventional open loop configuration four-phase clock generation circuit that is used for the low-speed clock scene, through adopting phase separation circuit to replace simple phase inverter circuit and produce the signal of 0 and 180 phase place, can eliminate the inherent time delay error that equals a phase inverter time delay between 0 and 180 that the phase inverter circuit produced mathematically. The utility model discloses the circuit is compared in other implementation, and it hardly receives the influence of technology angular deviation and temperature, still can further reduce the system phase error that four phases produced the circuit through using symmetrical input AND gate, makes it be applicable to high-speed clock scene with the open loop configuration, need not use more complicated closed loop configuration to realize the requirement of high-speed clock scene.

The utility model has the advantages of systematic time delay error is littleer, therefore the phase error of four-phase clock is littleer can be suitable for with the high-speed clock scene.

Drawings

Fig. 1 is a schematic diagram of a four-phase clock generation circuit of a conventional low-speed clock scenario. Fig. 2 is a schematic diagram of the overall structure of the four-phase clock generation circuit suitable for the high-speed clock scenario of the present invention.

Fig. 3 is a schematic structural diagram of an embodiment of the phase separation circuit of the present invention.

Fig. 4 is a schematic diagram of a symmetrical input and gate circuit used in the present invention.

Detailed Description

The utility model provides a four-phase clock produces circuit suitable for high-speed clock scene, below combine the figure and embodiment detailed description as follows:

the utility model provides a four-phase clock produces circuit suitable for high-speed clock scene, as shown in FIG. 2, this circuit is by the 1/2 frequency multiplication frequency divider and the symmetry input AND gate constitution of 50% duty cycle clock production circuit, phase separation circuit, symmetry output that connect gradually. The working principle is as follows: an output clock CLK with 50% duty ratio is generated by a 50% duty ratio clock generating circuit, the CLK generates CLKA and CLKB, CLKA and CLKB by a phase separating circuit, and generates CLKA and CLKB with frequency of 1/2, initial phases of 0 DEG and 180 DEG, and CLKB with initial phases of 90 DEG and 270 DEG by a 1/2 frequency doubling frequency divider with symmetrical output, and then CLKAA/CLKAB/CLKB are output by a symmetrical input AND gate (in the figure, phase 1 corresponds to CLKAB & CLKAA, phase 2 corresponds to CLKAA & CLKB, phase 3 corresponds to CLKAA & CLKB, phase 4 corresponds to CLKAB & CLKAB, wherein & represents AND gate logic symbols) to obtain a four-phase clock with frequency of 1/2, duty ratio of 25%, initial phases of 0 DEG, 90 DEG and 180 DEG, and 270 deg.

Because the CLK of this circuit 50% duty cycle clock generating circuit output when producing CLKA and CLKB through phase separation circuit, CLKA and CLKB's output is strict 180 phase difference (from this conventional circuit with the delay error of inverter eliminated), and still adopt the 1/2 times frequency divider that adopts symmetrical output, and symmetrical input AND gate does not introduce any systematic phase error, therefore the utility model discloses a four-phase clock phase error that the structure produced is far less than the phase error that traditional structure produced (eliminated systematic phase error), only produces phase error by domain mismatch and technology error, and its value is generally less than 3pS), can satisfy the application demand in high-speed clock scene.

The specific embodiments of the constituent circuits of the present invention are described as follows:

the specific implementation structure of the phase separation circuit of the present invention is shown in fig. 3, and the circuit is composed of 10 inverters, wherein the output end of the 50% duty cycle clock generation circuit is sequentially connected to the first to fifth inverters; the input end of a sixth inverter 6 is connected between the output end of the first inverter 1 and the input end of the second inverter 2, and the output end of the sixth inverter 6 is connected between the output end of the fourth inverter 4 and the input end of the fifth inverter 5; the input end of the seventh inverter 7 is connected with the output end of the fifth inverter 5; the eighth inverter 8 and the ninth inverter 9 are connected in series, the input end of the eighth inverter 8 is connected between the output end of the second inverter 2 and the input end of the third inverter 3, the output end of the tenth inverter 10 is connected between the output end of the fifth inverter 5 and the input end of the seventh inverter 7, and the input end of the tenth inverter 10 is connected between the output end of the seventh inverter 7 and the output end of the ninth inverter 9; the output terminal of the ninth inverter 9 outputs CLKA in common with the output terminal of the seventh inverter 7, and the output terminal of the fifth inverter 5 outputs CLKB in common with the output terminal of the tenth inverter 10.

The working principle of the circuit is as follows: the input clock CLK is cascaded through 6 inverters to output CLKA, the input clock CLK is cascaded through 2 inverters to obtain a signal CLK2 firstly, meanwhile, the input clock CLK is cascaded through 4 inverters to obtain a signal CLK4, then CLK2 and CLK4 are directly connected to the input end of a fifth inverter 5 together to obtain CLKB, finally, the CLKA is connected to the CLKB through the output end of a tenth inverter with a small size, and the CLKB is also connected to the CLKA through the output end of a ninth inverter with the same small size. If 1 is used to represent the inverter with the smallest size in the process standard cell library, the normalized sizes of the inverters in this embodiment are 7 times that of the inverter with the smallest size, 6 times that of the first inverter, 5 times that of the fifth, seventh and eighth inverters, 3 times that of the third, fourth and sixth inverters, and 2 times that of the ninth and tenth inverters, respectively. This combination of dimensions can achieve CLKA and CLKB that are close to the ideal 180 ° phase difference. It can be seen that CLKB is derived from 3 inverter cascades and 5 inverter cascades together, with an average delay time of 4 inverter delays. And CLKA is obtained by cascading 4 inverters, so that the time delay of the CLKA and the CLKB relative to CLK is 4 inverter time delays, a systematic one-inverter (or odd number) time delay error does not exist between the CLKA and the CLKB, CLKA is connected to CLKB through 1 inverter, CLKB is connected to CLKA through 1 inverter, and the correlation of 180-degree phase difference is further enhanced, so that two signals CLKA and CLKB closest to the 180-degree phase difference are obtained.

The utility model discloses a symmetrical input AND gate concrete implementation structure is shown in FIG. 4, and this circuit is a generalized structure, comprises two NAND gates, and every NAND gate comprises a PMOS pipe (M11, M21) and two NMOS pipes (M12, M13) and (M22, M23) respectively, and these two NAND gates symmetrical formula are connected, and wherein two PMOS combinations that connect common input signal simplify to one. The circuit of the AND gate is simplified into a description of the NAND gate, and the specific connection of the circuit is that A and B represent two inputs of a symmetric NAND gate, X represents an output of the symmetric NAND gate, wherein A and B are respectively connected with a power supply and the output X through a PMOS (M11, M21), A and B are respectively connected with the ground and the output X through two serial NMOSs (M12, M13), B and A are also connected with the ground and the output X through two serial NMOSs (M22, M23), wherein 2 PMOSs (M11, M21) have the same size, layout positions are close and are centrosymmetric, the sizes of 4 NMOSs are the same, the layout positions are close and are centrosymmetric, and the sizes of the PMOS and the NMOS are determined by electron and hole mobility in process parameters

The principle of the circuit is as follows: a and B are the two inputs of two nand gates, and X is the output of two nand gates. A and B are the same from any perspective, so it does not introduce any systematic symmetry errors in the path of the clock generation circuit.

The realization mode of 50% duty cycle circuit has a lot of circuits, the utility model discloses a 50% duty cycle clock produces the circuit can select for use and can realize forming the input clock of duty cycle in the certain limit into the clock output of strict 50% duty cycle and do not change a disclosed circuit of its frequency.

The utility model discloses a classic 1/2 times frequency division circuit structure that can adopt to 1/2 times frequency division circuit's concrete realization: i.e. the output of the D flip-flop is connected to the input and the clock is connected to the input clock to achieve a division of 1/2 times. The D flip-flop is also implemented by using classical combinational logic, i.e. by using 4 nand gates, and the nand gates used therein are also the symmetric input nand gates described in the present invention.

Claims

1. A four-phase clock generating circuit suitable for a high-speed clock scene is characterized by comprising a 50% duty cycle clock generating circuit, a phase separating circuit, an 1/2 frequency multiplication frequency divider with symmetrical output and a symmetrical input AND gate which are sequentially connected; the phase separation circuit consists of 10 inverters, wherein the output end of the 50% duty ratio clock generation circuit is sequentially connected with the first inverter to the fifth inverter; the input end of a sixth inverter (6) is connected between the output end of the first inverter (1) and the input end of the second inverter (2), and the output end of the sixth inverter (6) is connected between the output end of the fourth inverter (4) and the input end of the fifth inverter (5); the input end of the seventh inverter (7) is connected with the output end of the fifth inverter (5); the eighth inverter (8) and the ninth inverter (9) are connected in series, the input end of the eighth inverter (8) is connected between the output end of the second inverter (2) and the input end of the third inverter (3), the output end of the tenth inverter (10) is connected between the output end of the fifth inverter (5) and the input end of the seventh inverter (7), and the input end of the tenth inverter (10) is connected between the output end of the seventh inverter (7) and the output end of the ninth inverter (9); the output end of the ninth inverter (9) and the output end of the seventh inverter (7) output CLKA together, and the output end of the fifth inverter (5) and the output end of the tenth inverter (10) output CLKB together.

2. A four-phase clock generation circuit suitable for high-speed clock scenarios as claimed in claim 1, wherein the symmetrical input and gate circuit structure is composed of two nand gates, each of which is composed of one PMOS transistor (M11, M21) and two NMOS transistors (M12, M13) and (M22, M23), the two nand gates are symmetrically connected; the circuit is specifically connected in a way that two inputs A and B are respectively connected with a power supply and an output X through PMOS tubes (M11 and M21) of two NAND gates, the two inputs A and B are respectively connected with the ground and the output X through two serially connected NMOS tubes (M12 and M13) of a first NAND gate, the two inputs B and A are also connected with the ground and the output X through two serially connected NMOS tubes (M22 and M23) of a second NAND gate, wherein the sizes of the 2 PMOS tubes (M11 and M21) are the same, the layout positions are close and are centrosymmetric, the sizes of the 4 NMOS tubes are the same, and the layout positions are close and are centrosymmetric.