CN210864384U - Intelligence-promoting jigsaw control circuit - Google Patents
Intelligence-promoting jigsaw control circuit Download PDFInfo
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- CN210864384U CN210864384U CN201922241882.1U CN201922241882U CN210864384U CN 210864384 U CN210864384 U CN 210864384U CN 201922241882 U CN201922241882 U CN 201922241882U CN 210864384 U CN210864384 U CN 210864384U
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Abstract
The utility model discloses an intelligence-promoting jigsaw control circuit, which comprises an STM32F103C8T6 main control chip, a power circuit, a reset circuit, a clock circuit, an ADC detection circuit and a key circuit; the power supply circuit supplies power to the STM32F103C8T6 main control chip, and the reset circuit, the clock circuit, the ADC detection circuit and the key circuit are respectively connected to the STM32F103C8T6 main control chip. Utilize the structure of the utility model, the playing function is realized by connecting the circuit after the picture arrangement is completed.
Description
Technical Field
The utility model relates to a puzzle control circuit.
Background
Along with the improvement of living standard of people, people pay more attention to entertainment and learning, especially parent-child activities, how to lead parents to harvest more while playing with children is the future development trend of children toys, the idea jigsaw is based on the consideration of the buying demand of the jigsaw of people, when the parents play with children, the concentration degree of the attention of the brain is improved, the attention is developed, the learning and working efficiency is improved, the jigsaw is the most common choice of the current children toys, the AR intelligence-benefiting jigsaw breaks through the traditional mode, the circuit, the AR platform, the jigsaw, the mp3 module and the led lamp are combined, the most modern parent-child toys are created, and the players have better parent-child activities in strive.
The existing jigsaw tool only reflects the jigsaw and can not realize the expansibility function of the jigsaw.
Disclosure of Invention
The utility model aims at providing a puzzle control circuit benefits intelligence utilizes the utility model discloses a structure realizes playing the function through connecting the circuit after the picture arragement is accomplished.
In order to achieve the purpose, the intelligence-developing jigsaw control circuit comprises an STM32F103C8T6 main control chip, a power supply circuit, a reset circuit, a clock circuit, an ADC detection circuit and a key circuit; the power supply circuit supplies power to the STM32F103C8T6 main control chip, and the reset circuit, the clock circuit, the ADC detection circuit and the key circuit are respectively connected to the STM32F103C8T6 main control chip;
the ADC detection circuit comprises a triode Q1, a triode Q2 and a resistor R2, wherein a collector of the triode Q1 is connected with an output end of a power circuit, an emitter of the triode Q1 is connected with an input end of a preset circuit, a base of the triode Q1 is connected with a resistor R2, a collector of the triode Q2 is connected with an output end of the preset circuit, an emitter of the triode Q2 is grounded, meanwhile, an emitter of the triode Q2 is connected with a GND end of an STM32F103C8T6 main control chip, a base of the triode Q2 is connected with a resistor R2, and a resistor R2 is connected with a PB0 end of the STM32F103C8T6 main;
the key circuit comprises a first key circuit, a second key circuit, a third key circuit, a fourth key circuit, a fifth key circuit, a sixth key circuit, a seventh key circuit and an eighth key circuit;
the first key circuit comprises a light emitting diode LED1 and a switch K1, the anode of the light emitting diode LED1 is connected with the PA0 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED1 is grounded through a switch K1;
the second key circuit comprises a light emitting diode LED2 and a switch K2, the anode of the light emitting diode LED2 is connected with the PA1 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED2 is grounded through a switch K2;
the third key circuit comprises a light emitting diode LED3 and a switch K3, wherein the anode of the light emitting diode LED3 is connected with the PA2 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED3 is grounded through a switch K3;
the fourth key circuit comprises a light emitting diode LED4 and a switch K4, the anode of the light emitting diode LED4 is connected with the PA3 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED4 is grounded through a switch K4;
the fifth key circuit comprises a light emitting diode LED5 and a switch K5, wherein the anode of the light emitting diode LED5 is connected with the PA4 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED5 is grounded through a switch K5;
the sixth key circuit comprises a light emitting diode LED6 and a switch K6, wherein the anode of the light emitting diode LED6 is connected with the PA5 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED6 is grounded through a switch K6;
the seventh key circuit comprises a light emitting diode LED7 and a switch K7, wherein the anode of the light emitting diode LED7 is connected with the PA6 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED7 is grounded through a switch K7;
the eighth key circuit comprises a light emitting diode LED8 and a switch K8, wherein the anode of the light emitting diode LED8 is connected with the PA7 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED8 is grounded through a switch K8;
the anodes of the light emitting diodes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8 are respectively connected to the output end of the power supply circuit through a resistor R10;
the STM32F103C8T6 main control chip is connected with a loudspeaker.
The control method of the intelligence-promoting jigsaw control circuit comprises the following steps:
(1) turning on a power supply circuit, and enabling the power supply circuit to supply power to the STM32F103C8T6 main control chip, the reset circuit and the ADC detection circuit;
(2) the whole puzzle control circuit is reset through a reset switch;
(3) the method comprises the following steps of detecting a preset circuit signal consisting of picture mosaic modules through an ADC detection circuit, wherein the specific method comprises the following steps: the STM32F103C8T6 main control chip gives voltages to triodes Q1 and Q2 through a PB0 end, the triodes Q1 and Q2 are conducted, the output end of a power circuit is connected into a preset circuit through a triode Q1, and the output end of the preset circuit is connected to a triode Q2, so that an acquisition signal can be obtained from the STM32F103C8T6 main control chip, whether jigsaw is correct or not is judged by comparing the acquisition signal with a comparison signal, if the jigsaw is correct, the step (4) is carried out, and if the jigsaw is incorrect after comparison, the jigsaw is carried out again;
(5) music is played through the key switch and played through the loudspeaker.
According to the intelligent jigsaw control circuit, on the premise that a jigsaw is correct, the circuit built in the jigsaw module is connected into the control circuit, so that music notes of 1, 2, 3, 4, 5, 6, 7 and i can be played through the key switches K1-K8, a music tune is formed through popping up and is played through a loudspeaker, other functions of a jigsaw tool are developed, and the entertainment function of the jigsaw tool is improved.
Further, the reset circuit comprises a resistor R1, a capacitor C1 and a switch K9; one end of the resistor R1 is connected with the output end of the power supply circuit, the other end of the resistor R1 is grounded through a capacitor C1, the switch K9 is connected between the capacitors C1 in parallel, and the resistor R1 and the capacitor C1 are connected to the NRST reset end of the STM32F103C8T6 main control chip. With this configuration, when the switch K9 is pressed, the capacitor C1 is short-circuited, thereby resetting the device.
Furthermore, the clock circuit comprises a crystal oscillator tube Y1, a capacitor C2 and a capacitor C3, two ends of the crystal oscillator tube Y1 are respectively connected with OSC _ OUT and OSC _ IN ends of the STM32F103C8T6 main control chip, one end of a capacitor C2 is connected with one end of a crystal oscillator tube Y1, the other end of the capacitor C2 is grounded, one end of the capacitor C3 is connected with the other end of a crystal oscillator tube Y1, and the other end of the capacitor C3 is grounded. The mosaic can be timed through the structure.
Furthermore, the STM32F103C8T6 is connected with a display screen on the main control chip. The display is convenient.
Drawings
Figure 1 is a schematic diagram of an intelligent puzzle control circuit.
Fig. 2 is a schematic diagram of a power supply circuit.
Fig. 3 is a schematic diagram of a reset circuit.
Fig. 4 is a schematic diagram of a clock circuit.
FIG. 5 is a diagram illustrating a predetermined circuit corresponding to a tile module.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1 to 4, the intelligence promoting puzzle control circuit includes an STM32F103C8T6 main control chip 11, a power supply circuit 12, a reset circuit 13, a clock circuit 14, an ADC detection circuit 15, and a key circuit 16.
As shown in fig. 2, the power circuit 12 includes an XC6206P332MR chip 121, a capacitor C8, a capacitor C9, a resistor R4, and a light emitting diode LED 9; the VIN end of XC6206P332MR chip is connected with the input end of the power supply, in this embodiment, the power supply of the power supply input end is 5V, the VOUT end of XC6206P332MR chip is connected with the output end, in this embodiment, the voltage of the output end is 3.3V, the GND end of XC6206P332MR chip is grounded, capacitor C8 is connected with the VIN end and the GND end XC of XC6206P332MR chip, capacitor C9 is connected with the VOUT end and the GND end of 6206P332MR chip, the VOUT end of XC6206P332MR chip is connected with resistor R4 and light emitting diode LED9 in sequence, and the output end of diode LED9 is. In the power supply circuit, after voltage is input into an XC6206P332MR chip 121, a stable voltage value is output under the filtering action of capacitors C8 and C9, and whether the power supply circuit outputs the voltage can be visually observed through a light-emitting diode LED 9. The power supply circuit supplies power to the STM32F103C8T6 main control chip.
As shown in fig. 3, the reset circuit 13 includes a resistor R1, a capacitor C1, and a switch K9; one end of the resistor R1 is connected with the output end of the power supply circuit, the other end of the resistor R1 is grounded through a capacitor C1, the switch K9 is connected between the capacitors C1 in parallel, and the resistor R1 and the capacitor C1 are connected to the NRST reset end of the STM32F103C8T6 main control chip. By pressing the switch K9, the capacitor C1 is shorted out, resetting the device is achieved.
As shown IN fig. 4, the clock circuit 14 includes a crystal oscillator tube Y1, a capacitor C2, and a capacitor C3, two ends of the crystal oscillator tube Y1 are respectively connected to OSC _ OUT and OSC _ IN terminals on the STM32F103C8T6 main control chip, one end of a capacitor C2 is connected to one end of a crystal oscillator tube Y1, the other end of the capacitor C2 is grounded, one end of the capacitor C3 is connected to the other end of the crystal oscillator tube Y1, and the other end of the capacitor C3 is grounded. The picture mosaic timing can be realized through the crystal oscillator tube Y1.
As shown in fig. 1, the ADC detection circuit 15 includes a transistor Q1, a transistor Q2 and a resistor R2, a collector of the transistor Q1 is connected to an output terminal of the power supply circuit, an emitter of the transistor Q1 is connected to an input terminal of the preset circuit, a base of the transistor Q1 is connected to the resistor R2, a collector of the transistor Q2 is connected to an output terminal of the preset circuit, an emitter of the transistor Q2 is grounded, meanwhile, an emitter of the transistor Q2 is connected to a GND terminal of the STM32F103C8T6 main control chip, a base of the transistor Q2 is connected to the resistor R2, and the resistor R2 is connected to a PB0 terminal of the STM32F103C8T 6.
As shown in fig. 1, the key 16 circuit includes a first key circuit, a second key circuit, a third key circuit, a fourth key circuit, a fifth key circuit, a sixth key circuit, a seventh key circuit, and an eighth key circuit.
The first key circuit comprises a light emitting diode LED1 and a switch K1, the anode of the light emitting diode LED1 is connected with the PA0 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED1 is grounded through the switch K1.
The second key circuit comprises a light emitting diode LED2 and a switch K2, the anode of the light emitting diode LED2 is connected with the PA1 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED2 is grounded through the switch K2.
The third key circuit comprises a light emitting diode LED3 and a switch K3, wherein the anode of the light emitting diode LED3 is connected with the PA2 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED3 is grounded through the switch K3.
The fourth key circuit comprises a light emitting diode LED4 and a switch K4, the anode of the light emitting diode LED4 is connected with the PA3 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED4 is grounded through the switch K4.
The fifth key circuit comprises a light emitting diode LED5 and a switch K5, wherein the anode of the light emitting diode LED5 is connected with the PA4 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED5 is grounded through the switch K5.
The sixth key circuit comprises a light emitting diode LED6 and a switch K6, wherein the anode of the light emitting diode LED6 is connected with the PA5 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED6 is grounded through the switch K6.
The seventh key circuit comprises a light emitting diode LED7 and a switch K7, wherein the anode of the light emitting diode LED7 is connected with the PA6 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED7 is grounded through the switch K7.
The eighth key circuit comprises a light emitting diode LED8 and a switch K8, wherein the anode of the light emitting diode LED8 is connected with the PA7 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED8 is grounded through the switch K8.
The anodes of the light emitting diodes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8 are connected to the output terminal of the power supply circuit through resistors R10, respectively.
As shown in FIG. 5, the input terminal of the predetermined circuit corresponding to the tile module is connected to the SPK + terminal of the emitter of the transistor Q1, and the output terminal of the predetermined circuit corresponding to the tile module is connected to the SPK-terminal of the collector of the transistor Q2. When the puzzle pieces 100 in the puzzle module are correctly spliced, SPK + and SPK-are communicated.
The control method of the intelligence-promoting jigsaw control circuit comprises the following steps:
(1) and the power supply circuit is turned on, and the power supply circuit supplies power to the STM32F103C8T6 main control chip, the reset circuit and the ADC detection circuit.
(2) The entire puzzle control circuit is reset by pressing switch K9.
(3) The method comprises the following steps of detecting a preset circuit signal consisting of picture mosaic modules through an ADC detection circuit, wherein the specific method comprises the following steps: STM32F103C8T6 main control chip gives triode Q1 and Q2 voltage through PB0 end, let triode Q1 and Q2 switch on, power supply circuit's output is connected to in the predetermined circuit through triode Q1, the output of predetermined circuit is connected to on the triode Q2, thereby can obtain the signal of gathering at STM32F103C8T6 main control chip, compare with the comparison signal through this signal of gathering and judge whether the picture arragement is correct, if the picture arragement is correct, shift to step (4), if the picture arragement is incorrect after the comparison, the picture arragement again.
(5) Music is played through the key switch and played through the loudspeaker.
According to the intelligent jigsaw control circuit, on the premise that a jigsaw is correct, the circuit built in the jigsaw module is connected into the control circuit, so that music notes of 1, 2, 3, 4, 5, 6, 7 and i can be played through the key switches K1-K8, a music tune is formed through popping up and is played through a loudspeaker, other functions of a jigsaw tool are developed, and the entertainment function of the jigsaw tool is improved.
Claims (5)
1. An intelligence-promoting jigsaw control circuit is characterized in that: the system comprises an STM32F103C8T6 main control chip, a power circuit, a reset circuit, a clock circuit, an ADC detection circuit and a key circuit; the power supply circuit supplies power to the STM32F103C8T6 main control chip, and the reset circuit, the clock circuit, the ADC detection circuit and the key circuit are respectively connected to the STM32F103C8T6 main control chip;
the ADC detection circuit comprises a triode Q1, a triode Q2 and a resistor R2, wherein a collector of the triode Q1 is connected with an output end of a power circuit, an emitter of the triode Q1 is connected with an input end of a preset circuit, a base of the triode Q1 is connected with a resistor R2, a collector of the triode Q2 is connected with an output end of the preset circuit, an emitter of the triode Q2 is grounded, meanwhile, an emitter of the triode Q2 is connected with a GND end of an STM32F103C8T6 main control chip, a base of the triode Q2 is connected with a resistor R2, and a resistor R2 is connected with a PB0 end of the STM32F103C8T6 main;
the key circuit comprises a first key circuit, a second key circuit, a third key circuit, a fourth key circuit, a fifth key circuit, a sixth key circuit, a seventh key circuit and an eighth key circuit;
the first key circuit comprises a light emitting diode LED1 and a switch K1, the anode of the light emitting diode LED1 is connected with the PA0 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED1 is grounded through a switch K1;
the second key circuit comprises a light emitting diode LED2 and a switch K2, the anode of the light emitting diode LED2 is connected with the PA1 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED2 is grounded through a switch K2;
the third key circuit comprises a light emitting diode LED3 and a switch K3, wherein the anode of the light emitting diode LED3 is connected with the PA2 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED3 is grounded through a switch K3;
the fourth key circuit comprises a light emitting diode LED4 and a switch K4, the anode of the light emitting diode LED4 is connected with the PA3 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED4 is grounded through a switch K4;
the fifth key circuit comprises a light emitting diode LED5 and a switch K5, wherein the anode of the light emitting diode LED5 is connected with the PA4 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED5 is grounded through a switch K5;
the sixth key circuit comprises a light emitting diode LED6 and a switch K6, wherein the anode of the light emitting diode LED6 is connected with the PA5 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED6 is grounded through a switch K6;
the seventh key circuit comprises a light emitting diode LED7 and a switch K7, wherein the anode of the light emitting diode LED7 is connected with the PA6 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED7 is grounded through a switch K7;
the eighth key circuit comprises a light emitting diode LED8 and a switch K8, wherein the anode of the light emitting diode LED8 is connected with the PA7 end of the STM32F103C8T6 main control chip, and the cathode of the light emitting diode LED8 is grounded through a switch K8;
the anodes of the light emitting diodes LED1, LED2, LED3, LED4, LED5, LED6, LED7 and LED8 are respectively connected to the output end of the power supply circuit through a resistor R10;
the STM32F103C8T6 main control chip is connected with a loudspeaker.
2. The puzzle control circuit of claim 1, wherein: the power supply circuit comprises an XC6206P332MR chip, a capacitor C8, a capacitor C9, a resistor R4 and a light-emitting diode LED 9; the VIN end of the XC6206P332MR chip is connected with the input end of a power supply, the VOUT end of the XC6206P332MR chip is connected with the output end, the GND end of the XC6206P332MR chip is grounded, the capacitor C8 is connected with the VIN end and the GND end of the XC6206P332MR chip, the capacitor C9 is connected with the VOUT end and the GND end of the XC6206P332MR chip, the VOUT end of the XC6206P332MR chip is sequentially connected with the resistor R4 and the LED9, and the output end of the diode LED9 is grounded.
3. The puzzle control circuit of claim 1, wherein: the reset circuit comprises a resistor R1, a capacitor C1 and a switch K9; one end of the resistor R1 is connected with the output end of the power supply circuit, the other end of the resistor R1 is grounded through a capacitor C1, the switch K9 is connected between the capacitors C1 in parallel, and the resistor R1 and the capacitor C1 are connected to the NRST reset end of the STM32F103C8T6 main control chip.
4. The puzzle control circuit of claim 1, wherein: the clock circuit comprises a crystal oscillator tube Y1, a capacitor C2 and a capacitor C3, wherein two ends of the crystal oscillator tube Y1 are respectively connected with OSC _ OUT and OSC _ IN ends of an STM32F103C8T6 main control chip, one end of a capacitor C2 is connected with one end of a crystal oscillator tube Y1, the other end of the capacitor C2 is grounded, one end of the capacitor C3 is connected with the other end of a crystal oscillator tube Y1, and the other end of the capacitor C3 is grounded.
5. The puzzle control circuit of claim 1, wherein: the STM32F103C8T6 is connected with a key K11 and a display screen on the main control chip.
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CN201922241882.1U CN210864384U (en) | 2019-12-16 | 2019-12-16 | Intelligence-promoting jigsaw control circuit |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110794753A (en) * | 2019-12-16 | 2020-02-14 | 华南理工大学广州学院 | Intelligence-promoting jigsaw control circuit and control method |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN110794753A (en) * | 2019-12-16 | 2020-02-14 | 华南理工大学广州学院 | Intelligence-promoting jigsaw control circuit and control method |
CN110794753B (en) * | 2019-12-16 | 2024-05-31 | 华南理工大学广州学院 | Intelligent jigsaw control circuit and control method |
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