CN210839494U - Analog circuit with selectable attenuation coefficient - Google Patents
Analog circuit with selectable attenuation coefficient Download PDFInfo
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- CN210839494U CN210839494U CN201921163410.2U CN201921163410U CN210839494U CN 210839494 U CN210839494 U CN 210839494U CN 201921163410 U CN201921163410 U CN 201921163410U CN 210839494 U CN210839494 U CN 210839494U
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Abstract
The utility model discloses an optional analog circuit of decay coefficient, including decay coefficient selection circuit and amplifier circuit, decay coefficient selection circuit is including the gain resistance adjustment module of connecting the amplifier circuit input, gain resistance adjustment module includes: the circuit comprises an input resistance unit, a selection switch and a feedback resistor, wherein the input resistance unit is connected with a plurality of resistance monomers in series, the selection switch is connected between the input resistance unit and the input end of an amplifying circuit to control the input resistance unit, the feedback resistor is connected between the output end of the input resistance unit and the output end of the amplifying circuit to realize the operational amplifier following of the amplifying circuit, and the number of the resistance monomers connected to the input end of the amplifying circuit in the input resistance unit is adjusted through the selection switch to realize the attenuation coefficient selection of the amplifying circuit. The utility model discloses can realize accurate attenuation coefficient control, to the precision detection of SOC chip that has analog function, have very big use value and higher economic benefits.
Description
Technical Field
The utility model relates to an analog signal tests the field, in particular to optional analog circuit of decay coefficient.
Background
With the development of semiconductor technology, the chip design industry is more and more inclined to integrate more and more circuit modules on a System On Chip (SOC), so that the complexity of the system design end can be reduced, the cost of a system board card can be reduced, the design of the system board card is promoted to be miniaturized and thinned, and the SOC chip has more market competitiveness.
Currently, Automatic Test Equipment (ATE) tests analog circuits of system-on-chip chips in a DUT (Device under Test). The system-on-chip has high requirements on the amplitude of the input analog signal. Therefore, the signal input with large noise or interference inevitably leads to poor signal output. If the input signal is not controlled and adjusted to ensure the performance of the input signal, the purpose of testing the circuit performance of the SOC chip itself of the DUT cannot necessarily be achieved. Therefore, in order to better reflect the circuit performance of the SOC chip of the DUT itself, it is necessary to improve the performance of the input signal as much as possible so that the test result can truly reflect the circuit performance.
As shown in fig. 1, two input ends of the amplifying circuit are respectively connected in parallel with a plurality of resistors (R11-R15, R16-R19), and each resistor is correspondingly controlled by one relay switch (SW 9-SW 12, SW 13-SW 16). The internal resistance Ron of the relay switch itself becomes a part of the Gain resistance, on the basis, the amplification circuit is modeled to obtain a modeling diagram of the amplification circuit with the optional Gain as shown in fig. 2, and the Gain is calculated to be Rf/(Rg + Ron). Conventionally, Rf is 500 Ω, Rg is 500 Ω, and the expected Gain should be 1, but the actual calculation result Gain is 500/(500+50) 0.90909, which is much smaller than the expected value. On the occasion that the requirement on the precision of the gain coefficient is not high, the influence of the internal resistance of the relay switch on the gain coefficient can be ignored. However, for high-precision test equipment, the effect of gain error affects test precision, and has a significant effect on evaluating DUT performance, and therefore is not negligible.
SUMMERY OF THE UTILITY MODEL
The utility model provides an optional analog circuit of decay coefficient to analog circuit causes the attenuation error because of the reason of relay internal resistance among the solution prior art, thereby influences high accuracy test equipment's test accuracy problem.
In order to solve the technical problem, the utility model provides an optional analog circuit of decay coefficient, including decay coefficient selection circuit and amplifier circuit, decay coefficient selection circuit is including the gain resistance adjustment module of connecting the amplifier circuit input, the gain resistance adjustment module includes: the circuit comprises an input resistance unit, a selection switch and a feedback resistor, wherein the input resistance unit is connected with a plurality of resistance monomers in series, the selection switch is connected between the input resistance unit and the input end of an amplifying circuit to control the input resistance unit, the feedback resistor is connected between the output end of the input resistance unit and the output end of the amplifying circuit to realize the operational amplifier following of the amplifying circuit, and the number of the resistance monomers connected to the input end of the amplifying circuit in the input resistance unit is adjusted through the selection switch to realize the attenuation coefficient selection of the amplifying circuit.
Preferably, the amplifier further comprises a driving circuit, an input end of the driving circuit is connected to an output end of the amplifying circuit, and an output end of the driving circuit is an output end of the analog circuit.
Preferably, the selection switch adopts a multi-way selection switch (MUX) or a single-pole single-throw switch to realize the selection of the number of the resistance units.
Preferably, the single-pole single-throw switches correspond to the resistor units in the input resistor unit one by one, and each single-pole single-throw switch is correspondingly connected between the output end of the resistor unit and the input end of the amplifying circuit.
Preferably, the gain resistance adjusting modules are provided with two groups, and the two groups of gain resistance adjusting modules are respectively connected to two input ends of the amplifying circuit.
Preferably, the single-ended to differential conversion circuit is controlled by an upper computer and provides a single-ended signal for one input end of the amplifying circuit, and the other input end of the amplifying circuit is grounded.
Preferably, the single-ended to differential conversion circuit adopts a first digital-to-analog converter, and the first digital-to-analog converter is arranged between the upper computer and the input end of the amplifying circuit and is used for performing digital-to-analog conversion on a single-ended signal output by the upper computer and transmitting the converted single-ended signal to the amplifying circuit.
Preferably, the amplifier further comprises a common mode voltage adjusting circuit, wherein the common mode voltage adjusting circuit is controlled by the upper computer and provides a common mode level signal for the amplifying circuit.
Preferably, the common mode voltage regulating circuit adopts a second digital-to-analog converter, and the second digital-to-analog converter is arranged between the upper computer and the common mode input end of the amplifying circuit and provides a common mode level signal for the amplifying circuit.
Preferably, the host computer writes data into a register of the second digital-to-analog converter, so that the second digital-to-analog converter outputs a common mode level signal.
Compared with the prior art, the utility model has the advantages of it is following:
1. the utility model discloses set up gain resistance adjustment module in decay coefficient selection circuit, this gain resistance adjustment module can carry out digital adjustment to amplifier circuit's decay coefficient, realizes accurate decay coefficient control, to the accurate detection in SOC chip that has analog function, has very big practical value.
2. Use the utility model discloses an analog circuit can expand ATE's detection capability, has expanded equipment inspection chip type, has promoted the utilization ratio of ATE equipment, has very high economic benefits.
3. The utility model discloses a set up single-ended to differential circuit and common mode voltage regulating circuit, can convert single-ended signal into differential signal, realize moving analog signal's whole simultaneously, make it change based on common mode voltage.
4. The utility model discloses before the SOC chip of DUT is given in the final transport of signal, drive the signal with drive circuit, make it under the condition of very big load change, reduce nonlinear distortion, promote the analog circuit performance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments of the present disclosure will be briefly described below, and it is obvious that the drawings in the following description are only a part of the embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present disclosure and the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional gain-selectable amplifier circuit;
FIG. 2 is a modeling diagram of the amplifying circuit of FIG. 1;
fig. 3 is a schematic diagram of the structural principle of the analog circuit of the present invention;
fig. 4 is an amplifying circuit diagram of the analog circuit of the present invention with an attenuation coefficient selecting circuit;
fig. 5 is an amplifying circuit diagram of the analog circuit of the present invention, which has a single-ended to differential circuit and an attenuation factor selecting circuit;
fig. 6 is a schematic diagram of a common mode voltage regulating circuit in an analog circuit according to the present invention;
fig. 7 is a frequency spectrum diagram of an output signal after a signal is input to the analog circuit of the present invention.
Shown in the figure:
10. an attenuation coefficient selection circuit; 11. an input resistance unit; 12. a selector switch; 13. a feedback resistor; 20. a single-ended to differential circuit; 30. an amplifying circuit; 40. a common mode voltage regulating circuit; 50. a drive circuit; 60. and (4) an upper computer.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only some embodiments, but not all embodiments, of the embodiments of the present disclosure. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present disclosure, belong to the protection scope of the embodiments of the present disclosure.
It should be noted that reference to "and/or" in embodiments of the present disclosure is intended to include any and all combinations of one or more of the associated listed items. The terms "first", "second", and the like in the description and claims of the present disclosure and in the drawings are used for distinguishing between different objects and not for limiting a particular order.
It should also be noted that, in the embodiments of the present disclosure, each of the following embodiments may be executed alone, or may be executed in combination with each other, and the embodiments of the present disclosure are not limited specifically.
The technical solutions of the embodiments of the present disclosure are further described by the following detailed description in conjunction with the accompanying drawings.
As shown in fig. 3, an embodiment of the present invention provides an analog circuit with selectable attenuation coefficients, including: the circuit comprises an attenuation coefficient selection circuit 10, a single-ended to differential circuit 20, a common mode voltage regulation circuit 40, an amplification circuit 30 and a drive circuit 50. The attenuation coefficient selection circuit 10 and the common mode voltage adjustment circuit 40 are controlled by the upper computer 60 through the measurement board, and perform related attenuation coefficient selection and common mode voltage control operations. It should be noted that the upper computer 60 may be a PC or ATE, and the measurement board may be understood as a lower computer, and is configured to receive instructions and signals from the upper computer 60 and provide test signals to the analog circuit. Accordingly, the present embodiment provides an analog circuit for conditioning and controlling test signals disposed between the ATE and the SOC chip of the DUT.
Therefore, when testing the SOC chip, the upper computer 60 first controls the attenuation coefficient selection circuit 10 according to actual needs or received instructions to select an attenuation coefficient. The single-ended to differential circuit 20 receives a test signal sent by the upper computer 60 (of course, the test signal is a single-ended signal); the single-ended to differential circuit 20 performs digital-to-analog conversion on the single-ended test signal, converts the single-ended test signal into a differential signal, and transmits the differential signal to the input terminal of the amplifying circuit 30.
Meanwhile, the upper computer 60 controls the common mode voltage regulating circuit 40 to give a common mode level signal according to the requirement of the terminal DUT, and further provides a common mode level for the amplifying circuit 30.
Then, the amplifying circuit 30 receives the differential signal and the common mode level signal, amplifies the differential signal and the common mode level signal, changes the differential signal based on the common mode voltage, and finally outputs the changed differential signal. Specifically, the differential signals are normally sine waves and cosine waves as shown in fig. 6, and when the common mode voltage is Vocm, the sine waves and the cosine waves are respectively subjected to waveform change based on Vocm.
Before the differential signal is finally transmitted to the SOC chip of the DUT, the driving circuit 50 drives the differential signal, so that nonlinear distortion is reduced and the performance of the analog circuit is improved under the condition of a large load variation. Therefore, the utility model discloses to the precision detection of SOC chip that has analog circuit function, have very big use value. The utility model discloses an analog circuit and ATE cooperation during operation can expand the type of ATE equipment inspection chip, promote the utilization ratio of ATE equipment, have very high economic benefits.
Specifically, the attenuation coefficient selection circuit 10 includes two groups of gain resistance adjustment modules, which are respectively connected to two input ends of the amplification circuit 30, and the structures of the two groups of gain resistance adjustment modules or the selection of components are the same.
As shown in fig. 4, the gain resistance adjustment module 10 includes: the amplifier comprises an input resistance unit 11, a selection switch 12 connected between the input resistance unit 11 and the input end of an amplifying circuit 30 to control the input resistance unit 11, and a feedback resistor 13 connected between the output end of the input resistance unit 11 and the output end of the amplifying circuit 30 to realize the operational amplifier following of the amplifying circuit, wherein the input resistance unit 11 is controlled by the selection switch 12 to realize the attenuation coefficient selection of the amplifying circuit. In other words, the input resistance unit 11 in this embodiment is directly connected in series with the feedback resistance 13, and the selection switch 12 is connected between the input resistance unit 11 and the input end of the amplifying circuit 30, and is used for selecting the input resistance unit 11, that is, the attenuation coefficient is selected, and meanwhile, the internal resistance of the selection switch 12 does not affect the input resistance of the amplifying circuit 30, or affect the feedback resistance 13 of the amplifying circuit 30, so that the control accuracy of the attenuation coefficient is ensured. This criterion becomes less important when selecting the internal resistance value of the switch 12. A plurality of selection switches 12 with slightly large internal resistance can be selected, so that the threshold of selecting switch chips is reduced, and the flexibility and the practicability of the circuit are improved.
Preferably, the input resistance unit 11 includes a plurality of resistance units connected in series, where the number of the resistance units and the corresponding resistance value can be selected according to actual requirements. Since the single resistors and the feedback resistors are connected in series, when the selection switch 12 selects the single resistors in the input resistor unit 11, a part of the single resistors are used as input resistors and connected to the input terminal of the amplifying circuit 30 through the selection switch 12, and another part of the single resistors, which are not selected, form a feedback resistor combination together with the feedback resistor 13, and the feedback resistor combination is a resistor which really plays a feedback role.
As shown in fig. 4, in one specific example, the input resistance unit 11 connected to the positive input terminal of the amplification circuit 30 is defined as a first input resistance unit for display distinction, and the input resistance unit 11 connected to the negative input terminal of the amplification circuit 30 is positioned as a second input resistance unit. The first input resistance unit comprises a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4 which are sequentially connected in series; the feedback resistor 13 connected in series with the first input resistor unit is a fifth resistor R5. Accordingly, the second input resistance unit includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9 connected in series in sequence, and the feedback resistor 13 connected in series corresponding to the second input resistance unit is a tenth resistor R10. Wherein: r1 ═ R6, R2 ═ R7, R3 ═ R8, R4 ═ R9, and R5 ═ R10.
In the scheme, the selection switch adopts SPST (single pole single throw) switch, and each resistance single body is correspondingly provided with one SPST element (relay), so that eight relays are correspondingly arranged in the scheme.
The first relay SW1 is provided between the first resistor R1 and the positive input terminal of the amplifier circuit 30, for controlling the first resistor R1.
The second relay SW2 is provided between the second resistor R2 and the positive input terminal of the amplifying circuit 30, for controlling the second resistor R2.
The third relay SW3 is provided between the third resistor R3 and the positive input terminal of the amplifier circuit 30, for controlling the third resistor R3.
The fourth relay SW4 is provided between the fourth resistor R4 and the positive input terminal of the amplifier circuit 30, for controlling the fourth resistor R4.
The fifth relay SW5 is provided between the sixth resistor R6 and the negative input terminal of the amplifier circuit 30, for controlling the sixth resistor R6.
The sixth relay SW6 is provided between the seventh resistor R7 and the negative input terminal of the amplifier circuit 30, for controlling the seventh resistor R7.
The seventh relay SW7 is provided between the eighth resistor R8 and the negative input terminal of the amplifier circuit 30, for controlling the eighth resistor R8.
The eighth relay SW8 is provided between the ninth resistor R9 and the negative input terminal of the amplifying circuit 30, for controlling the ninth resistor R9.
In order to ensure that the input signals of the two input ends of the amplifying circuit 30 are consistent, the relays are set to be 4 groups: SW1 and SW5, SW2 and SW6, SW3 and SW7, and SW4 and SW 8. If it is specified that only 1 group of the 4 groups of relays can be closed at a certain time, the attenuation coefficient selection circuit 10 in the scheme has 4 kinds of gains, namely, the attenuation coefficients can be selected:
if the 4 groups of relays are not limited to only have 1 group closed at a certain time, the attenuation coefficient can be more selected, and the application range is wider. The number of attenuation factor options in the attenuation factor selection circuit 10 depends on the space allowed by the analog circuit. If the circuit pair space limit is small, the selection switch can adopt SPST elements with large size, and then each resistance single body can be controlled independently. This allows any combination of any switch ON/OFF states to be achieved. If the space of the analog circuit is small and a small package needs to be selected, a MUX element (multi-selection switch) in which a plurality of switches are within 1 chip can be employed.
For ATE test equipment, board space is typically limited. In the embodiment of the utility model provides an in order to realize the miniaturization, can choose 2 switch that select more for use 8. The 8-to-2 multi-selection switch is formed by combining two 4-to-1 switches, and the two 4-to-1 switches have a common selection end. The common selection terminal is just suitable for switching the combination of the resistance units in the input resistance unit, so that the space and the resources are saved.
Referring to fig. 5, the single-ended to differential conversion circuit 20 employs a first digital-to-analog converter, which is disposed between the upper computer 60 and the input end of the amplifying circuit 30, and is configured to perform digital-to-analog conversion on a single-ended signal output by the upper computer 60 and transmit the converted single-ended signal to the amplifying circuit 30. Specifically, the positive input end of the amplifier circuit 30 is connected to the single-ended signal, and the negative input end is grounded, so that the single-ended signal is converted into the differential signal. Therefore, the first digital-to-analog converter is used for receiving the digital single-ended signal from the upper computer 60, converting the digital single-ended signal into an analog single-ended signal, and transmitting the analog single-ended signal to the positive input terminal of the amplifying circuit 30, and since the negative input terminal of the amplifying circuit 30 is grounded, the analog single-ended signal is automatically converted into a differential signal and finally output by the amplifying circuit 30.
Referring to fig. 6, the common mode voltage adjusting circuit 40 employs a second digital-to-analog converter, which is disposed between the upper computer 60 and the common mode input terminal Vocm of the amplifying circuit 30, and provides a common mode level signal for the amplifying circuit 30. Specifically, the upper computer 60 writes data into a register of the second digital-to-analog converter, so that the second digital-to-analog converter outputs a precise common mode level signal, and transmits the precise common mode level signal to the common mode input end Vocm of the amplifying circuit 30, and the amplifying circuit 30 processes the common mode level signal and the differential signal in the foregoing to obtain an amplified differential signal based on the common mode level change.
The driver circuit 50 is disposed between the amplifier circuit 30 and the SOC chip of the DUT, and drives the signal with the driver circuit 50, so that nonlinear distortion is reduced and analog circuit performance is improved under a large load variation.
To illustrate the influence of the analog circuit with selectable attenuation coefficient in this embodiment on the actual test, in a specific example, a signal source is input to the input terminal Vin of the analog circuit in fig. 3, and the parameters of the signal source are set as follows: input voltage + -3.75V, input frequency Fin 1kHz, total harmonic distortion plus noise THD + N100 dB.
The output end Vout of the analog circuit in FIG. 3 is tested to test the THD + N index variation of the waveform under various attenuation conditions. When Gain is 1, 1/3, 1/5, and 1/11, the spectrogram of the obtained signal is shown in fig. 7. Therefore, the analog circuit of the present embodiment does not affect the important index of signal harmonic distortion.
The foregoing description is only a preferred embodiment of the disclosed embodiments and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the disclosure in the embodiments of the present disclosure is not limited to the particular combination of the above-described features, but also encompasses other embodiments in which any combination of the above-described features or their equivalents is possible without departing from the scope of the present disclosure. For example, the above features and (but not limited to) the features with similar functions disclosed in the embodiments of the present disclosure are mutually replaced to form the technical solution.
It will be apparent to those skilled in the art that various changes and modifications may be made to the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. An analog circuit with selectable attenuation coefficient, comprising an attenuation coefficient selection circuit and an amplification circuit, wherein the attenuation coefficient selection circuit comprises a gain resistance adjustment module connected to an input terminal of the amplification circuit, and the gain resistance adjustment module comprises: the circuit comprises an input resistance unit, a selection switch and a feedback resistor, wherein the input resistance unit is connected with a plurality of resistance monomers in series, the selection switch is connected between the input resistance unit and the input end of an amplifying circuit to control the input resistance unit, the feedback resistor is connected between the output end of the input resistance unit and the output end of the amplifying circuit to realize the operational amplifier following of the amplifying circuit, and the number of the resistance monomers connected to the input end of the amplifying circuit in the input resistance unit is adjusted through the selection switch to realize the attenuation coefficient selection of the amplifying circuit.
2. The analog circuit with selectable attenuation coefficient of claim 1, further comprising a driving circuit, wherein an input terminal of the driving circuit is connected to an output terminal of the amplifying circuit, and an output terminal of the driving circuit is an output terminal of the analog circuit.
3. The analog circuit with selectable attenuation coefficient according to claim 1, wherein the selection switch is a multi-way selection switch or a single-pole single-throw switch to select the number of the resistor units.
4. The analog circuit with selectable attenuation coefficient according to claim 3, wherein the single-pole single-throw switches are in one-to-one correspondence with the single resistors in the input resistor unit, and each single-pole single-throw switch is correspondingly connected between the output end of the single resistor and the input end of the amplifying circuit.
5. The analog circuit with selectable attenuation coefficient of claim 1, wherein there are two groups of gain resistance adjusting modules, and the two groups of gain resistance adjusting modules are respectively connected to two input terminals of the amplifying circuit.
6. The analog circuit with selectable attenuation coefficient of claim 1, further comprising a single-ended to differential circuit, wherein the single-ended to differential circuit is controlled by a host computer to provide a single-ended signal to one input of the amplifying circuit, and wherein another input of the amplifying circuit is grounded.
7. The analog circuit of claim 6, wherein the single-ended to differential conversion circuit employs a first digital-to-analog converter, and the first digital-to-analog converter is disposed between the upper computer and the input end of the amplifying circuit, and is configured to perform digital-to-analog conversion on the single-ended signal output by the upper computer and transmit the converted single-ended signal to the amplifying circuit.
8. The analog circuit with selectable attenuation coefficient of claim 1, further comprising a common mode voltage adjusting circuit, wherein the common mode voltage adjusting circuit is controlled by a host computer to provide a common mode level signal for the amplifying circuit.
9. The analog circuit of claim 8, wherein the common mode voltage regulator circuit comprises a second digital-to-analog converter disposed between the host computer and the common mode input of the amplifier circuit for providing a common mode level signal to the amplifier circuit.
10. The selectable attenuation factor analog circuit of claim 9, wherein the host computer writes data to a register of the second digital-to-analog converter, thereby causing the second digital-to-analog converter to output a common mode level signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921163410.2U CN210839494U (en) | 2019-07-23 | 2019-07-23 | Analog circuit with selectable attenuation coefficient |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921163410.2U CN210839494U (en) | 2019-07-23 | 2019-07-23 | Analog circuit with selectable attenuation coefficient |
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| CN210839494U true CN210839494U (en) | 2020-06-23 |
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| CN201921163410.2U Active CN210839494U (en) | 2019-07-23 | 2019-07-23 | Analog circuit with selectable attenuation coefficient |
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