CN210838981U - Chip integrating battery charging and discharging control management circuit and electronic product - Google Patents
Chip integrating battery charging and discharging control management circuit and electronic product Download PDFInfo
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- CN210838981U CN210838981U CN201921701511.0U CN201921701511U CN210838981U CN 210838981 U CN210838981 U CN 210838981U CN 201921701511 U CN201921701511 U CN 201921701511U CN 210838981 U CN210838981 U CN 210838981U
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Abstract
A chip and electronic product of integrated battery charge-discharge control management circuit, the chip includes: the input end of the first control unit is used for being connected with a power supply end; the output end of the first level conversion unit is connected with the control end of the first control unit; the input end of the second control unit is connected with the output end of the first control unit, and the output end of the second control unit is used for connecting the anode of the battery; the output end of the second level conversion unit is connected with the control end of the second control unit; the input end of the third control unit is used for being connected between a power supply end and the positive end of the load, and the output end of the third control unit is connected between the output end of the first control unit and the input end of the second control unit; the output end of the third level conversion unit is connected with the control end of the third control unit. The chip can provide better protection for the battery.
Description
Technical Field
The utility model relates to an electricity field especially relates to an integrated battery charge-discharge control management circuit's chip and electronic product.
Background
In various electronic products, particularly mobile electronic products, an internal battery is often provided. Such electronic products usually require a corresponding charge management circuit, and two chips are usually required in the circuit.
As shown in fig. 1, the conventional electronic product includes a charging management chip 10 for managing battery charging; one is an output management chip 20 for controlling battery discharge. The power supply end Input is used for accessing corresponding charging voltage, the charging voltage accessed by the charger is introduced into the charging management chip 10 from the Vin position, the chip 10 is connected to the positive pole of the battery BAT, and the negative pole of the battery BAT is connected to the reference ground. The chip 20 is also connected to the positive electrode of the battery BAT, while the positive electrode of the battery BAT is connected to the positive electrode of the load L (which may be a lamp source, as shown in fig. 1), and the negative electrode of the load L is connected to another connection position of the chip 20. When the charge management chip 10 detects the state of the battery BAT voltage, the charge is turned on when the battery BAT voltage is lower than a set value. When the battery BAT voltage reaches a set value, the charging is turned off. And the output management chip 20 controls the magnitude and switching state of the output current.
In such an electronic product, since the charge management chip 10 and the output management chip 20 are in an independent control mode, when the charger (power supply terminal Input) is connected to the power supply, the battery BAT is repeatedly charged and discharged, and the service life of the battery is reduced.
SUMMERY OF THE UTILITY MODEL
The utility model provides a problem provide an integrated battery charge-discharge control management circuit's chip and electronic product to protect the battery in the electronic product better.
In order to solve the above problem, the utility model provides an integrated battery charge-discharge control management circuit's chip, include: the input end of the first control unit is used for being connected with a power supply end; the output end of the first level conversion unit is connected with the control end of the first control unit; the input end of the second control unit is connected with the output end of the first control unit, and the output end of the second control unit is used for being connected with the anode of a battery; the output end of the second level conversion unit is connected with the control end of the second control unit; a third control unit, an input end of the third control unit is used for being connected between the power supply terminal and a positive end of a load, and an output end of the third control unit is connected between an output end of the first control unit and an input end of the second control unit; the output end of the third level conversion unit is connected with the control end of the third control unit; the driving signal end of the charging control unit is connected between the output end of the second level conversion unit and the control end of the second control unit; the input end of the output management unit is used for being connected with the negative end of a load, and the output end of the output management unit is connected with a reference ground.
Optionally, the first control unit is a first enhancement type NMOS transistor, a source of the first enhancement type NMOS transistor is used as an input end of the first control unit, a drain of the first enhancement type NMOS transistor is used as an output end of the first control unit, and a gate of the first enhancement type NMOS transistor is used as a control end of the first control unit; the first level shifting unit is a first charge pump.
Optionally, the second control unit is a second enhancement type NMOS transistor, a source of the second enhancement type NMOS transistor is used as an input end of the second control unit, a drain of the second enhancement type NMOS transistor is used as an output end of the second control unit, and a gate of the second enhancement type NMOS transistor is used as a control end of the second control unit; the second level shifting unit is a second charge pump.
Optionally, the third control unit is a third enhancement type NMOS transistor, a source of the third enhancement type NMOS transistor is used as an input end of the third control unit, a drain of the third enhancement type NMOS transistor is used as an output end of the third control unit, and a gate of the third enhancement type NMOS transistor is used as a control end of the third control unit; the third level shifting unit is a third charge pump.
Optionally, the charge control unit includes a first amplifier, a fourth enhancement NMOS transistor, and a first pull-down resistor; the positive phase input end of the first amplifier is used as a current detection end, the negative phase input end of the first amplifier is used as a current reference end, and the output end of the first amplifier is connected with the grid electrode of the fourth enhancement type NMOS tube; the drain electrode of the fourth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; the first end of the first pull-down resistor is connected with the source electrode of the fourth enhancement type NMOS tube, and the second end of the first pull-down resistor is connected with the reference ground; the charging control unit further comprises a second amplifier, a fifth enhancement type NMOS tube and a second pull-down resistor; the positive phase input end of the second amplifier is used as a battery feedback end, the negative phase input end of the second amplifier is used as a voltage reference end, and the output end of the second amplifier is connected with the grid electrode of the fifth enhancement type NMOS tube; the drain electrode of the fifth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; a first end of the second pull-down resistor is connected with a source electrode of the fifth enhancement type NMOS tube, and a second end of the second pull-down resistor is connected with a reference ground; the output management unit comprises a sixth enhancement type NMOS tube, the drain electrode of the sixth enhancement type NMOS tube is connected with the negative end of the load, and the source electrode of the sixth enhancement type NMOS tube is connected with the reference ground.
In order to solve the above problem, the utility model also provides an electronic product, include: a power supply end; a load; a battery; the chip of the integrated battery charge-discharge control management circuit, the said chip includes: the input end of the first control unit is connected with the power supply end; the output end of the first level conversion unit is connected with the control end of the first control unit; the input end of the second control unit is connected with the output end of the first control unit, and the output end of the second control unit is connected with the anode of the battery; the output end of the second level conversion unit is connected with the control end of the second control unit; a third control unit, an input terminal of the third control unit being connected between the power supply terminal and a positive terminal of the load, and an output terminal of the third control unit being connected between an output terminal of the first control unit and an input terminal of the second control unit; the output end of the third level conversion unit is connected with the control end of the third control unit; the driving signal end of the charging control unit is connected between the output end of the second level conversion unit and the control end of the second control unit; the input end of the output management unit is connected with the negative end of the load, and the output end of the output management unit is connected with the reference ground.
Optionally, the first control unit is a first enhancement type NMOS transistor, a source of the first enhancement type NMOS transistor is used as an input end of the first control unit, a drain of the first enhancement type NMOS transistor is used as an output end of the first control unit, and a gate of the first enhancement type NMOS transistor is used as a control end of the first control unit; the first level conversion unit is a first charge pump; the second control unit is a second enhancement type NMOS tube, a source electrode of the second enhancement type NMOS tube is used as an input end of the second control unit, a drain electrode of the second enhancement type NMOS tube is used as an output end of the second control unit, and a grid electrode of the second enhancement type NMOS tube is used as a control end of the second control unit; the second level conversion unit is a second charge pump; the third control unit is a third enhancement type NMOS tube, a source electrode of the third enhancement type NMOS tube is used as an input end of the third control unit, a drain electrode of the third enhancement type NMOS tube is used as an output end of the third control unit, and a grid electrode of the third enhancement type NMOS tube is used as a control end of the third control unit; the third level shifting unit is a third charge pump.
Optionally, the charge control unit includes a first amplifier, a fourth enhancement NMOS transistor, and a first pull-down resistor; the positive phase input end of the first amplifier is used as a current detection end, the negative phase input end of the first amplifier is used as a current reference end, and the output end of the first amplifier is connected with the grid electrode of the fourth enhancement type NMOS tube; the drain electrode of the fourth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; the first end of the first pull-down resistor is connected with the source electrode of the fourth enhancement type NMOS tube, and the second end of the first pull-down resistor is connected with the reference ground; the charging control unit further comprises a second amplifier, a fifth enhancement type NMOS tube and a second pull-down resistor; the positive phase input end of the second amplifier is used as a battery feedback end, the negative phase input end of the second amplifier is used as a voltage reference end, and the output end of the second amplifier is connected with the grid electrode of the fifth enhancement type NMOS tube; the drain electrode of the fifth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; a first end of the second pull-down resistor is connected with a source electrode of the fifth enhancement type NMOS tube, and a second end of the second pull-down resistor is connected with a reference ground; the output management unit comprises a sixth enhancement type NMOS tube, the drain electrode of the sixth enhancement type NMOS tube is connected with the negative end of the load, and the source electrode of the sixth enhancement type NMOS tube is connected with the reference ground.
Optionally, the electronic product further includes a voltage dividing resistor, a first end of the voltage dividing resistor is connected to the power supply end, and a second end of the voltage dividing resistor is connected to the positive end of the load.
Optionally, the electronic product is a mobile desk lamp, and the load is a light source.
The utility model discloses in one of them aspect of technical scheme, provide an electronic product that can manage the battery charge-discharge path, electronic product can be through detecting input power, and the charging-discharge path is controlled, has avoided charging repeatedly and discharging of the inside battery of electronic product, has improved the life-span of battery. In addition, in the electronic product, a circuit which can be realized only by two chips at present is integrated on one chip by design, so that the integration level of a system is improved, and the area of a circuit board is reduced.
In another aspect of the technical solution of the present invention, the specific electronic product can be a mobile desk lamp. The existing desk lamp can be charged while a battery is used, and the service life of the battery is shortened in repeated charging and discharging when the battery is connected with an external power supply. In the mobile desk lamp in the embodiment, the charging and discharging paths of the battery are managed by the management chip, so that the charging and discharging are managed on one chip, the situation that the battery is repeatedly charged when being connected with an external power supply is avoided, and the service life of the battery is prolonged.
Drawings
FIG. 1 is a circuit diagram of a conventional electronic product;
fig. 2 is a schematic circuit diagram of an electronic product according to an embodiment.
Detailed Description
The service life of the self-contained battery of the electronic product is continuously reduced along with the increase of the charging and discharging times. In battery application systems, there are often applications where the battery is charged and discharged simultaneously. This is because, in the prior art, even if an external power source is directly connected to a load, the battery may discharge (supply) power to the load, and at this time, the battery level may decrease, and once the battery level decreases below a set value, the battery may enter a charged state. Thus, the charging and discharging can be simultaneously started, and the charging is stopped until the electric quantity of the battery reaches the set value. This situation is repeated, and the battery is repeatedly charged and discharged, which is disadvantageous to the life span of the battery.
Therefore, the utility model provides a new integrated battery charge-discharge control management circuit's chip and electronic product to solve the not enough of above-mentioned existence.
For a clearer illustration, the present invention will be described in detail with reference to the accompanying drawings.
An embodiment of the present invention provides an electronic product, please refer to fig. 2, which includes:
a power supply terminal Input; a load L; a battery BAT; the chip 100 of the integrated battery charge-discharge control management circuit, wherein the chip 100 includes:
the Input end of the first control unit (not labeled) is connected with a power supply end Input;
the output end of the first level conversion unit (not labeled) is connected with the control end of the first control unit (not labeled);
the input end of the second control unit (not labeled) is connected with the output end of the first control unit (not labeled), the output end of the second control unit (not labeled) is connected with the positive electrode of the battery BAT, and the negative electrode of the battery BAT is connected with the reference ground;
the output end of the second level conversion unit (not labeled) is connected with the control end of the second control unit (not labeled);
a third control unit (not labeled), an Input end of the third control unit (not labeled) being connected between the power supply terminal Input and the positive terminal of the load L, an output end of the third control unit (not labeled) being connected between an output end of the first control unit (not labeled) and an Input end of the second control unit (not labeled);
a third level conversion unit (not labeled), wherein an output end of the third level conversion unit (not labeled) is connected with a control end of a third control unit (not labeled);
a charging control unit 110, wherein a driving signal end of the charging control unit 110 is connected between an output end of a second level conversion unit (not labeled) and a control end of the second control unit (not labeled);
and an input end of the output management unit 120 is connected with a negative end of the load L, and an output end of the output management unit 120 is connected with a reference ground.
In the electronic product of this embodiment, the first control unit (not labeled) is a first enhancement NMOS transistor Q1, the source of the first enhancement NMOS transistor Q1 is used as the input terminal of the first control unit (not labeled) (the position of the access chip 100 is shown as Vin1 in fig. 2), the drain of the first enhancement NMOS transistor Q1 is used as the output terminal of the first control unit (not labeled), and the gate of the first enhancement NMOS transistor Q1 is used as the control terminal of the first control unit (not labeled); the first level shifting unit (not labeled) is a first charge pump CP 1.
In the electronic product of this embodiment, the second control unit (not labeled) is a second enhancement type NMOS transistor Q2, a source of the second enhancement type NMOS transistor Q2 is used as an input end of the second control unit (not labeled) (the position of the input chip 100 is shown as Vin2 in fig. 2), a drain of the second enhancement type NMOS transistor Q2 is used as an output end of the second control unit (not labeled) (the position of the output chip 100 is shown as Iout in fig. 2), and the output end is connected to the positive electrode of the battery BAT, so that the output end of the second control unit (not labeled) is connected to the positive electrode of the battery BAT; the gate of the second enhancement type NMOS transistor Q2 is used as the control terminal of a second control unit (not labeled); the second level shifting unit (not labeled) is a second charge pump CP 2.
In the electronic product of this embodiment, the third control unit (not labeled) is a third enhancement mode NMOS transistor Q3, the source of the third enhancement mode NMOS transistor Q3 is used as the input terminal of the third control unit (not labeled), the drain of the third enhancement mode NMOS transistor Q3 is used as the output terminal of the third control unit (not labeled), and the gate of the third enhancement mode NMOS transistor Q3 is used as the control terminal of the third control unit (not labeled); the third level shifting unit (not labeled) is a third charge pump CP 3.
In the electronic product of the embodiment, the charging control unit 110 includes a first amplifier C1, a fourth enhancement NMOS transistor Q4, and a first pull-down resistor R1; the positive phase input end of the first amplifier C1 is used as a current detection end, the negative phase input end of the first amplifier C1 is used as a current reference end, and the output end of the first amplifier C1 is connected with the grid electrode of the fourth enhancement type NMOS transistor Q4; the drain of the fourth enhancement type NMOS transistor Q4 is connected between the output terminal of the second charge pump CP2 and the control terminal of the second control unit (not labeled); a first end of the first pull-down resistor R1 is connected with the source electrode of the fourth enhancement type NMOS transistor Q4, and a second end of the first pull-down resistor R1 is connected with the reference ground;
in the electronic product of the embodiment, the charging control unit 110 includes a second amplifier C2, a fifth enhancement NMOS transistor Q5, and a second pull-down resistor R2; the positive phase input end of the second amplifier C2 is used as the battery BAT feedback end, the negative phase input end of the second amplifier C2 is used as the voltage reference end, and the output end of the second amplifier C2 is connected with the grid electrode of the fifth enhancement type NMOS transistor Q5; the drain of the fifth enhancement type NMOS transistor Q5 is connected between the output terminal of the second charge pump CP2 and the control terminal of the second control unit (not labeled); the first end of the second pull-down resistor R2 is connected to the source of the fifth enhancement NMOS transistor Q5, and the second end of the second pull-down resistor R2 is connected to ground.
In the electronic product of this embodiment, the output management unit 120 includes a sixth enhancement mode NMOS transistor Q6, a drain of the sixth enhancement mode NMOS transistor Q6 is connected to a negative terminal of the load L (the position of the connection chip 100 is shown as Vin3 in fig. 2), a source of the sixth enhancement mode NMOS transistor Q6 is connected to ground, and a gate of the sixth enhancement mode NMOS transistor Q6 is connected to the output control circuit CL.
In the electronic product of this embodiment, the working process is as follows:
when the chip 100 detects an input power (which may be detected by the Vin1 position in general, and corresponding detection logic is not shown, as in the prior art), the first charge pump CP1 (the signal for controlling the first charge pump CP1 is also provided by corresponding logic) turns on the first enhancement NMOS transistor Q1, and the third charge pump CP3 turns off the third enhancement NMOS transistor Q3; the second charge pump CP2 sets a charging current by controlling the gate voltage of the second enhancement type NMOS transistor Q2 according to the voltage of the battery BAT, and when the voltage of the battery BAT does not reach a set value, the second enhancement type NMOS transistor Q2 is kept on, and the power supply terminal Input charges the battery BAT; when the voltage of the battery BAT reaches a set value, the second charge pump CP2 turns off the second enhancement NMOS transistor Q2, and the charging is finished; the load L is connected with the voltage provided by the power supply end Input, namely the load L is only powered by the power supply end Input at the moment; that is to say, at this time, the discharging loop from the battery BAT to the output is in the off state at the position of the third enhancement type NMOS transistor Q3, so the battery BAT does not supply power to the load L, and after the battery BAT is charged to a certain voltage value, only the charging is stopped, and the situation that the voltage is reduced and the charging is needed due to the power supply does not occur immediately, so the phenomena of repeated charging and discharging of the battery BAT do not occur, and the service life of the battery is prolonged;
when the chip 100 detects that there is no input power, the first charge pump CP1 turns off the first enhancement NMOS transistor Q1, the second charge pump CP2 turns on the second enhancement NMOS transistor Q2, and the third charge pump CP3 turns on the third enhancement NMOS transistor Q3, at this time, the load L is powered by the battery BAT.
In this embodiment, the first charge pump CP1, the second charge pump CP2, and the third charge pump CP3 are all charge pumps fabricated inside the chip 100. The charge pump is composed of a switch and a capacitor, and can be completely integrated in the chip. And the charge pump can ensure that correspondingly required high voltage is provided for the grid electrode of each corresponding NMOS tube, and the realization of corresponding control action is ensured. Specifically, in order to ensure the corresponding circuit performance, the source voltage of each NMOS transistor is usually directly raised to the voltage provided by the power supply terminal Input, which is usually 5V, and at this time, it is necessary to increase the voltage of about 7.5V or more at the gate of the corresponding NMOS transistor to ensure that the corresponding NMOS transistor is turned on. In the embodiment, the charge pump is used to provide a voltage of about 10V even for the gate of the NMOS transistor, so as to ensure the turn-on operation of the corresponding NMOS transistor.
It should be noted that in this embodiment, as the turn-on condition of the first enhancement NMOS transistor Q1, when the chip 100 detects that the power supply terminal Input has an Input voltage, and the circuit has no other abnormality (the abnormality includes an overvoltage abnormality, an overcurrent abnormality, a high-temperature abnormality, and the like), at this time, the logic circuit inside the chip 100 further turns on the first enhancement NMOS transistor Q1 by using the first charge pump CP1 through controlling the first charge pump CP 1.
It should be noted that the turn-on condition of the second enhancement NMOS transistor Q2 is the cooperation between the internal logic circuit of the chip 100 and the charging control unit 110. Therefore, in fig. 2, a control terminal (the control terminal may output a DRV signal, a driving signal) of the charging control unit 110 is shown to be connected between the gate of the second enhancement NMOS transistor Q2 and the output terminal of the second charge pump CP 2. The action mechanism of the charging control unit 110 generally includes the combined action of current and voltage, which belongs to the prior art and is not described herein again.
In the electronic product of this embodiment, each enhancement NMOS transistor is used as a corresponding control unit, because the NMOS transistor has a small impedance, the impedance requirement can be ensured by manufacturing the corresponding NMOS transistor with a small chip area, and thus the chip area can be controlled to be small.
In this embodiment, the battery BAT may be a lithium battery.
In the electronic product of this embodiment, the electronic product is a mobile desk lamp, and the load L is a light source. In other embodiments, the electronic product may also be other electronic products such as a radio.
The electronic product of this embodiment further includes a voltage dividing resistor R0, wherein a first end of the voltage dividing resistor R0 is connected to the power supply terminal Input, and a second end of the voltage dividing resistor R0 is connected to the positive terminal of the load L. The voltage dividing resistor R0 may function to protect the chip 100 and reduce power consumption on the chip 100. Since, when the load L is operating, the voltage dividing resistor R0, the load L and the output management unit 120 of the chip 100 correspond to a series structure, the voltage dividing resistor R0 can reduce the current of the circuit in this series structure, thereby reducing the power consumption consumed by the management unit 120, i.e., the power consumption falling on the chip 100. Specifically, when the electronic product is a mobile desk lamp, the resistance of the voltage dividing resistor R0 may be 1 Ω -2 Ω.
The electronic product of the embodiment relates to a battery charging and discharging management system, in particular to battery charging and discharging path management applied to a mobile desk lamp. The content mentioned in the implementation can be applied to the mobile desk lamp, so that the service life of the battery is prolonged, the integration level of the system is improved, and the area of the circuit board is reduced.
In the electronic product provided by this embodiment, an electronic product capable of managing a battery charge/discharge path is provided, and the electronic product can control the charge/discharge path by detecting an input power supply, thereby avoiding repeated charge and discharge of a battery inside the electronic product, and improving the service life of the battery. In addition, in the electronic product provided by this embodiment, the circuit that can be implemented only by two chips at present is integrated on one chip by design, so that the integration level of the system is improved, and the area of the circuit board is reduced.
In the electronic product provided by this embodiment, a specific electronic product may be a mobile desk lamp. The existing desk lamp can be charged while a battery is used, and the service life of the battery is shortened in repeated charging and discharging when the battery is connected with an external power supply. In the mobile desk lamp in this embodiment, the battery charging and discharging path management chip (i.e., the chip 100) is applied, so that charging and discharging are managed on one chip, thereby avoiding the situation that the battery is repeatedly charged when being connected with an external power supply and prolonging the service life of the battery.
As can be seen from the related contents of the electronic product, the present embodiment also provides a chip 100 integrated with a battery charging/discharging control management circuit, which includes:
the Input end of the first control unit (not labeled) is used for being connected with a power supply end Input;
the output end of the first level conversion unit (not labeled) is connected with the control end of the first control unit (not labeled);
the input end of the second control unit (not labeled) is connected with the output end of the first control unit (not labeled), and the output end of the second control unit (not labeled) is used for being connected with the positive electrode of the battery BAT;
the output end of the second level conversion unit (not labeled) is connected with the control end of the second control unit (not labeled);
a third control unit (not labeled), an Input end of the third control unit (not labeled) is used for being connected between the power supply end Input and the positive end of the load L, and an output end of the third control unit (not labeled) is connected between an output end of the first control unit (not labeled) and an Input end of the second control unit (not labeled);
a third level conversion unit (not labeled), wherein an output end of the third level conversion unit (not labeled) is connected with a control end of a third control unit (not labeled);
a charging control unit 110, wherein a driving signal end of the charging control unit 110 is connected between an output end of a second level conversion unit (not labeled) and a control end of the second control unit (not labeled);
and an input end of the output management unit 120 is used for being connected with a negative end of the load L, and an output end of the output management unit 120 is connected with a reference ground.
In this embodiment, the first control unit (not labeled) is a first enhancement NMOS transistor Q1, the source of the first enhancement NMOS transistor Q1 is used as the input terminal of the first control unit (not labeled), the drain of the first enhancement NMOS transistor Q1 is used as the output terminal of the first control unit (not labeled), and the gate of the first enhancement NMOS transistor Q1 is used as the control terminal of the first control unit (not labeled); the first level shifting unit (not labeled) is a first charge pump CP 1.
In this embodiment, the second control unit (not labeled) is a second enhancement type NMOS transistor Q2, the source of the second enhancement type NMOS transistor Q2 is used as the input terminal of the second control unit (not labeled), the drain of the second enhancement type NMOS transistor Q2 is used as the output terminal of the second control unit (not labeled), and the gate of the second enhancement type NMOS transistor Q2 is used as the control terminal of the second control unit (not labeled); the second level shifting unit (not labeled) is a second charge pump CP 2.
In this embodiment, the third control unit (not labeled) is a third enhancement mode NMOS transistor Q3, the source of the third enhancement mode NMOS transistor Q3 is used as the input terminal of the third control unit (not labeled), the drain of the third enhancement mode NMOS transistor Q3 is used as the output terminal of the third control unit (not labeled), and the gate of the third enhancement mode NMOS transistor Q3 is used as the control terminal of the third control unit (not labeled); the third level shifting unit (not labeled) is a third charge pump CP 3.
In this embodiment, the charge control unit 110 includes a first amplifier C1, a fourth enhancement NMOS transistor Q4, and a first pull-down resistor R1; the positive phase input end of the first amplifier C1 is used as a current detection end, the negative phase input end of the first amplifier C1 is used as a current reference end, and the output end of the first amplifier C1 is connected with the grid electrode of the fourth enhancement type NMOS transistor Q4; the drain of the fourth enhancement type NMOS transistor Q4 is connected between the output terminal of the second charge pump CP2 and the control terminal of the second control unit (not labeled); the first end of the first pull-down resistor R1 is connected to the source of the fourth enhancement NMOS transistor Q4, and the second end of the first pull-down resistor R1 is connected to ground.
In this embodiment, the charging control unit 110 further includes a second amplifier C2, a fifth enhancement NMOS transistor Q5, and a second pull-down resistor R2; the positive phase input end of the second amplifier C2 is used as the battery BAT feedback end, the negative phase input end of the second amplifier C2 is used as the voltage reference end, and the output end of the second amplifier C2 is connected with the grid electrode of the fifth enhancement type NMOS transistor Q5; the drain of the fifth enhancement type NMOS transistor Q5 is connected between the output terminal of the second charge pump CP2 and the control terminal of the second control unit (not labeled); the first end of the second pull-down resistor R2 is connected to the source of the fifth enhancement NMOS transistor Q5, and the second end of the second pull-down resistor R2 is connected to ground.
In this embodiment, the output management unit 120 includes a sixth enhancement mode NMOS transistor Q6, a drain of the sixth enhancement mode NMOS transistor Q6 is connected to a negative terminal of the load L, a source of the sixth enhancement mode NMOS transistor Q6 is connected to ground, and a gate of the sixth enhancement mode NMOS transistor Q6 is connected to the output control circuit CL.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.
Claims (10)
1. A chip of an integrated battery charge-discharge control management circuit is characterized by comprising:
the input end of the first control unit is used for being connected with a power supply end;
the output end of the first level conversion unit is connected with the control end of the first control unit;
the input end of the second control unit is connected with the output end of the first control unit, and the output end of the second control unit is used for being connected with the anode of a battery;
the output end of the second level conversion unit is connected with the control end of the second control unit;
a third control unit, an input end of the third control unit is used for being connected between the power supply terminal and a positive end of a load, and an output end of the third control unit is connected between an output end of the first control unit and an input end of the second control unit;
the output end of the third level conversion unit is connected with the control end of the third control unit;
the driving signal end of the charging control unit is connected between the output end of the second level conversion unit and the control end of the second control unit;
the input end of the output management unit is used for being connected with the negative end of a load, and the output end of the output management unit is connected with a reference ground.
2. The chip of claim 1, wherein the first control unit is a first enhancement mode NMOS transistor, a source of the first enhancement mode NMOS transistor serves as an input terminal of the first control unit, a drain of the first enhancement mode NMOS transistor serves as an output terminal of the first control unit, and a gate of the first enhancement mode NMOS transistor serves as a control terminal of the first control unit; the first level shifting unit is a first charge pump.
3. The chip of claim 1, wherein the second control unit is a second enhancement type NMOS transistor, a source of the second enhancement type NMOS transistor serves as an input terminal of the second control unit, a drain of the second enhancement type NMOS transistor serves as an output terminal of the second control unit, and a gate of the second enhancement type NMOS transistor serves as a control terminal of the second control unit; the second level shifting unit is a second charge pump.
4. The chip of claim 1, wherein the third control unit is a third enhancement mode NMOS transistor, a source of the third enhancement mode NMOS transistor serves as an input terminal of the third control unit, a drain of the third enhancement mode NMOS transistor serves as an output terminal of the third control unit, and a gate of the third enhancement mode NMOS transistor serves as a control terminal of the third control unit; the third level shifting unit is a third charge pump.
5. The chip of claim 3, wherein:
the charging control unit comprises a first amplifier, a fourth enhancement type NMOS tube and a first pull-down resistor; the positive phase input end of the first amplifier is used as a current detection end, the negative phase input end of the first amplifier is used as a current reference end, and the output end of the first amplifier is connected with the grid electrode of the fourth enhancement type NMOS tube; the drain electrode of the fourth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; the first end of the first pull-down resistor is connected with the source electrode of the fourth enhancement type NMOS tube, and the second end of the first pull-down resistor is connected with the reference ground;
the charging control unit further comprises a second amplifier, a fifth enhancement type NMOS tube and a second pull-down resistor; the positive phase input end of the second amplifier is used as a battery feedback end, the negative phase input end of the second amplifier is used as a voltage reference end, and the output end of the second amplifier is connected with the grid electrode of the fifth enhancement type NMOS tube; the drain electrode of the fifth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; a first end of the second pull-down resistor is connected with a source electrode of the fifth enhancement type NMOS tube, and a second end of the second pull-down resistor is connected with a reference ground;
the output management unit comprises a sixth enhancement type NMOS tube, the drain electrode of the sixth enhancement type NMOS tube is connected with the negative end of the load, and the source electrode of the sixth enhancement type NMOS tube is connected with the reference ground.
6. An electronic product, comprising:
a power supply end;
a load;
a battery;
the chip of the integrated battery charge-discharge control management circuit, the said chip includes:
the input end of the first control unit is connected with the power supply end;
the output end of the first level conversion unit is connected with the control end of the first control unit;
the input end of the second control unit is connected with the output end of the first control unit, and the output end of the second control unit is connected with the anode of the battery;
the output end of the second level conversion unit is connected with the control end of the second control unit;
a third control unit, an input terminal of the third control unit being connected between the power supply terminal and a positive terminal of the load, and an output terminal of the third control unit being connected between an output terminal of the first control unit and an input terminal of the second control unit;
the output end of the third level conversion unit is connected with the control end of the third control unit;
the driving signal end of the charging control unit is connected between the output end of the second level conversion unit and the control end of the second control unit;
the input end of the output management unit is connected with the negative end of the load, and the output end of the output management unit is connected with the reference ground.
7. The electronic product of claim 6, wherein:
the first control unit is a first enhancement type NMOS tube, a source electrode of the first enhancement type NMOS tube is used as an input end of the first control unit, a drain electrode of the first enhancement type NMOS tube is used as an output end of the first control unit, and a grid electrode of the first enhancement type NMOS tube is used as a control end of the first control unit; the first level conversion unit is a first charge pump;
the second control unit is a second enhancement type NMOS tube, a source electrode of the second enhancement type NMOS tube is used as an input end of the second control unit, a drain electrode of the second enhancement type NMOS tube is used as an output end of the second control unit, and a grid electrode of the second enhancement type NMOS tube is used as a control end of the second control unit; the second level conversion unit is a second charge pump;
the third control unit is a third enhancement type NMOS tube, a source electrode of the third enhancement type NMOS tube is used as an input end of the third control unit, a drain electrode of the third enhancement type NMOS tube is used as an output end of the third control unit, and a grid electrode of the third enhancement type NMOS tube is used as a control end of the third control unit; the third level shifting unit is a third charge pump.
8. The electronic product of claim 7, wherein:
the charging control unit comprises a first amplifier, a fourth enhancement type NMOS tube and a first pull-down resistor; the positive phase input end of the first amplifier is used as a current detection end, the negative phase input end of the first amplifier is used as a current reference end, and the output end of the first amplifier is connected with the grid electrode of the fourth enhancement type NMOS tube; the drain electrode of the fourth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; the first end of the first pull-down resistor is connected with the source electrode of the fourth enhancement type NMOS tube, and the second end of the first pull-down resistor is connected with the reference ground;
the charging control unit further comprises a second amplifier, a fifth enhancement type NMOS tube and a second pull-down resistor; the positive phase input end of the second amplifier is used as a battery feedback end, the negative phase input end of the second amplifier is used as a voltage reference end, and the output end of the second amplifier is connected with the grid electrode of the fifth enhancement type NMOS tube; the drain electrode of the fifth enhancement type NMOS tube is connected between the output end of the second charge pump and the control end of the second control unit; a first end of the second pull-down resistor is connected with a source electrode of the fifth enhancement type NMOS tube, and a second end of the second pull-down resistor is connected with a reference ground;
the output management unit comprises a sixth enhancement type NMOS tube, the drain electrode of the sixth enhancement type NMOS tube is connected with the negative end of the load, and the source electrode of the sixth enhancement type NMOS tube is connected with the reference ground.
9. The electronic product according to claim 6, further comprising a voltage dividing resistor, wherein a first terminal of the voltage dividing resistor is connected to the power supply terminal, and a second terminal of the voltage dividing resistor is connected to a positive terminal of the load.
10. The electronic product according to any one of claims 6 to 9, wherein the electronic product is a mobile desk lamp, and the load is a light source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921701511.0U CN210838981U (en) | 2019-10-12 | 2019-10-12 | Chip integrating battery charging and discharging control management circuit and electronic product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921701511.0U CN210838981U (en) | 2019-10-12 | 2019-10-12 | Chip integrating battery charging and discharging control management circuit and electronic product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210838981U true CN210838981U (en) | 2020-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921701511.0U Active CN210838981U (en) | 2019-10-12 | 2019-10-12 | Chip integrating battery charging and discharging control management circuit and electronic product |
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| Country | Link |
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| CN (1) | CN210838981U (en) |
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2019
- 2019-10-12 CN CN201921701511.0U patent/CN210838981U/en active Active
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