CN210811035U - An electrocardiogram signal processing chip - Google Patents

Abstract

The present application belongs to the technical field of medical devices, and mainly provides an ECG signal processing chip. The ECG signal processing chip includes a substrate, an ECG signal processing circuit disposed on the surface of the substrate, and an ECG signal processing circuit for packaging the ECG signal. A processing circuit and a package of the substrate; wherein, the ECG signal processing circuit includes an ECG acquisition chip for receiving an ECG signal and amplifying the ECG signal to obtain an ECG amplified signal; A processor chip for receiving the electrocardiographic amplification signal and processing the electrocardiographic amplification signal based on the stored electrocardiographic processing program, and a noise reduction circuit for noise reduction of the signal. By integrating the ECG acquisition chip and the processor chip into an ECG signal processing chip that integrates software and hardware, the problems of excessive noise and complex circuit design caused by multi-level circuits are avoided, and the problems existing in the current development plan are solved. technical problem.

Description

An electrocardiogram signal processing chip

technical field

The present application belongs to the technical field of medical devices, and in particular relates to an electrocardiographic signal processing chip.

Background technique

An electrocardiogram (ECG) system is a widely used medical detection and monitoring device that generates an electrocardiogram waveform. A typical ECG waveform consists of a series of characteristic points represented by the letters P, Q, R, S, and T. The waveform of the Q, R, and S parts as a whole is called a QRS complex. The R wave portion of the QRS complex is the most prominent portion of each cardiac cycle in an ECG signal. In various ECG applications, it is very critical for the ECG system to accurately determine the time point of the R wave peak. A traditional ECG system includes an analog front-end circuit, an analog-to-digital converter (ADC), and a digital signal processor to perform the task of determining the peak value of the R wave.

The electrocardiogram was recognized in the early 19th century. Its hardware acquisition and processing circuit and software algorithm identification have entered a relatively stable development mode in the development of nearly a hundred years. The ECG waveform and heart rate detection results are also commonly used in the existing research and development process. The hardware acquisition circuit has been developed from a multi-chip separated IC circuit to a dedicated IC circuit, and the filtering, fault tolerance and feature point recognition capabilities of the software algorithm are also getting stronger and stronger.

However, in the current development plan, the ECG circuit module has problems such as high noise and complicated circuit design.

Utility model content

The purpose of this application is to provide an ECG signal processing chip, which aims to solve the technical problems existing in the current development scheme.

In order to solve the above technical problems, the present application provides an ECG signal processing chip, the ECG signal processing chip includes: a substrate, an ECG signal processing circuit disposed on the surface of the substrate, and an ECG signal processing circuit for packaging the ECG signal A processing circuit and a package of the substrate; the ECG signal processing circuit includes:

An ECG acquisition chip for receiving ECG signals and amplifying the ECG signals to obtain ECG amplified signals;

A processor chip that is connected to the ECG acquisition chip and used to receive the ECG amplified signal and process the ECG amplified signal based on the stored ECG processing program;

A noise reduction circuit that is connected to the ECG acquisition chip and used for noise reduction of signals.

Optionally, the noise reduction circuit includes: a first capacitor, a first resistor, a second capacitor, a third capacitor and a second resistor;

The first end of the first capacitor is connected to the low-pass filter signal end of the ECG acquisition chip, and the first end of the second capacitor is connected to the reference signal end of the ECG acquisition chip. The power amplification signal end of the acquisition chip, the second end of the second capacitor, the first end of the first capacitor, the first end of the first resistor, the second end of the first resistor, and the The first end of the second resistor is connected in common, the high-pass filter signal end of the ECG acquisition chip is connected to the first end of the third capacitor, the pre-stage output end of the power amplifier signal of the ECG acquisition chip, the The second end of the three capacitors and the second end of the second resistor are connected in common.

Optionally, the ECG signal processing circuit further includes:

The clock signal oscillation circuit is connected with the processor chip and used for providing the clock signal.

Optionally, the clock signal oscillation circuit includes a fourth capacitor, a fifth capacitor and a crystal oscillator;

The first end of the fourth capacitor and the first end of the crystal oscillator are connected to the oscillating signal output end of the processor chip, and the first end of the fifth capacitor is connected to the first end of the crystal oscillator. The two terminals are connected to the oscillating signal input terminal of the processor chip in common, and the second terminal of the fourth capacitor and the second terminal of the fifth capacitor are connected to the ground in common.

Optionally, the model of the ECG acquisition chip is any one of Bit2010-A6, AD8231 and ADS1191.

Optionally, the model of the processor chip is GD32F403.

Optionally, the package body is provided with a plurality of electrodes, and the plurality of electrodes are connected to a plurality of signal terminals of the ECG signal processing circuit in a one-to-one correspondence.

Optionally, the ECG acquisition chip and the processor chip are packaged by a solder ball array.

Optionally, the length of the package body is 5mm-20mm, the width of the package body is 5mm-20mm, and the thickness of the package body is 1mm-5mm.

Optionally, the length of the package body is 9 mm, the width of the package body is 9 mm, and the thickness of the package body is 1.2 mm.

The present application provides an ECG signal processing chip, the ECG signal processing chip includes a substrate, an ECG signal processing circuit disposed on the surface of the substrate, and an ECG signal processing circuit for packaging the ECG signal processing circuit and the substrate. A package body; wherein the ECG signal processing circuit includes an ECG acquisition chip for receiving the ECG signal, amplifying the ECG signal to obtain the ECG amplified signal, receiving the ECG amplified signal, and A processor chip for processing the ECG amplified signal based on a stored ECG processing program, and a noise reduction circuit for noise reduction of the signal. By integrating the ECG acquisition chip and the processor chip into an ECG signal processing chip that integrates software and hardware, the problems of excessive noise and complex circuit design caused by multi-stage circuits are avoided, and the problems in the current development plan are solved. existing technical problems.

Description of drawings

FIG. 1 is a schematic structural diagram of an ECG signal processing circuit according to an embodiment of the present application.

FIG. 2 is a schematic structural diagram of an ECG signal processing circuit according to another embodiment of the present application.

FIG. 3 is a schematic structural diagram of an ECG signal processing circuit according to an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

FIG. 1 is a schematic structural diagram of an ECG signal processing chip provided by an embodiment of the present application. Referring to FIG. 1 , the ECG signal processing chip includes: a substrate, an ECG signal processing circuit disposed on the surface of the substrate, and a package body 100 for packaging the ECG signal processing circuit and the substrate;

The ECG signal processing circuit includes:

an ECG acquisition chip U1 for receiving an ECG signal and amplifying the ECG signal to obtain an ECG amplified signal;

A processor chip U2 that is connected to the ECG acquisition chip and used to receive the ECG amplified signal and process the ECG amplified signal based on the stored ECG processing program;

The noise reduction circuit 101 is connected to the ECG acquisition chip and used for noise reduction of the signal.

In this embodiment, the ECG acquisition chip U1 is used to receive the ECG signal, amplify the ECG signal to obtain the ECG amplified signal, and the processor chip U2 is used to receive the ECG amplified signal, and based on the stored The ECG processing program processes the ECG amplified signal and outputs the corresponding processing results. The ECG processing program is pre-stored in the device chip U2. In the process of ECG signal processing, the ECG signal can be directly received and then the detection result can be output. The user does not need to have the corresponding ECG algorithm expertise, which greatly reduces the difficulty of research and development. and development cycle.

In this embodiment, by connecting the noise reduction circuit 101 to the ECG acquisition chip U1, the noise in the process of ECG signal acquisition and amplification can be reduced, and the error in the ECG test process can be reduced.

In one embodiment, the ECG processing program pre-stored in the processor chip U2 can output corresponding information such as the corresponding ECG waveform, heart rate, and heart rhythm detection result based on the received ECG amplified signal.

In this embodiment, by pre-writing an ECG processing program in the processor chip U2, the ECG processing program calculates and processes the received ECG amplified signal according to its internal algorithm to obtain the corresponding ECG waveform, heart rate and For data such as heart rhythm, further, by processing and analyzing the heart rhythm data, it is judged whether the heart rhythm of the tested person is normal, and if the heart rhythm is abnormal, a corresponding arrhythmia result is output.

Further, in this embodiment, by using the package body 100 to encapsulate the peripheral resistance and capacitance of the ECG acquisition chip U1 and the processor chip U2 and the ECG acquisition chip U1 and the processor chip U2 in one chip, not only the The symmetry of the circuit can be improved to improve the common mode rejection ratio of the ECG signal, and the volume of the product can be greatly reduced, which is convenient for the development and application of wearable products.

Further, integrating the peripheral resistors and capacitors of the ECG acquisition chip U1 and the processor chip U2 into the ECG signal processing chip can also improve the signal-to-noise ratio of the ECG signal by reducing the interference of the power supply signal, thereby improving the signal-to-noise ratio of the ECG signal. Signal quality.

In one embodiment, as shown in FIG. 1 , the noise reduction circuit 101 includes: a first capacitor C1, a first resistor R1, a second capacitor C2, a third capacitor C3 and a second resistor R2;

The first terminal of the first capacitor C1 is connected to the low-pass filter signal terminal LP_OUT of the ECG acquisition chip U1, and the first terminal of the second capacitor C2 is connected to the reference signal terminal VREFCM of the ECG acquisition chip U1. connected, the power amplification signal terminal AMP+ of the ECG acquisition chip U1, the second terminal of the second capacitor C2, the first terminal of the first capacitor C1, the first terminal of the first resistor R1, the The second end of the first resistor R1 and the first end of the second resistor R2 are connected together, and the high-pass filter signal end HP_OUT of the ECG acquisition chip U1 is connected to the first end of the third capacitor C3, so The pre-stage output terminal PRE_OUT of the power amplifier signal of the ECG acquisition chip U1, the second terminal of the third capacitor C3 and the second terminal of the second resistor R2 are connected in common.

In one embodiment, as shown in FIG. 2 , the ECG signal processing circuit further includes: a clock signal oscillation circuit 102 connected to the processor chip U2 and configured to provide a clock signal.

In one embodiment, as shown in FIG. 2 , the clock signal oscillation circuit 102 includes a fourth capacitor C4, a fifth capacitor C5 and a crystal oscillator Z1;

The first end of the fourth capacitor C4 and the first end of the crystal oscillator Z1 are connected to the oscillating signal output end OSC_OUT of the processor chip, and the first end of the fifth capacitor C5 is connected to the crystal The second end of the oscillator Z1 is commonly connected to the oscillation signal input end OSC_IN of the processor chip U2 , and the second end of the fourth capacitor C4 and the second end of the fifth capacitor C5 are commonly connected to ground.

In one embodiment, the model of the ECG acquisition chip U1 is any one of Bit2010-A6, AD8231 and ADS1191.

In one embodiment, the model of the processor chip U2 is GD32F403.

In this embodiment, the ECG acquisition chip U1 and the processor chip U2 are both bare chips, and are welded on the substrate through a flying lead process to achieve electrical connection.

In one embodiment, the package body 100 is provided with a plurality of electrodes, and the plurality of electrodes are connected to a plurality of signal terminals of the ECG signal processing circuit in a one-to-one correspondence.

In this embodiment, the package body 100 is provided with a plurality of electrodes. Referring to FIG. 1 , the signal input end of the ECG acquisition chip U1 is connected to the three ECG signal acquisition electrodes RA and LA respectively through a standard ECG lead wire. and RL connection, wherein the signal input terminal RA of the ECG acquisition chip U1 is connected to the electrode RA on the package body 100 through the third resistor R3, and the signal input terminal LA of the ECG acquisition chip U1 is connected to the package body 100 through the fourth resistor R4. On the electrode LA electrode, the signal terminal RLDINV of the ECG acquisition chip U1 is connected to the first terminal of the sixth capacitor C6, the signal terminal RLDOUT of the ECG acquisition chip U1 and the second terminal of the sixth capacitor C6 are connected to the fifth resistor. The first end of R5 and the second end of the fifth resistor R5 are connected to the electrode RL, wherein, in one application, the electrode RA is used to connect with the right arm of the human body, the electrode LA is connected to the left arm of the human body, and the electrode RL is connected to the human body right leg connection.

In one embodiment, as shown in FIG. 1 , the ground terminal GND of the ECG acquisition chip U1 , the analog circuit ground, and the first terminal of the seventh resistor R7 are connected to the analog circuit ground electrode AGND of the package body 100 , and the seventh The second end of the resistor R7 and the first end of the sixth resistor R6 are connected to the reference voltage signal terminal VREF of the ECG acquisition chip U1, the second end of the sixth resistor and the analog signal power supply terminal of the ECG acquisition chip U1 AVDD and the power amplifier power signal terminal ADC_VDDA of the processor chip U2 are connected to the analog signal power supply electrode AVDD of the package; the current gain terminal ICTRL of the ECG acquisition chip U1 is connected to the port GPIO0 of the processor chip U2, and the ECG acquisition chip chip The port BL_INT of U1 is connected to the port GPIO1 of the processor chip U2, the enable signal terminal EN of the ECG acquisition chip U1 is connected to the port GPIO2 of the processor chip U2, and the port LD_OUT of the ECG acquisition chip U1 is connected to the processor chip U2 The port GPIO4 is connected, and the signal output terminal OUT of the ECG acquisition chip U1 is connected with the signal input terminal AD of the processor chip U2.

In one embodiment, the port GPIO0, the port GPIO1, the port GPIO2, and the port GPIO4 may all be general-purpose IO interfaces of the processor chip U2.

In one embodiment, the port AVD, port AVDPWR, port AVS, port AVD1, and ground port GND of the processor chip U2 are commonly connected to the digital ground electrode DGND on the package body 100, and the ports VDDIO1, VDDIO2, The port VDDPST, the port ADC_VDDIO1 and the port ADC_VDDIO2 are commonly connected to the first digital signal power supply electrode DVDD on the package body 100 , and the port VDDC1 , the port VDDC2 , the port PLL_VDDRFE, the port PLL_VDDRHV, the FLASH_VDDF, the port VDDU1 and the port VDDU2 are commonly connected to the package body 100 The second digital signal power supply electrode DVDD1V8, the enable signal terminal EN of the processor chip U2 and the enable signal electrode EN on the package body 100, the signal terminal SPI_RXD, the signal terminal SPI_TXD, the signal terminal SPI_CLK and the signal terminal of the processor chip U2 The SPI_SS is respectively connected with the electrodes SPI_RXD, the electrode SPI_TXD, the electrode SPI_CLK and the electrode SPI_SS on the package body 100 in a one-to-one correspondence, and the download program ports JTAG_TMS and JTAG_TCK of the processor chip U2 are respectively connected with the electrodes JTAG_TMS and JTAG_TCK on the package body 100 in a one-to-one correspondence , used to obtain the ECG processing program from the host computer, the boot terminal BOOT0 of the processor chip U2 is connected to the boot signal electrode BOOT0 on the package body 100 , the reset signal terminal RESET of the processor chip U2 is connected to the reset signal electrode RESET of the package body 100 connect.

In one embodiment, the oscillating signal output terminal OSC_OUT of the processor chip U2 and the oscillating signal input terminal OSC_IN of the processor chip U2 are respectively connected to the oscillating signal output electrode OSC_OUT and the oscillating signal input electrode OSC_IN on the package body 100 .

In one embodiment, as shown in FIG. 2 , the oscillating signal output terminal OSC_OUT of the processor chip U2 and the oscillating signal input terminal OSC_IN of the processor chip U2 are connected to the clock signal oscillating circuit 102 , and the clock signal oscillating circuit 102 is connected to the package body 100 The ground signal terminal on the GND connection.

In one embodiment, a plurality of electrodes are arranged on the package body 100 in sequence, and the plurality of electrodes may be a plurality of solder balls arranged in sequence on the surface of the package body 100 .

In one embodiment, the ECG acquisition chip U1 and the processor chip U2 are packaged by a solder ball array.

In one embodiment, as shown in FIG. 3 , each side of the package body 100 is provided with a plurality of electrodes, and the plurality of electrodes are used for connection with an external circuit.

3 is a schematic diagram of the overall structure of an ECG signal processing chip provided by an embodiment of the present application. In this embodiment, the length of the package body 100 is 1cm-2cm, and the width of the package body 100 is 1cm-2cm. The thickness of the package body 100 is 1 mm-5 mm. In one embodiment, the length of the package body 100 in this embodiment is 9 mm, the width of the package body 100 is 9 mm, and the thickness of the package body 100 is 1.2 mm.

The present application provides an ECG signal processing chip, the ECG signal processing chip includes a substrate, an ECG signal processing circuit disposed on the surface of the substrate, and an ECG signal processing circuit for packaging the ECG signal processing circuit and the substrate. A package body; wherein the ECG signal processing circuit includes an ECG acquisition chip for receiving the ECG signal, amplifying the ECG signal to obtain the ECG amplified signal, receiving the ECG amplified signal, and A processor chip for processing the ECG amplified signal based on a stored ECG processing program, and a noise reduction circuit for noise reduction of the signal. By integrating the ECG acquisition chip and the processor chip into an ECG signal processing chip that integrates software and hardware, the problems of excessive noise and complex circuit design caused by multi-level circuits are avoided, and the problems existing in the current development plan are solved. technical problem.

The above descriptions are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection of the present application. within the range.

Claims (10)

1. An electrocardiosignal processing chip, characterized in that, electrocardiosignal processing chip includes: the electrocardiosignal processing circuit comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body used for packaging the electrocardiosignal processing circuit and the substrate; the electrocardiosignal processing circuit comprises:

the electrocardio acquisition chip is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals;

the processor chip is connected with the electrocardio acquisition chip and used for receiving the electrocardio amplification signals, processing the electrocardio amplification signals based on a stored electrocardio processing program and outputting corresponding electrocardio waveforms, heart rate and heart rhythm detection results;

and the noise reduction circuit is connected with the electrocardio acquisition chip and is used for reducing noise of signals.

2. The cardiac signal processing chip of claim 1, wherein the noise reduction circuit comprises: the circuit comprises a first capacitor, a first resistor, a second capacitor, a third capacitor and a second resistor;

the first end of the first capacitor is connected with the low-pass filtering signal end of the electrocardio acquisition chip, the first end of the second capacitor is connected with the reference signal end of the electrocardio acquisition chip, the power amplification signal end of the electrocardio acquisition chip, the second end of the second capacitor, the first end of the first resistor, the second end of the first resistor and the first end of the second resistor are connected together, the high-pass filtering signal end of the electrocardio acquisition chip is connected with the first end of the third capacitor, and the power amplification signal preceding-stage output end of the electrocardio acquisition chip, the second end of the third capacitor and the second end of the second resistor are connected together.

3. The cardiac signal processing chip of claim 1, wherein the cardiac signal processing circuit further comprises:

and the clock signal oscillating circuit is connected with the processor chip and used for providing a clock signal.

4. The cardiac signal processing chip according to claim 3, wherein the clock signal oscillating circuit comprises a fourth capacitor, a fifth capacitor, and a crystal oscillator;

the first end of the fourth capacitor and the first end of the crystal oscillator are connected to the oscillation signal output end of the processor chip in a shared mode, the first end of the fifth capacitor and the second end of the crystal oscillator are connected to the oscillation signal input end of the processor chip in a shared mode, and the second end of the fourth capacitor and the second end of the fifth capacitor are connected to the ground in a shared mode.

5. The cardiac signal processing chip according to claim 1, wherein the model of the cardiac acquisition chip is any one of Bit2010-A6, AD8231 and ADS 1191.

6. The cardiac signal processing chip as set forth in claim 1, wherein the processor chip is of type GD32F 403.

7. The ecg signal processing chip of claim 1, wherein the package has a plurality of electrodes, and the plurality of electrodes are connected to the plurality of signal terminals of the ecg signal processing circuit in a one-to-one correspondence.

8. The ecg signal processing chip of claim 1, wherein the ecg collection chip and the processor chip are packaged by a solder ball array.

9. The cardiac signal processing chip according to claim 1, wherein the package has a length of 5mm to 20mm, a width of 5mm to 20mm, and a thickness of 1mm to 5 mm.

10. The cardiac signal processing chip according to claim 9, wherein the package has a length of 9mm, a width of 9mm, and a thickness of 1.2 mm.

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