CN210811035U - Electrocardiosignal processing chip - Google Patents
Electrocardiosignal processing chip Download PDFInfo
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- CN210811035U CN210811035U CN201921275366.4U CN201921275366U CN210811035U CN 210811035 U CN210811035 U CN 210811035U CN 201921275366 U CN201921275366 U CN 201921275366U CN 210811035 U CN210811035 U CN 210811035U
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- 239000003990 capacitor Substances 0.000 claims description 47
- 230000000747 cardiac effect Effects 0.000 claims description 15
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Abstract
The application belongs to the technical field of medical instruments and mainly provides an electrocardiosignal processing chip which comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body used for packaging the electrocardiosignal processing circuit and the substrate; the electrocardiosignal processing circuit comprises an electrocardiosignal acquisition chip, a processor chip and a noise reduction circuit, wherein the electrocardiosignal acquisition chip is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals, the processor chip is used for receiving the electrocardio amplified signals and processing the electrocardio amplified signals based on a stored electrocardio processing program, and the noise reduction circuit is used for reducing noise of the signals. The electrocardiosignal acquisition chip and the processor chip are packaged and integrated into the electrocardiosignal processing chip integrating software and hardware, so that the problems of overlarge noise, complex circuit design and the like caused by a multi-stage circuit are avoided, and the technical problem existing in the development scheme at the present stage is solved.
Description
Technical Field
The application belongs to the technical field of medical equipment, and particularly relates to an electrocardiosignal processing chip.
Background
An Electrocardiogram (ECG) system is a widely used medical detection and monitoring device that produces an ECG waveform. A typical ECG waveform includes a series of feature points represented by the letters P, Q, R, S and T. The waveform of the Q, R and S portions as a whole is referred to as the QRS complex. The R wave portion of the QRS complex is the most prominent portion of each cardiac cycle in an ECG signal. In various ECG applications, it is very critical for the electrocardiogram system to accurately determine the point in time of the R-wave peak. Conventional electrocardiographic systems include analog front end circuitry, analog-to-digital converters (ADCs), and digital signal processors to perform the task of determining the peak value of the R wave.
The electrocardiogram is recognized in the beginning of the 19 th century, a hardware acquisition processing circuit and software algorithm identification of the electrocardiogram enter a stable development mode in the development of the past hundred years, and the way of calculating and processing the electrocardiogram signals through an electrocardiogram processing program to obtain corresponding electrocardiogram waveform and heart rate detection results is also a way commonly adopted in the existing research and development process. The hardware acquisition circuit has been developed from a plurality of separated IC circuits to a special IC circuit, and the filtering, fault tolerance and feature point identification capabilities of software algorithms are stronger and stronger.
However, in the current development scheme, the ECG circuit module has problems of large noise, complicated circuit design, and the like.
SUMMERY OF THE UTILITY MODEL
The application aims to provide an electrocardiosignal processing chip and aims to solve the technical problem existing in the development scheme at the present stage.
In order to solve the above technical problem, the present application provides an electrocardiographic signal processing chip, which includes: the electrocardiosignal processing circuit comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body used for packaging the electrocardiosignal processing circuit and the substrate; the electrocardiosignal processing circuit comprises:
the electrocardio acquisition chip is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals;
the processor chip is connected with the electrocardio acquisition chip and used for receiving the electrocardio amplification signals and processing the electrocardio amplification signals based on a stored electrocardio processing program;
and the noise reduction circuit is connected with the electrocardio acquisition chip and is used for reducing noise of signals.
Optionally, the noise reduction circuit includes: the circuit comprises a first capacitor, a first resistor, a second capacitor, a third capacitor and a second resistor;
the first end of the first capacitor is connected with the low-pass filtering signal end of the electrocardio acquisition chip, the first end of the second capacitor is connected with the reference signal end of the electrocardio acquisition chip, the power amplification signal end of the electrocardio acquisition chip, the second end of the second capacitor, the first end of the first resistor, the second end of the first resistor and the first end of the second resistor are connected together, the high-pass filtering signal end of the electrocardio acquisition chip is connected with the first end of the third capacitor, and the power amplification signal preceding-stage output end of the electrocardio acquisition chip, the second end of the third capacitor and the second end of the second resistor are connected together.
Optionally, the electrical cardiac signal processing circuit further includes:
and the clock signal oscillating circuit is connected with the processor chip and used for providing a clock signal.
Optionally, the clock signal oscillation circuit includes a fourth capacitor, a fifth capacitor, and a crystal oscillator;
the first end of the fourth capacitor and the first end of the crystal oscillator are connected to the oscillation signal output end of the processor chip in a shared mode, the first end of the fifth capacitor and the second end of the crystal oscillator are connected to the oscillation signal input end of the processor chip in a shared mode, and the second end of the fourth capacitor and the second end of the fifth capacitor are connected to the ground in a shared mode.
Optionally, the type of the electrocardiograph acquisition chip is any one of Bit2010-a6, AD8231 and ADs 1191.
Optionally, the model of the processor chip is GD32F 403.
Optionally, a plurality of electrodes are disposed on the package body, and the plurality of electrodes are connected to the plurality of signal terminals of the electrocardiograph signal processing circuit in a one-to-one correspondence manner.
Optionally, the electrocardiograph acquisition chip and the processor chip are packaged by a solder ball array.
Optionally, the length of the package body is 5mm-20mm, the width of the package body is 5mm-20mm, and the thickness of the package body is 1mm-5 mm.
Optionally, the length of the package body is 9mm, the width of the package body is 9mm, and the thickness of the package body is 1.2 mm.
The application provides an electrocardiosignal processing chip, which comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body used for packaging the electrocardiosignal processing circuit and the substrate; the electrocardiosignal processing circuit comprises an electrocardiosignal acquisition chip, a processor chip and a noise reduction circuit, wherein the electrocardiosignal acquisition chip is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals, the processor chip is used for receiving the electrocardio amplified signals and processing the electrocardio amplified signals based on a stored electrocardio processing program, and the noise reduction circuit is used for reducing noise of the signals. The electrocardiosignal acquisition chip and the processor chip are packaged and integrated into the electrocardiosignal processing chip integrating software and hardware, so that the problems of overlarge noise, complex circuit design and the like caused by a multi-stage circuit are avoided, and the technical problem existing in the development scheme at the current stage is solved.
Drawings
Fig. 1 is a schematic structural diagram of an electrocardiograph signal processing circuit according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an electrocardiograph signal processing circuit according to another embodiment of the present application.
Fig. 3 is a schematic structural diagram of an electrical cardiac signal processing circuit according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Fig. 1 is a schematic structural diagram of an electrocardiograph signal processing chip according to an embodiment of the present application, and referring to fig. 1, the electrocardiograph signal processing chip includes: the electrocardiosignal processing circuit comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body 100 used for packaging the electrocardiosignal processing circuit and the substrate;
the electrocardiosignal processing circuit comprises:
the electrocardio acquisition chip U1 is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals;
the processor chip U2 is connected with the electrocardio acquisition chip and used for receiving the electrocardio amplified signals and processing the electrocardio amplified signals based on a stored electrocardio processing program;
and the noise reduction circuit 101 is connected with the electrocardio acquisition chip and is used for reducing noise of signals.
In this embodiment, the electrocardiograph acquisition chip U1 is configured to receive an electrocardiograph signal, amplify the electrocardiograph signal to obtain an electrocardiograph amplified signal, the processor chip U2 is configured to receive the electrocardiograph amplified signal, process the electrocardiograph amplified signal based on a stored electrocardiograph processing program, and output a corresponding processing result, the electrocardiograph acquisition chip U1 and the processor chip U2 are packaged and integrated into an electrocardiograph processor chip with software and hardware integrated, the electrocardiograph processing program is pre-stored in the processor chip U2, during the electrocardiograph signal processing process, the electrocardiograph signal can be directly received and then a detection result is output, and a user does not need to have professional knowledge of a corresponding electrocardiograph algorithm, thereby greatly reducing the research and development difficulty and the research and development period.
In this embodiment, the noise reduction circuit 101 is connected to the electrocardiograph acquisition chip U1, so that noise in the electrocardiograph signal acquisition and amplification process can be reduced, and errors in the electrocardiograph test process can be reduced.
In one embodiment, the electrocardiograph processing program pre-stored in the processor chip U2 may output corresponding electrocardiographic waveforms, heart rates, and heart rate detection results based on the received electrocardiographic amplified signals.
In this embodiment, an electrocardiographic processing program is written in the processor chip U2 in advance, and the electrocardiographic processing program performs calculation processing on the received electrocardiographic amplification signal according to an algorithm therein to obtain corresponding data such as an electrocardiographic waveform, a heart rate, and a heart rhythm, and further performs processing analysis on the heart rhythm data to determine whether the heart rhythm of the subject is normal, and if the heart rhythm is abnormal, outputs a corresponding arrhythmia result.
Further, in this embodiment, the electrocardio acquisition chip U1 and the resistors and capacitors on the periphery of the processor chip U2, the electrocardio acquisition chip U1 and the processor chip U2 are all packaged in one chip by the packaging body 100, so that the circuit symmetry can be improved, the common mode rejection ratio of electrocardiosignals can be improved, the size of the product can be greatly reduced, and the wearable product can be conveniently developed and applied.
Furthermore, resistors and capacitors at the periphery of the electrocardiosignal acquisition chip U1 and the processor chip U2 are integrated in the electrocardiosignal processing chip, so that the signal-to-noise ratio of the electrocardiosignals can be improved by reducing the interference of power signals, and the signal quality of the electrocardiosignals is improved.
In one embodiment, referring to fig. 1, the noise reduction circuit 101 includes: a first capacitor C1, a first resistor R1, a second capacitor C2, a third capacitor C3 and a second resistor R2;
a first end of the first capacitor C1 is connected to a low-pass filtered signal end LP _ OUT of the ecg acquisition chip U1, a first end of the second capacitor C2 is connected to a reference signal end VREFCM of the ecg acquisition chip U1, a second end of the power amplified signal end AMP + of the ecg acquisition chip U1, a second end of the second capacitor C2, a first end of the first capacitor C1, a first end of the first resistor R1, a second end of the first resistor R1, and a first end of the second resistor R2 are connected in common, a high-pass filtered signal end HP _ OUT of the ecg acquisition chip U1 is connected to a first end of the third capacitor C3, a PRE-stage PRE _ OUT of a power amplifier signal output end of the ecg acquisition chip U1, a second end of the third capacitor C3, and a second end of the second resistor R2 are connected in common.
In one embodiment, referring to fig. 2, the electrical cardiac signal processing circuit further comprises: and a clock signal oscillating circuit 102 connected to the processor chip U2 for providing a clock signal.
In one embodiment, referring to fig. 2, the clock signal oscillating circuit 102 includes a fourth capacitor C4, a fifth capacitor C5, and a crystal oscillator Z1;
a first end of the fourth capacitor C4 and a first end of the crystal oscillator Z1 are commonly connected to an oscillation signal output end OSC _ OUT of the processor chip, a first end of the fifth capacitor C5 and a second end of the crystal oscillator Z1 are commonly connected to an oscillation signal input end OSC _ IN of the processor chip U2, and a second end of the fourth capacitor C4 and a second end of the fifth capacitor C5 are commonly connected to ground.
In one embodiment, the model of the electrocardio acquisition chip U1 is any one of Bit2010-A6, AD8231 and ADS 1191.
In one embodiment, the processor chip U2 is model number GD32F 403.
In this embodiment, the electrocardiograph acquisition chip U1 and the processor chip U2 are bare chips and are soldered on the substrate by a flying wire process to achieve electrical connection.
In one embodiment, the package 100 is provided with a plurality of electrodes, and the plurality of electrodes are connected to the plurality of signal terminals of the electrical cardiac signal processing circuit in a one-to-one correspondence.
In the present embodiment, the package 100 is provided with a plurality of electrodes, as shown in fig. 1, a signal input end of the electrocardiographic acquisition chip U1 is respectively connected to the three electrocardiographic signal acquisition electrodes RA, LA and RL through standard electrocardiographic lead wires, wherein, a signal input end RA of the electrocardio acquisition chip U1 is connected with an electrode RA electrode on the packaging body 100 through a third resistor R3, a signal input end LA of the electrocardio acquisition chip U1 is connected with an electrode LA electrode on the packaging body 100 through a fourth resistor R4, a signal end RLDINV of the electrocardio acquisition chip U1 is connected with a first end of a sixth capacitor C6, a signal end RLDOUT of the electrocardio acquisition chip U1 and a second end of the sixth capacitor C6 are connected with a first end of a fifth resistor R5 in a sharing way, a second end of the fifth resistor R5 is connected with an electrode RL, wherein in one application electrode RA is for connection to the right arm of the human body, electrode LA is for connection to the left arm of the human body, and electrode RL is for connection to the right leg of the human body.
In one embodiment, referring to fig. 1, the ground GND of the ecg collection chip U1, the analog circuit ground and the first end of the seventh resistor R7 are commonly connected to the analog circuit ground electrode AGND of the package 100, the second end of the seventh resistor R7 and the first end of the sixth resistor R6 are commonly connected to the reference voltage signal terminal VREF of the ecg collection chip U1, the second end of the sixth resistor, the analog signal power terminal AVDD of the ecg collection chip U1 and the power amplifier power signal terminal ADC VDDA of the processor chip U2 are commonly connected to the analog signal power electrode AVDD of the package; the current gain end ICTRL of the electrocardio acquisition chip U1 is connected with a port GPIO0 of a processor chip U2, a port BL _ INT of the electrocardio acquisition chip U1 is connected with a port GPIO1 of the processor chip U2, an enable signal end EN of the electrocardio acquisition chip U1 is connected with a port GPIO2 of the processor chip U2, a port LD _ OUT of the electrocardio acquisition chip U1 is connected with a port GPIO4 of the processor chip U2, and a signal output end OUT of the electrocardio acquisition chip U1 is connected with a signal input end AD of the processor chip U2.
In one embodiment, port GPIO0, port GPIO1, port GPIO2, and port GPIO4 may each be general purpose IO interfaces for processor chip U2.
In one embodiment, port AVD, port AVDPWR, port AVS, port AVD1, and ground port GND of processor chip U2 are coupled in common to digital ground electrode DGND on package 100, port VDDIO1, port VDDIO2, port VDDPST, port ADC _ VDDIO1, and port ADC _ VDDIO2 of processor chip U2 are coupled in common to first digital signal supply electrode DVDD on package 100, port VDDC1, port VDDC2, port PLL _ VDDRFE, port PLL _ VDDRHV, FLASH _ VDDF, port VDDU1, and port VDDU2 are coupled in common to second digital signal supply electrode DVDD1V8 on package 100, an enable signal terminal EN of processor chip U2 is coupled to an enable signal electrode on package 100, a signal terminal SPI _ RXD, a signal terminal SPI _ d, signal terminal CLK, and a signal terminal SS 35ss of processor chip U2 are coupled to corresponding SPI _ RXD, SPI _ electrode, and SPI _ SPI, the download program ports JTAG _ TMS and JTAG _ TCK of the processor chip U2 are respectively connected with the electrodes JTAG _ TMS and JTAG _ TCK on the packaging body 100 in a one-to-one correspondence manner and are used for obtaining an electrocardio processing program from an upper computer, the start terminal BOOT0 of the processor chip U2 is connected with the start signal electrode BOOT0 on the packaging body 100, and the RESET signal terminal RESET of the processor chip U2 is connected with the RESET signal electrode RESET of the packaging body 100.
IN one embodiment, the oscillation signal output terminal OSC _ OUT of the processor chip U2 and the oscillation signal input terminal OSC _ IN of the processor chip U2 are connected to the oscillation signal output electrode OSC _ OUT and the oscillation signal input electrode OSC _ IN of the package 100, respectively.
IN one embodiment, referring to fig. 2, the oscillation signal output terminal OSC _ OUT of the processor chip U2 and the oscillation signal input terminal OSC _ IN of the processor chip U2 are connected to the clock signal oscillating circuit 102, and the clock signal oscillating circuit 102 is connected to the ground signal terminal GND on the package 100.
In one embodiment, the package body 100 is provided with a plurality of electrodes arranged in sequence, and the plurality of electrodes may be a plurality of solder balls arranged in sequence on the surface of the package body 100.
In one embodiment, the ecg acquisition chip U1 and the processor chip U2 are packaged by a ball grid array.
In one embodiment, referring to fig. 3, a plurality of electrodes are disposed on each side of the package 100 for connection to an external circuit.
Fig. 3 is a schematic view of an overall structure of an electrical cardiac signal processing chip according to an embodiment of the present application, in this embodiment, a length of the package 100 is 1cm to 2cm, a width of the package 100 is 1cm to 2cm, and a thickness of the package 100 is 1mm to 5 mm. In one embodiment, the length of the package 100 in this embodiment is 9mm, the width of the package 100 is 9mm, and the thickness of the package 100 is 1.2 mm.
The application provides an electrocardiosignal processing chip, which comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body used for packaging the electrocardiosignal processing circuit and the substrate; the electrocardiosignal processing circuit comprises an electrocardiosignal acquisition chip, a processor chip and a noise reduction circuit, wherein the electrocardiosignal acquisition chip is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals, the processor chip is used for receiving the electrocardio amplified signals and processing the electrocardio amplified signals based on a stored electrocardio processing program, and the noise reduction circuit is used for reducing noise of the signals. The electrocardiosignal acquisition chip and the processor chip are packaged and integrated into the electrocardiosignal processing chip integrating software and hardware, so that the problems of overlarge noise, complex circuit design and the like caused by a multi-stage circuit are avoided, and the technical problem existing in the development scheme at the present stage is solved.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. An electrocardiosignal processing chip, characterized in that, electrocardiosignal processing chip includes: the electrocardiosignal processing circuit comprises a substrate, an electrocardiosignal processing circuit arranged on the surface of the substrate and a packaging body used for packaging the electrocardiosignal processing circuit and the substrate; the electrocardiosignal processing circuit comprises:
the electrocardio acquisition chip is used for receiving electrocardiosignals and amplifying the electrocardiosignals to obtain electrocardio amplified signals;
the processor chip is connected with the electrocardio acquisition chip and used for receiving the electrocardio amplification signals, processing the electrocardio amplification signals based on a stored electrocardio processing program and outputting corresponding electrocardio waveforms, heart rate and heart rhythm detection results;
and the noise reduction circuit is connected with the electrocardio acquisition chip and is used for reducing noise of signals.
2. The cardiac signal processing chip of claim 1, wherein the noise reduction circuit comprises: the circuit comprises a first capacitor, a first resistor, a second capacitor, a third capacitor and a second resistor;
the first end of the first capacitor is connected with the low-pass filtering signal end of the electrocardio acquisition chip, the first end of the second capacitor is connected with the reference signal end of the electrocardio acquisition chip, the power amplification signal end of the electrocardio acquisition chip, the second end of the second capacitor, the first end of the first resistor, the second end of the first resistor and the first end of the second resistor are connected together, the high-pass filtering signal end of the electrocardio acquisition chip is connected with the first end of the third capacitor, and the power amplification signal preceding-stage output end of the electrocardio acquisition chip, the second end of the third capacitor and the second end of the second resistor are connected together.
3. The cardiac signal processing chip of claim 1, wherein the cardiac signal processing circuit further comprises:
and the clock signal oscillating circuit is connected with the processor chip and used for providing a clock signal.
4. The cardiac signal processing chip according to claim 3, wherein the clock signal oscillating circuit comprises a fourth capacitor, a fifth capacitor, and a crystal oscillator;
the first end of the fourth capacitor and the first end of the crystal oscillator are connected to the oscillation signal output end of the processor chip in a shared mode, the first end of the fifth capacitor and the second end of the crystal oscillator are connected to the oscillation signal input end of the processor chip in a shared mode, and the second end of the fourth capacitor and the second end of the fifth capacitor are connected to the ground in a shared mode.
5. The cardiac signal processing chip according to claim 1, wherein the model of the cardiac acquisition chip is any one of Bit2010-A6, AD8231 and ADS 1191.
6. The cardiac signal processing chip as set forth in claim 1, wherein the processor chip is of type GD32F 403.
7. The ecg signal processing chip of claim 1, wherein the package has a plurality of electrodes, and the plurality of electrodes are connected to the plurality of signal terminals of the ecg signal processing circuit in a one-to-one correspondence.
8. The ecg signal processing chip of claim 1, wherein the ecg collection chip and the processor chip are packaged by a solder ball array.
9. The cardiac signal processing chip according to claim 1, wherein the package has a length of 5mm to 20mm, a width of 5mm to 20mm, and a thickness of 1mm to 5 mm.
10. The cardiac signal processing chip according to claim 9, wherein the package has a length of 9mm, a width of 9mm, and a thickness of 1.2 mm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921275366.4U CN210811035U (en) | 2019-08-02 | 2019-08-02 | Electrocardiosignal processing chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921275366.4U CN210811035U (en) | 2019-08-02 | 2019-08-02 | Electrocardiosignal processing chip |
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