CN210807201U - High-order full-pass two-port network - Google Patents

Abstract

The utility model discloses a two port networks are led to entirely to high order, two port networks are led to entirely to the high order for the k rank, and k is greater than or equal to 3, and its topological circuit of half structure under odd-even mode includes: when k is odd number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the inductive element jX connected in parallel with the topology circuit_kThe topology circuit in odd mode comprises a topology circuit in k-1 order odd mode and a capacitive element jB connected in series with the topology circuit_k(ii) a When k is even number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the capacitive element jB connected in series with the topology circuit_kThe topology circuit in the odd mode comprises a topology circuit in a k-1 order odd mode and an inductive element jX connected with the topology circuit in parallel_k. The utility model discloses a two port network are led to entirely to high-order can obtain more excellent matching bandwidth, frequency and time delay performance.

Description

High-order full-pass two-port network

Technical Field

The utility model belongs to the technical field of network communication, concretely relates to two port networks of high-order full expert.

Background

The all-pass two-port network is mainly used in analog and radio frequency circuit systems and mainly used for adjusting the time delay characteristic of signals. Particularly, in the field of broadband phased array antennas, because the signal bandwidth is very wide, the traditional phase control unit adopting a phase shifter can cause the signal of each channel to generate time delay changing along with the frequency, and accurate beam forming cannot be realized. Therefore, the all-pass two-port network is widely applied to the phased array antenna system with higher bandwidth requirement.

The traditional all-pass network can be realized by using a transmission line, and an ideal transmission line is all-pass for signals, namely, the amplitude is not attenuated along with the frequency change, and only a time delay effect is generated on the signals. However, the transmission line has large size and poor economical efficiency. Another type of conventional delay circuit network generally adopts an artificial transmission line form formed by lumped elements, the matching characteristic of the artificial transmission line changes along with the frequency change, the matching frequency range is inversely proportional to the value of the basic network element forming the artificial transmission line, and the artificial transmission line cannot be applied to the application scenes of ultra wide band and high delay.

The delay circuit network adopting the all-pass two-port network as a basic unit can obtain an infinite matching frequency range under ideal conditions, and the group delay characteristic with a second-order response form can obtain a wider flat delay frequency range. However, the all-through two-port network has the following disadvantages:

the transmission line form is adopted, the occupied area is large, the process requirement is high, and the cost is high;

the artificial transmission line form of the lumped element is often adopted, the matching bandwidth is limited, and the application bandwidth cannot be expanded;

and a second-order all-pass network form is adopted, the signal time delay generated by a unit cell is limited, and the signal time delay generation efficiency is low.

Therefore, in order to solve the above technical problems, it is necessary to provide a high-order all-pass two-port network.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a high order leads to two port networks entirely to solve signal time delay scheduling problem among the prior art.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

a high-order all-pass two-port network is of k order, k is larger than or equal to 3, and a topological circuit of a half structure of the high-order all-pass two-port network in an odd-even mode comprises:

when k is odd number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the inductive element jX connected in parallel with the topology circuit_kThe topology circuit in odd mode comprises a topology circuit in k-1 order odd mode and a capacitive element jB connected in series with the topology circuit_k；

When k is even number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the capacitive element jB connected in series with the topology circuit_kThe topology circuit in the odd mode comprises a topology circuit in a k-1 order odd mode and an inductive element jX connected with the topology circuit in parallel_k。

In one embodiment, in the high-order all-pass two-port network, the inductive element jX_kAnd a capacitive element jB_kSatisfy the requirement of

X_kIs the reactance value of the inductive element, B_kAs susceptance value of a capacitive element, Z₀Impedance is matched to the ports.

In one embodiment, the topology circuit of the second-order all-pass two-port network half structure in the parity mode comprises:

comprising series arranged inductive elements jX in even mode₁And a capacitive element jB₂；

Comprising capacitive elements jB arranged in parallel in odd mode₁And inductive element jX₂。

In one embodiment, the topology circuit of the third-order all-pass two-port network half structure in the parity mode comprises:

topology circuit under even mode including second-order even mode and inductive element jX arranged in parallel with topology circuit₃；

Including the second order odd mode in the odd modeTopological circuit under formula (JB) and capacitive element jB connected in series with same₃。

In one embodiment, the topology circuit of the fourth-order all-pass two-port network half structure in the parity mode comprises:

the dual mode comprises a topology circuit in the third order dual mode and a capacitive element jB connected in series with the topology circuit₄；

The three-order odd-mode topological circuit and the inductive element jX connected in parallel₄。

In one embodiment, the inductive element comprises an inductor and the capacitive element comprises a capacitor.

Compared with the prior art, the utility model has the advantages of it is following:

the high-order all-pass two-port network can obtain better matching bandwidth, frequency and time delay performance;

the network construction adopts a recursive method, is easy to implement and is suitable for the synthesis of the all-pass network with the order greater than 2.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIGS. 1a and 1b are schematic diagrams of a two-port network and its half-structure, respectively;

FIGS. 2a and 2b are circuit structures of a second-order all-pass two-port network and a half structure thereof, respectively;

FIGS. 3a and 3b are equivalent circuit diagrams of a second-order all-pass two-port network half structure in odd mode and even mode, respectively;

fig. 4a and 4b are topological circuit structures of a second-order all-pass two-port network half-structure in an even mode and an odd mode, respectively, and fig. 4c is a topological circuit structure of a second-order all-pass two-port network half-structure;

fig. 5a and 5b are respectively topology circuit structures of a three-order all-pass two-port network half-structure in an even mode and an odd mode in embodiment 1 of the present invention;

fig. 6a and 6b are topology circuit structures of a four-stage all-pass two-port network half-structure in an even mode and an odd mode, respectively, in embodiment 2 of the present invention;

fig. 7a and 7b are topology circuit structures of a k-step (k is an odd number) all-pass two-port network half-structure in an even mode and an odd mode, respectively, according to embodiment 3 of the present invention;

fig. 8a and 8b are topology circuit structures of a k-order (k is an even number) all-pass two-port network half-structure in an even mode and an odd mode, respectively, according to embodiment 4 of the present invention;

fig. 9 is a comparison graph of delay-frequency characteristics of a fourth-order all-pass two-port network and a second-order all-pass two-port network.

Detailed Description

The present invention will be described in detail below with reference to embodiments shown in the drawings. However, the present invention is not limited to the embodiments, and the structural, method, or functional changes made by those skilled in the art according to the embodiments are all included in the scope of the present invention.

The utility model discloses a two port networks are led to entirely to high order, this two port networks are led to entirely to high order be k rank, and k is greater than or equal to 3, and its topological circuit of half structure under odd-even mode includes:

when k is odd number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the inductive element jX connected in parallel with the topology circuit_kThe topology circuit in odd mode comprises a topology circuit in k-1 order odd mode and a capacitive element jB connected in series with the topology circuit_k；

When k is even number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the capacitive element jB connected in series with the topology circuit_kThe topology circuit in the odd mode comprises a topology circuit in a k-1 order odd mode and an inductive element jX connected with the topology circuit in parallel_k。

The utility model also discloses a construction method of two port networks of high-order full expert, include:

s1, determining topological circuits of the second-order all-pass two-port network half structure in an odd mode and an even mode;

s2, constructing a topology circuit of the high-order all-pass two-port network half structure in an odd mode and an even mode, comprising:

when k is odd number, the topology circuit under the even mode is that an inductive element jX is connected in parallel in the topology circuit under the k-1 order even mode_kThe topology circuit in the odd mode is formed by serially connecting a capacitive element jB in the topology circuit in the k-1 order odd mode_k；

When k is even number, the topology circuit under the even mode is that the capacitive element jB is connected in series in the topology circuit under the k-1 order even mode_kIn the topology circuit under the odd mode, an inductive element jX is connected in parallel in the topology circuit under the k-1 order odd mode_k；

And S3, synthesizing the network topology based on the parity mode to obtain the high-order all-pass two-port network.

In order to ensure the reciprocity of two ports of the all-pass network, the utility model discloses discuss the all-pass network structure that has symmetrical structure.

The utility model discloses a two port network integrated approach that leads to entirely is based on odd-even mode theory, to the two port network of the symmetry that fig. 1a shows, only needs the semi-structure of two port network in the analysis fig. 1b, can obtain the electrical characteristics of whole two port network.

For example, fig. 2a shows a complete second-order all-pass two-port network, and fig. 2b shows a half structure after dividing a symmetry plane, where the circuit structure of the half structure in the parity mode is:

in the odd mode, the symmetry plane is grounded, and the circuit is shown in fig. 3 a;

in the even mode, the symmetry plane is floating, and the circuit is shown in fig. 3 b.

The present invention will be further described with reference to the following specific examples.

Example 1: three-order full-through two-port network

The topological circuit of the second-order all-pass two-port network half structure in the odd-even mode comprises the following steps:

see FIG. 4a for aIn even mode, comprises series-connected inductive elements jX₁And a capacitive element jB₂；

Referring to FIG. 4b, the odd mode includes capacitive elements jB arranged in parallel₁And inductive element jX₂。

Where X is an inductive element, B is a capacitive element, the inductive element including an inductance, etc., the capacitive element including a capacitance, etc., and the subscripts of each element indicate increasing order.

The three-order full-pass two-port network is evolved from a topological circuit of a second-order full-pass network, and the topological circuit of the half structure of the three-order full-pass two-port network in an odd-even mode comprises the following steps:

referring to fig. 5a, the even mode includes a topology circuit in the second order even mode and an inductive element jX connected in parallel with the topology circuit₃I.e. inductive elements jX₁And a capacitive element jB₂After being connected in series, the inductive element jX is connected₃Parallel connection;

referring to FIG. 5b, the odd mode includes a topology circuit in the second order odd mode and a capacitive element jB connected in series with the topology circuit₃I.e. capacitive elements jB₁And inductive element jX₂After being connected in parallel, the capacitor element jB₃Are connected in series.

Example 2: four-stage all-pass two-port network

The four-stage all-pass two-port network is evolved from a topology circuit of a three-stage all-pass network, the topology circuit of the three-stage all-pass network is shown in embodiment 1, which is not described herein again, and the topology circuit of the four-stage all-pass two-port network half structure in the parity mode includes:

referring to fig. 6a, the dual mode comprises a topology circuit in the third order dual mode and a capacitive element jB connected in series with the topology circuit₄I.e. inductive elements jX₁And a capacitive element jB₂After series connection, with inductive element jX₃Connected in parallel with the capacitive element jB₄Are connected in series;

referring to fig. 6b, the odd mode includes a topology circuit in the third order odd mode and an inductive element jX connected in parallel with the topology circuit₄I.e. capacitive elements jB₁And inductive element jX₂After being connected in parallel with the capacitive elementjB₃Connected in series with the inductive element jX₄And (4) connecting in parallel.

Example 3: k-order all-through two-port network (k is odd number)

The k-order all-pass two-port network is evolved from a topological circuit of a k-1-order all-pass network, and when k is an odd number, the topological circuit of the k-order all-pass two-port network half structure in an odd-even mode comprises the following steps:

referring to FIG. 7a, the topology circuit in even mode includes a topology circuit in k-1 order even mode and an inductive element jX connected in parallel with the topology circuit_k；

Referring to FIG. 7b, the topology circuit in odd mode comprises the topology circuit in odd mode of order k-1 and the capacitive element jB connected in series with the topology circuit_k。

Example 4: k-order all-through two-port network (k is even number)

The k-order all-pass two-port network is evolved from a topological circuit of a k-1-order all-pass network, and when k is an even number, the topological circuit of the k-order all-pass two-port network half structure in an odd-even mode comprises the following steps:

referring to FIG. 8a, the topology circuit in even mode comprises a topology circuit in k-1 order even mode and a capacitive element jB connected in series with the topology circuit_k；

Referring to FIG. 8b, the topology circuit in odd mode comprises the topology circuit in odd mode of order k-1 and the inductive element jX connected in parallel with the topology circuit_k。

In the embodiments 3 and 4, the topology circuits in the odd mode and the even mode of the k-1 order all-pass two-port network are respectively regarded as a whole, and the k order all-pass two-port network is realized by respectively adding a serial element and a parallel element in the two modes, wherein the specific adding mode is dual to the generation mode (relative to the k-2 order) of the k-1 order all-pass two-port network parity mode topology.

Referring to fig. 4a and 4b, the input impedance of the second-order all-pass two-port network half structure in the odd mode and the even mode is Z_in,oAnd Z_in,e，Z₀For impedance matching of the system ports, the reflection coefficients in odd and even modes are such that the two-port network satisfies the all-pass characteristic.

The above-mentioned fruitIn examples 1-4, inductive element jX_kAnd a capacitive element jB_kSatisfy the requirement of

X_kIs the reactance value of the inductive element, B_kAs susceptance value of a capacitive element, Z₀Impedance is matched to the ports.

The utility model discloses well high order leads to two port networks's construction method is specifically as follows:

1. determining topological circuits of a second-order all-pass two-port network half structure in an odd mode and an even mode, which are specifically shown in FIGS. 4a and 4 b;

2. the method for constructing the topological circuit of the high-order full-pass two-port network half structure in the odd mode and the even mode comprises the following steps:

when k is odd, referring to FIG. 7a, the topology circuit in even mode is the topology circuit in k-1 order even mode with parallel inductive element jX_kReferring to FIG. 7b, the topology circuit in odd mode is a topology circuit in odd mode of order k-1 with a capacitive element jB connected in series_k；

When k is even, referring to FIG. 8a, the topology circuit in even mode is the topology circuit in k-1 order even mode with the capacitive element jB connected in series_kReferring to FIG. 8b, in the topology circuit in odd mode, the inductive element jX is connected in parallel in the topology circuit in k-1 order odd mode_k；

3. According to

Determining perceptual elements jX_kAnd a capacitive element jB_kA value of (d);

4. and synthesizing the network topology based on the odd-even mode to obtain the high-order all-pass two-port network.

The network topology synthesis in the odd-even mode is an inverse method of the odd-even mode analysis, and a complete half structure can be constructed by contrasting the grounding and suspension requirements of the symmetry plane, for example, a complete half structure topology structure shown in fig. 4c can be constructed according to the second-order even mode topology structure shown in fig. 4a and the second-order odd mode topology structure shown in fig. 4 b.

The higher the order of the high-order all-pass two-port network is, the higher the order of the obtained delay characteristic is, and the wider the maximum flat delay frequency range can be obtained in a high-delay scene.

The utility model discloses in use the four-order to lead to two port networks entirely in embodiment 2 to explain as the example, refer to the time delay-frequency characteristic curve contrast diagram that figure 9 shows for four-order to lead to two port networks entirely and two-order to lead to two port networks entirely, can see that, under producing the same time delay setting, the flat time delay frequency range that obvious four-order network obtained far surpasss the second order network.

According to the technical scheme provided by the utility model, the utility model discloses following beneficial effect has:

the high-order all-pass two-port network can obtain better matching bandwidth, frequency and time delay performance;

the network construction adopts a recursive method, is easy to implement and is suitable for the synthesis of the all-pass network with the order greater than 2.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (6)

1. A high-order all-pass two-port network is characterized in that the high-order all-pass two-port network is of k order, k is larger than or equal to 3, and a topological circuit of a half structure of the high-order all-pass two-port network in an odd-even mode comprises:

when k is odd number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the inductive element jX connected in parallel with the topology circuit_kThe topology circuit in odd mode comprises a topology circuit in k-1 order odd mode and a capacitive element jB connected in series with the topology circuit_k；

When k is even number, the topology circuit under the even mode comprises the topology circuit under the k-1 order even mode and the capacitive element jB connected in series with the topology circuit_kThe topology circuit in the odd mode comprises a topology circuit in a k-1 order odd mode and an inductive element jX connected with the topology circuit in parallel_k。

2. The higher-order all-pass two-port network according to claim 1, wherein in the higher-order all-pass two-port network, inductive element jX_kAnd a capacitive element jB_kSatisfy the requirement of

X_kIs the reactance value of the inductive element, B_kAs susceptance value of a capacitive element, Z₀Impedance is matched to the ports.

3. The higher-order all-pass two-port network of claim 1, wherein the topology of the second-order all-pass two-port network half-structure in parity mode comprises:

comprising series arranged inductive elements jX in even mode₁And a capacitive element jB₂；

Comprising capacitive elements jB arranged in parallel in odd mode₁And inductive element jX₂。

4. The higher-order all-pass two-port network according to claim 3, wherein the topology circuit of the third-order all-pass two-port network half structure in the odd-even mode comprises:

topology circuit under even mode including second-order even mode and inductive element jX arranged in parallel with topology circuit₃；

Topological circuit under odd mode and second-order odd mode and capacitive element jB connected in series with topological circuit₃。

5. The higher-order all-pass two-port network of claim 4, wherein the topology of the fourth-order all-pass two-port network half-structure in parity mode comprises:

the dual mode comprises a topology circuit in the third order dual mode and a capacitive element jB connected in series with the topology circuit₄；

The three-order odd-mode topological circuit and the inductive element jX connected in parallel₄。

6. The high-order all-pass two-port network according to any one of claims 1 to 5, wherein the inductive element comprises an inductor and the capacitive element comprises a capacitor.

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