CN210780525U

CN210780525U - Power switch parallel control circuit

Info

Publication number: CN210780525U
Application number: CN201921123221.2U
Authority: CN
Inventors: 刘钧; 冯颖盈; 姚顺; 敖华
Original assignee: Shanghai Weimeisi New Energy Co ltd
Current assignee: Shanghai Weimeisi New Energy Co ltd
Priority date: 2019-07-17
Filing date: 2019-07-17
Publication date: 2020-06-16
Anticipated expiration: 2029-07-17

Abstract

The utility model discloses a power switch parallel control circuit, which comprises a power switch and a PWM controller for controlling the on-off of the power switch, wherein the power switch is divided into a plurality of groups, each group of power switches are mutually connected in parallel, and one group of power switches is connected with the control end of one PWM controller; all groups of power switch groups are simultaneously conducted under the control of the PWM controller, but the turn-off time is in turn advanced; the utility model uses a plurality of power switches in parallel to control the on-off of large current and high power; the power switch groups are turned off in advance, so that the loss of each power switch is balanced, the heat productivity is average, the whole service life is prolonged, and the reliability of the electronic product is greatly improved.

Description

Power switch parallel control circuit

Technical Field

The present invention relates to power switch control circuits, and more particularly to a control circuit for connecting a plurality of power switches in parallel.

Background

In electronic circuits, power switches are widely used. With the continuous increase of the power density of the circuit, the on-off power of a single power switch cannot meet the use requirement. If a plurality of power switches are simply connected in parallel for use, due to the discreteness of the power devices, the driving delay of the power devices is inconsistent, and the inconsistency is kept unchanged (the power devices are fast in switching-off and slow in switching-off all the time), so that the switching-off loss falls on the power devices with slow switching-off speed, the service life of the whole group of power switches is easily shortened, the individual power switches are overheated, and even potential safety hazards are caused, and adverse effects are brought to the whole electronic product.

Therefore, how to design a parallel control circuit for power switches is an urgent technical problem to be solved in the industry.

SUMMERY OF THE UTILITY MODEL

In order to solve the above-mentioned defect that exists among the prior art, the utility model provides a force power switch parallel control circuit who turns off in advance in turn.

The utility model adopts the technical scheme that a power switch parallel control circuit is designed, which comprises power switches and a PWM controller for controlling the on-off of the power switches, wherein the power switches are divided into a plurality of groups, each group of power switches are mutually connected in parallel, and one group of power switches is connected with the control end of one PWM controller; under the control of the PWM controller, the power switch groups are simultaneously conducted, but the turn-off time is alternately advanced.

The power switches can be divided into two groups, and the two power switch groups are simultaneously conducted under the control of the PWM controller, but the turn-off time is alternately advanced.

The power switches can be divided into three groups, and the three power switch groups are simultaneously switched on under the control of the PWM controller, but are alternately switched off in advance, normally and delayed in turn at the switching-off time.

All the power switches adopt power switches of the same specification and model, each power switch group comprises two power switches connected in parallel, and the two power switches are connected with the control end of the same PWM controller.

The utility model provides a technical scheme's beneficial effect is:

a plurality of power switches are used in parallel to control the on-off of large current and high power; the power switch groups are turned off in advance, so that the loss of each power switch is balanced, the heat productivity is average, the whole service life is prolonged, and the reliability of the electronic product is greatly improved.

Drawings

The invention is explained in more detail below with reference to exemplary embodiments and the accompanying drawings, in which:

FIG. 1 is a circuit diagram of two sets of power switches;

FIG. 2 is a logic diagram of the wave timing of two sets of power switches;

FIG. 3 is a circuit diagram of three sets of power switches;

fig. 4 is a logic relationship diagram of the wave-sending time sequence of three groups of power switches.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The utility model discloses a power switch parallel control circuit, which comprises a power switch and a PWM controller for controlling the on-off of the power switch, wherein the power switch is divided into a plurality of groups, each group of power switches are mutually connected in parallel, and one group of power switches is connected with the control end of one PWM controller; under the control of the PWM controller, the power switch groups are simultaneously conducted, but the turn-off time is alternately advanced.

And finally, all groups of power switches are turned off in turn, so that turn-off loss falls on all groups of power switches in turn. Therefore, the loss of each power switch is balanced, the heat productivity is average, the whole service life is prolonged, and the reliability of the electronic product is greatly improved.

In one embodiment shown in fig. 1, the power switches are divided into two groups, and the two groups of power switches are turned on at the same time under the control of the PWM controller, but the turn-off times are alternately advanced. Referring to fig. 1, Q1 and Q2 are in one group, controlled by PWM 1; q3 and Q4 are in one group and controlled by PWM 2. The two groups of PWM are simultaneously switched on and alternately switched off in advance (the first group is switched off in advance in the first switching period, the second group is normally switched off, the second group is switched off in advance in the next switching period, the first group is normally switched off, and the steps are cycled in sequence). Referring to the logic relationship diagram of the wave-sending time sequence shown in fig. 2, the PWM1 counter and the PWM2 counter are triangular fundamental waves of the PWM1 and the PWM2, and the time sequences are consistent. The effective turn-on time is Ton1, in the first switching period, the turn-on time of the PWM1 is Ton1, the turn-on time of the PWM2 is Ton2, and Tdelay is the turn-off delay of the two-path drive; in the second switching period, the on time of the PWM2 is Ton1, the on time of the PWM1 is Ton2, and Tdelay is the turn-off delay of the two-way driving, which are sequentially cycled.

In one embodiment shown in fig. 3, the power switches are divided into three groups, and the three groups of power switches are turned on at the same time under the control of the PWM controller, but are turned off in turn at an early turn-off time, a normal turn-off time, and a late turn-off time. Referring to fig. 3, Q1 and Q2 are in one group, controlled by PWM 1; q3 and Q4 are a group and controlled by PWM 2; q5 and Q6 are in one group and controlled by PWM 3. The three groups of PWM are simultaneously switched on and are switched off in advance, normally switched off and switched off in a delayed mode in turn (the first group is switched off in advance in the first switching period, the second group is switched off normally, the third group is switched off in a delayed mode, the first group is switched off normally, the second group is switched off in a delayed mode, the third group is switched off in advance in the next switching period, the first group is switched off in a delayed mode, the second group is switched off in advance, the third group is switched off normally in the next switching period. Referring to the logic relationship diagram of the wave-making timing shown in fig. 4, the PWM1 counter, the PWM2 counter and the PWM3 counter are triangular fundamental waves of the PWM1, the PWM2 and the PWM3, and the timing is consistent. In the first switching period, the on time of the PWM1 is Ton1, the on time of the PWM2 is Ton2, the on time of the PWM3 is Ton3, and Tdelay is the advance or lag time of the two-path driving; in the second switching period, the on time of the PWM1 is Ton2, the on time of the PWM2 is Ton3, the on time of the PWM3 is Ton1, and Tdelay is the advance or lag time of the two-path driving; in the third switching period, the on time of the PWM1 is Ton3, the on time of the PWM2 is Ton1, the on time of the PWM3 is Ton2, and Tdelay is the advance or lag time of the two-way driving, which are cycled sequentially.

In a preferred embodiment, all the power switches adopt power switches of the same specification and model, each power switch group comprises two power switches connected in parallel, and the two power switches are connected with the control end of the same PWM controller.

The foregoing examples are illustrative only and are not intended to be limiting. Any equivalent modifications or variations without departing from the spirit and scope of the present application should be included in the claims of the present application.

Claims

1. The utility model provides a power switch parallel control circuit, includes power switch and the PWM controller of control power switch break-make which characterized in that: the power switches are divided into a plurality of groups, the power switches of each group are connected in parallel, and one group of power switches is connected with the control end of one PWM controller; under the control of the PWM controller, the power switch groups are simultaneously conducted, but the turn-off time is alternately advanced.

2. The power switch parallel control circuit of claim 1, wherein: the power switches are divided into two groups, and the two power switch groups are simultaneously conducted under the control of the PWM controller, but the turn-off time is alternately advanced.

3. The power switch parallel control circuit of claim 1, wherein: the power switches are divided into three groups, the three power switch groups are simultaneously switched on under the control of the PWM controller, and the switching-off time is alternately switched off in advance, normally and delayed.

4. A power switch parallel control circuit according to any of claims 1 to 3, wherein: all the power switches adopt power switches of the same specification and model, each power switch group comprises two power switches connected in parallel, and the two power switches are connected with the control end of the same PWM controller.