CN210776651U - FPGA parallel fast multiplier module for vector and matrix - Google Patents

Abstract

The FPGA parallel fast multiplier module for the vector and the matrix eliminates the problem that repeated addressing is needed in calculation of the existing method, effectively reduces the memory access times and the memory access time, improves the calculation speed, realizes the parallel multiplication operation of the vector and the matrix, and provides the realization method of the vector and matrix multiplier. The technical scheme of the utility model: the structure is as follows: the structure consists of n +1 FIFO queue structure memories, n multipliers, n accumulators, n buffers and n controllers. Each memory has 1 input port and 1 output port; each multiplier has 2 input ports and 1 output port; each accumulator has 2 input ports and 1 output port; each buffer has 1 input port and 1 output port; each controller has 1 input port and 2 output ports.

Description

FPGA parallel fast multiplier module for vector and matrix

Technical Field

The invention belongs to the field of information communication, and particularly relates to a vector and matrix FPGA parallel fast multiplier.

Background

The multiplication operation of vector and matrix is the most basic operation in modern signal processing, and is widely applied to the process control in the fields of feature extraction in the image processing field, sparse signal processing, data compression in the machine learning field and automatic control. The multiplication operation of the vector and the matrix is an operation which is long in time consumption, high in calculation complexity and large in memory consumption, and the calculation performance of the operation directly influences the overall performance of the system.

In recent years, with the rapid development of the FPGA technology, the FPGA integrates functions of acquisition, control, processing, transmission, and the like into one chip, so that the development cycle is shortened, the programmable flexibility is greatly increased by parallel computing, and the existing FPGA is more widely applied to computing-intensive application occasions along with the improvement of the process and the precision. Based on the design principle and the framework of the FPGA, the FPGA can quickly and effectively realize parallel processing and improve the computing speed by designing a plurality of parallel computing modules. However, in the aspect of vector and matrix multiplication design based on the FPGA, a serial design method is mostly adopted, and the methods have the limitations of long delay time, poor expandability, doubled bandwidth along with dimensionality, and the like. Therefore, the existing processing mode has complex control, can not perform pipelined operation on real-time data, has higher computational complexity, consumes large memory and is difficult to realize.

Disclosure of Invention

The invention aims to provide a vector and matrix FPGA parallel fast multiplier aiming at the defects of the prior method, solves the problem that the prior method needs repeated addressing during calculation, effectively reduces the memory access times and the memory access time, improves the calculation speed, realizes the parallel multiplication operation of the vector and the matrix, and provides an implementation method of the vector and matrix multiplier.

The technical scheme of the invention is as follows: the structure is as follows:

the structure comprises n +1 FIFO queue structure memories (memory (0), memory (1), memory (2) … memory (n)), and n multipliers (M)₁，M₂，…M_n) N accumulators (A)₁，A₂… An), n buffers (Buf1, Buf2, … Bufn) and n controllers (controller 1, controller 2, … controller n).

Each memory has 1 input port and 1 output port; each multiplier has 2 input ports and 1 output port; each accumulator has 2 input ports and 1 output port; each buffer has 1 input port and 1 output port; each controller has 1 input port and 2 output ports.

The connection relationship of the components is as follows:

output port of memory (0) and multiplier M₁，M₂，…M_nAre connected to one input port of the memory (1) and the output port of the memory is connected to the multiplier M₁Is connected to the other input port of the multiplier M₁Output port and accumulator A₁Is connected to one input port of the accumulator A₁Is connected to the output port 1 of the controller 1, an accumulator a₁Is connected with the input port of the buffer Buf1, the output port of the buffer Buf1 is connected with the input port of the controller 1, and the controllerOutput port 2 of 1 is the final result output port out 1;

output port of memory (0) and multiplier M₁，M₂，…M_nAre connected to one input port of the memory (2), and an output port of the memory is connected to the multiplier M₂Is connected to the other input port of the multiplier M₂Output port and accumulator A₂Is connected to one input port of the accumulator A₂Is connected to the output port 1 of the controller 2, an accumulator a₂The output port of buffer Buf2 is connected with the input port of the buffer Buf2, the output port of the buffer Buf2 is connected with the input port of the controller 2, and the output port 2 of the controller 2 is the final result output port out 2;

……

output port of memory (0) and multiplier M₁，M₂，…M_nAre connected to one input port of the memory (n), and the output port of the memory (n) is connected to the multiplier M_nIs connected to the other input port of the multiplier M_nOutput port and accumulator A_nIs connected to one input port of the accumulator A_nIs connected to the output port of the controller n, an accumulator a_nThe output port of the buffer Bufn is connected with the input port of the buffer Bufn, the output port of the buffer Bufn is connected with the input port of the controller n, and the output port 2 of the controller n is the final result output port outn; the operation steps are as follows:

s1, the m-dimensional vector X is stored in the memory (0), namely the value X stored in the memory (0)₁，x₂，…x_m(ii) a For storage convenience, the matrix W is converted into an n-m-dimensional matrix, and then n row vectors are respectively stored into a memory (1) and a memory (2) …; i.e. the value stored in the memory (1) is w₁₁，w₂₁，…w_m1The value stored in the memory (2) is w₁₂,w₂₂,…w_m2By analogy, the value stored in the memory (n) is w_1n，w_2n,…w_mn；

S2 fetches the 1 st element x in memory (0)₁And in the memories (1), (2), …1 st element w₁₁,w₁₂,…,w_1n(ii) a X is to be₁Are respectively sent into M₁，M₂，…M_nMultiplier, w₁₁，w₁₂，…w₁n is sequentially fed into M₁，M₂，… M_nMultiplier, implementing x₁And w₁₁，w₁₂，…w₁n parallel multiplication of n, then feeding the product result into corresponding accumulator A₁，A₂，…An；

S3 fetches the 2 nd element x in the memory (0)₂And a 2 nd element w in memory (1), memory (2) … memory (n)₂₁，w₂₂，…w_2n(ii) a X is to be₂Are respectively sent into M₁，M₂，…M_nMultiplier, w₂₁，w₂₂，…w₂n is sequentially fed into M₁，M₂，…M_nMultiplier, implementing x₂And w₂₁，w₂₂，…w₂n parallel multiplication of n, then feeding the product result into corresponding accumulator A₁，A₂… An; s4 extracting the ith (m > i ≧ 3) element x in memory (0)_iAnd the ith element w in memory (1), memory (2) … memory (n)_i1,w_i2,…,w_in(ii) a X is to be_iAre respectively sent into M₁，M₂，…,M_nMultiplier, w_i1，w_i2，…w_inSequentially feed into M₁，M₂，…M_nMultiplier, implementing x_iAnd w_i1，w_i2，…w_inN paths of parallel multiplication calculation, and then the product result is sent to the corresponding accumulator A₁，A₂，…An；

S5, if i is less than m, i +1, repeating the step S4; otherwise, go to step S6;

s6 accumulator A₁，A₂… An stores the output results in registers Buf1, Buf2, …, Bufn, respectively. The controller 1, the controller 2, … and the controller n judge whether the operation of the vector X and the matrix W is finished, if not, the results in Buf1, Buf2, … and Bufn are sent toAccumulator A₁，A₂… An; if the result is finished, the result in Buf1, Buf2, … and Bufn is output, namely the result [ out1, out2, … outn of multiplying the vector X by the matrix W].

Drawings

FIG. 1 is a schematic view of the structure

Detailed Description

As shown in fig. 1, for clarity of description, a controller module is added to facilitate control of whether multiplication is completed or not, and if not, the result buf is fed to the accumulator a1, and if the calculation is completed, the result Out is output.

The technical scheme of the invention is as follows:

the FPGA parallel fast multiplier principle of the vector and matrix is as follows:

one vector X ═ X₁,x₂,x₃,……,x_m)，

If X × W, the following operations are required if the conventional calculation method is used:

1) get x₁Taking w₁₁Calculating x₁*w₁₁；

2) Get x₂Taking w₂₁Calculating x₂*w₂₁；

3) Get x₃Taking w₃₁Calculating x₃*w₃₁；

……

4) Get x_mTaking w_m1Calculating x_m*w_m1；

5) Calculating ∑ xi × w_i1Obtaining X W₁The product operation of the vector X and the first column of the matrix W is completed.

The product operation of the vector and a matrix column needs to be accessed and stored for 2m times, and so on, the product operation of the m-dimensional vector X and the m-n-dimensional matrix W needs to be accessed and stored for 2mn times, and the parallel effect is very poor.

If W is transposed,

then the following operations may be performed:

taking the first vector X in X₁As a common vector, take W^TThe first column in (1) can be calculated by n-way parallel multiplication to obtain

Taking the second vector X in X₂As a common vector, take W^TThe second column in (1) can be calculated by n-way parallel multiplication to obtain

……

Get the m-th vector X in X_mAs a common vector, take W^TThe m-th column in the sequence can be calculated by n-path parallel multiplication to obtain

The above results are accumulated to obtain the product of vector X and matrix W

The method has access to memory mn + m times, and when n is greater than 1, 2mn is greater than mn + m. That is, the second method has fewer access times and is easy for parallel operation, and when designing a parallel module, the structure of the parallel module can be as shown in fig. 1:

the execution process of the multiplier in the FPGA comprises the following steps:

if the m-dimensional vector X is multiplied by the m X n-dimensional matrix W, the multiplication process is as follows:

(1) storing the m-dimensional vector X into the memory (0), i.e. the value stored in the memory (0) is X₁，x₂，…x_m(ii) a For storage convenience, the matrix W is converted into n × m dimensional matrix, and then n row vectors are respectively stored in the memories (1) and (2) …A memory (n); i.e. the value stored in the memory (1) is w₁₁，w₂₁，…w_m1The value stored in the memory (2) is w₁₂,w₂₂,…w_m2By analogy, the value stored in the memory (n) is w_1n，w_2n,…w_mn；

(2) Fetch the 1 st element x in memory (0)₁And 1 st element w in memory (1), memory (2), … memory (n)₁₁,w₁₂,…,w_1n(ii) a X is to be₁Are respectively sent into M₁，M₂，…M_nMultiplier, w₁₁，w₁₂，…w₁n is sequentially fed into M₁，M₂，…M_nMultiplier, implementing x₁And w₁₁，w₁₂，…w₁n parallel multiplication of n, then feeding the product result into corresponding accumulator A₁，A₂，…An。

(3) Fetch the 2 nd element x in memory (0)₂And a 2 nd element w in memory (1), memory (2) … memory (n)₂₁，w₂₂，…w_2n(ii) a X is to be₂Are respectively sent into M₁，M₂，…M_nMultiplier, w₂₁，w₂₂，…w₂n is sequentially fed into M₁，M₂，…M_nMultiplier, implementing x₂And w₂₁，w₂₂，…w₂n parallel multiplication of n, then feeding the product result into corresponding accumulator A₁，A₂，…An。

(4) And so on, the m-th element x in the memory (0) is taken out_mAnd the m-th element w in the memory (1), the memory (2) … and the memory (n)_m1,w_m2,…,w_mn(ii) a X is to be_mAre respectively sent into M₁，M₂，…,M_nMultiplier, w_m1，w_m2，…w_mnSequentially feed into M₁，M₂，…M_nMultiplier, implementing x_mAnd w_m1，w_m2，…w_mnN parallel multiplication and then feeding the product result into the phaseCorresponding accumulator A₁，A₂，…An。

(5) Accumulator A₁，A₂… An stores the output results in registers Buf1, Buf2, …, Bufn, respectively. The controller 1, the controller 2, … and the controller n judge whether the operation of the vector X and the matrix W is finished, if not, the results in Buf1, Buf2, … and Bufn are sent to an accumulator A₁，A₂… An; if the result is finished, the result in Buf1, Buf2, … and Bufn is output, namely the result [ out1, out2, … outn of multiplying the vector X by the matrix W].

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, improvement and the like made within the content and principle of the present invention shall be included in the protection scope of the present invention.

Claims (1)

1. A FPGA parallel fast multiplier module of vector and matrix is characterized in that the structure is as follows:

the structure consists of n +1 FIFOs (first-in first-out) queue structure memories, n multipliers, n accumulators, n buffers and n controllers;

each memory has 1 input port and 1 output port; each multiplier has 2 input ports and 1 output port; each accumulator has 2 input ports and 1 output port; each buffer has 1 input port and 1 output port; each controller is provided with 1 input port and 2 output ports;

the connection relationship of the components is as follows:

output port of memory (0) and multiplier M₁，M₂，…M_nAre connected to one input port of the memory (1) and the output port of the memory is connected to the multiplier M₁Another input port ofConnected, multiplier M₁Output port and accumulator A₁Is connected to one input port of the accumulator A₁Is connected to the output port 1 of the controller 1, an accumulator a₁The output port of buffer Buf1 is connected with the input port of the buffer Buf1, the output port of buffer Buf1 is connected with the input port of the controller 1, and the output port 2 of the controller 1 is the final result output port out 1;

output port of memory (0) and multiplier M₁，M₂，…M_nAre connected to one input port of the memory (2), and an output port of the memory is connected to the multiplier M₂Is connected to the other input port of the multiplier M₂Output port and accumulator A₂Is connected to one input port of the accumulator A₂Is connected to the output port 1 of the controller 2, an accumulator a₂The output port of buffer Buf2 is connected with the input port of the buffer Buf2, the output port of the buffer Buf2 is connected with the input port of the controller 2, and the output port 2 of the controller 2 is the final result output port out 2;

sequentially connecting the output port of the memory (0) and the multiplier M₁，M₂，…M_nAre connected to one input port of the memory (n), and the output port of the memory (n) is connected to the multiplier M_nIs connected to the other input port of the multiplier M_nOutput port and accumulator A_nIs connected to one input port of the accumulator A_nIs connected to the output port of the controller n, an accumulator a_nThe output port of buffer Bufn is connected with the input port of buffer Bufn, the output port of buffer Bufn is connected with the input port of controller n, and output port 2 of controller n is the final result output port outn.

Images