CN210776274U

CN210776274U - Cloud forbidden gate controller

Info

Publication number: CN210776274U
Application number: CN201922302281.7U
Authority: CN
Inventors: 谢庆林; 徐兵; 张朝林
Original assignee: Shenzhen Ubiquitous Unicom Technology Co ltd
Current assignee: Shenzhen Ubiquitous Unicom Technology Co ltd
Priority date: 2019-12-17
Filing date: 2019-12-17
Publication date: 2020-06-16
Anticipated expiration: 2029-12-17

Abstract

The utility model discloses a cloud forbidden gate controller, which comprises a main control module, a watchdog module, a storage module, an indication module, a detection module, a power supply module, a driving module, an interface module, a download module and a wifi module; the main control module corresponds the end respectively with watchdog module, storage module, instruction module, detection module, power module, drive module, interface module, download module, wifi module electric connection. The utility model discloses cloud entrance guard compares traditional entrance guard and has following advantage: network door opening: the user can control the entrance guard to open the door through the mobile phone APP network, so that the user can conveniently come in and go out; reporting an event: all door opening events are reported to the cloud server, so that record generation and query are facilitated; remote monitoring: the administrator can remotely check the access control equipment and know the state of the access control equipment in real time; high safety: serial port communication adopts 485 encryption, and the two-dimensional code data adopts rc4 dynamic encryption.

Description

Cloud forbidden gate controller

Technical Field

The utility model relates to an entrance guard technical field, in particular to cloud forbidden gate controller.

Background

The entrance guard safety management system is a modern safety management system, it integrates microcomputer automatic identification technology and modern safety management measures into one body, it relates to many new technologies of electronics, machinery, optics, computer technology, communication technology and biological technology. The method is an effective measure for realizing safety precaution management at the entrance and exit of important departments. The system is suitable for various essential departments, such as banks, hotels, parking lot management, machine rooms, ordnance depots, key rooms, office rooms, intelligent districts, factories and the like.

The cloud entrance guard controller (NCU) has 1 way CAN communication interface, 1 way RJ 4510/100M self-adaptation net gape, 1 way WiFi, 1 way RS485 interface. The CAN interface CAN be used for expanding a distributed access controller, a 1+ X mode is adopted, 1 4-door network access controller is adopted, then the X2-door (or 4-door) distributed Access Controller (ACU) CAN be expanded through a CAN bus, and the maximum number of each set of controller supports 36 doors. The RJ45 network port and the WiFi are used for connecting a network, and the cloud access controller is connected with and communicated with the cloud server through a TCP (transmission control protocol); and the RS485 interface is linked with third-party equipment. The traditional access control system can only be used for card swiping access, cannot be used for network door opening, cannot be used for event reporting, is lack of remote monitoring and is low in safety.

SUMMERY OF THE UTILITY MODEL

To the problem that prior art exists, the utility model provides a cloud forbidden gate controller.

In order to achieve the above purpose, the utility model discloses technical scheme as follows:

a cloud forbidden gate controller comprises a main control module, a watchdog module, a storage module, an indication module, a detection module, a power supply module, a driving module, an interface module and a downloading module; the corresponding end of the main control module is electrically connected with the watchdog module, the storage module, the indication module, the detection module, the power supply module, the driving module, the interface module and the downloading module respectively.

Preferably, the main control module includes a first main control circuit and a second main control circuit, and the first main control circuit is set as a NUC972 chip and peripheral circuits thereof; the second main control circuit is set as an STM32F103 chip and a peripheral circuit thereof; and the corresponding end of the NUC972 chip is electrically connected with the corresponding end of the STM32F103 chip.

Preferably, the watchdog module comprises a watchdog circuit, and the watchdog circuit is set as an SP706 chip and peripheral circuits thereof; and the corresponding end of the SP706 chip is respectively connected with the corresponding ends of the NUC972 chip and the STM32F103 chip.

Preferably, the memory module comprises a TF card circuit and a memory circuit; the TF card circuit comprises an ULN2003 chip and peripheral circuits thereof; the corresponding end of the ULN2003 chip is connected with the corresponding end of the NUC972 chip; the storage circuit is set to be an MT29F1G08ABAEA chip and a peripheral circuit thereof; and the corresponding end of the MT29F1G08ABAEA chip is connected with the corresponding end of the NUC972 chip.

Preferably, the indication module includes a buzzer and an LED, and a corresponding end of a circuit of the buzzer and the LED is connected to a corresponding end of the NUC972 chip.

Preferably, the detection module comprises a pick-proof power-down detection circuit, an auxiliary input and a voltage detection input circuit; the anti-prying power-failure detection circuit is set as an LM2596-ADJ chip and a peripheral circuit thereof, and an LM1117-3.3 chip and a peripheral circuit thereof; the corresponding end of the LM2596-ADJ chip is respectively connected with the corresponding ends of the LM1117-3.3 chip and the STM32F103 chip; and the corresponding ends of the auxiliary input and voltage detection input circuit are connected with the corresponding ends of the STM32F103 chip.

Preferably, the power module includes a power supply, a voltage regulator circuit, a first buck conversion chip, a second buck conversion chip, an integrated circuit, and a buck circuit; the power supply outputs 5V voltage to the circuit through the voltage stabilizing circuit, and the 5V voltage output by the voltage stabilizing circuit respectively outputs 3.3V, 1.2V and 1.8V to the STM32F103 chip and the NUC972 chip through the first buck conversion chip, the second buck conversion chip, the integrated circuit and the buck circuit; the first buck conversion chip is set as an LM2596 chip and a peripheral circuit thereof; the first buck conversion chip is set as a first LP3204 chip and a peripheral circuit thereof, and a corresponding end of the first LP3204 chip is connected with a corresponding end of the LM2596 chip; the second buck conversion chip is set as a second LP3204 chip and a peripheral circuit thereof, and a corresponding end of the second LP3204 chip is connected with a corresponding end of the LM2596 chip; the integrated circuit is a G916 integrated circuit and a peripheral circuit thereof, and the corresponding end of the G916 integrated circuit is connected with the corresponding end of the LM2596 chip; the voltage reduction circuit is set as an AMS1117 chip and a peripheral circuit thereof, and the corresponding end of the AMS1117 chip is connected with the corresponding end of the LM2596 chip.

Preferably, the driving module includes a first driving circuit, a second driving circuit, and a third driving circuit; the first driving circuit is set as an MCP2551 chip and a peripheral circuit thereof, and a corresponding end of the MCP2551 chip is connected with a corresponding end of the NUC972 chip; the second driving circuit is set as a first MAX3485 chip and a peripheral circuit thereof, and a corresponding end of the first MAX3485 chip is connected with a corresponding end of the NUC972 chip; the third driving circuit is set as a second MAX3485 chip and a peripheral circuit thereof, and a corresponding end of the second MAX3485 chip is connected with a corresponding end of the STM32F103 chip.

Preferably, the interface module includes a UART debug interface circuit, a wired network interface circuit, a wiegand interface circuit, and an SWD debug interface circuit; the wired network interface circuit is set as an RTL8201F chip and a peripheral circuit thereof, and a corresponding end of the RTL8201F chip is connected with a corresponding end of the NUC972 chip; the corresponding end of the wired network interface circuit is connected with the corresponding end of the NUC972 chip; and the corresponding ends of the Wiegand interface circuit and the SWD debugging interface circuit are connected with the corresponding ends of the STM32F103 chip.

Preferably, the download module comprises a USB download circuit; the USB downloading circuit is set as a USB-MINI and a peripheral circuit thereof, and the corresponding end of the USB-MINI is connected with the corresponding end of the NUC972 chip.

Preferably, the cloud forbidden gate controller further comprises a gate switch module, the gate switch module is set as a gate switch circuit, and a corresponding end of the gate switch circuit is connected with a corresponding end of the STM32F103 chip.

Adopt the technical scheme of the utility model, following beneficial effect has: the utility model discloses cloud entrance guard compares traditional entrance guard and has following advantage: network door opening: the user can control the entrance guard to open the door through the mobile phone APP network, so that the user can conveniently come in and go out; reporting an event: all door opening events are reported to the cloud server, so that record generation and query are facilitated; remote monitoring: the administrator can remotely check the access control equipment and know the state of the access control equipment in real time; high safety: serial port communication adopts 485 encryption, and the two-dimensional code data adopts rc4 dynamic encryption.

Drawings

Fig. 1 is a schematic block diagram of the present invention;

fig. 2 is a schematic diagram of a second main control circuit and an SWD debug interface circuit of the present invention;

fig. 3 is a schematic diagram of a first main control circuit of the present invention;

FIG. 4 is a schematic circuit diagram of the watchdog module of the present invention;

FIG. 5 is a schematic diagram of the TF card circuit of the present invention;

FIG. 6 is a schematic diagram of the memory circuit of the present invention;

fig. 7 is a schematic circuit diagram of the indicating module of the present invention;

FIG. 8 is a schematic diagram of the anti-prying power-down detection circuit of the present invention;

FIG. 9 is a schematic diagram of the auxiliary input and voltage detection input circuit of the present invention;

FIG. 10 is a schematic diagram of a voltage regulator circuit and a voltage reduction circuit according to the present invention;

fig. 11 is a schematic diagram of a first buck conversion chip circuit according to the present invention;

FIG. 12 is a schematic diagram of an integrated circuit according to the present invention;

fig. 13 is a schematic diagram of a second buck conversion chip of the present invention;

fig. 14 is a schematic diagram of the first driving circuit and the third driving circuit of the present invention;

fig. 15 is a schematic diagram of a second driving circuit of the present invention;

FIG. 16 is a schematic diagram of the UART debug interface circuit of the present invention;

fig. 17 is a schematic diagram of the wired network interface circuit of the present invention;

FIG. 18 is a schematic diagram of a Wired Wiegand interface circuit of the present invention;

FIG. 19 is a schematic diagram of a download circuit of the present invention;

FIG. 20 is a schematic circuit diagram of the door magnetic switch module of the present invention;

FIG. 21 is a schematic diagram of the output circuit with relay of the present invention;

fig. 22 is a schematic circuit diagram of the wifi module of the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1 to 22, the present invention provides a cloud forbidden gate controller, which includes a main control module 1, a watchdog module 2, a storage module 3, an indication module 4, a detection module 5, a power module 6, a driving module 7, an interface module 8, a download module 9, and a wifi module 12; the corresponding end of the main control module 1 is electrically connected with the watchdog module 2, the storage module 3, the indication module 4, the detection module 5, the power module 6, the driving module 7, the interface module 8, the downloading module 9 and the wifi module 12 respectively.

The main control module 1 comprises a first main control circuit 102 and a second main control circuit 101, wherein the first main control circuit 102 is set as a NUC972 chip and peripheral circuits thereof; the second main control circuit 101 is set as an STM32F103 chip and peripheral circuits thereof; and the corresponding end of the NUC972 chip is electrically connected with the corresponding end of the STM32F103 chip.

The watchdog module 2 comprises a watchdog circuit which is set as an SP706 chip and a peripheral circuit thereof; and the corresponding end of the SP706 chip is respectively connected with the corresponding ends of the NUC972 chip and the STM32F103 chip.

The memory module 3 comprises a TF card circuit 301 and a memory circuit 302; the TF card circuit 301 comprises a ULN2003 chip and peripheral circuits thereof; the corresponding end of the ULN2003 chip is connected with the corresponding end of the NUC972 chip; the memory circuit 302 is set as an MT29F1G08ABAEA chip and its peripheral circuits; and the corresponding end of the MT29F1G08ABAEA chip is connected with the corresponding end of the NUC972 chip.

The indicating module 4 comprises a buzzer and an LED, and the corresponding end of the circuit of the buzzer and the LED is connected with the corresponding end of the NUC972 chip.

The detection module 5 comprises a pick-proof power-down detection circuit 501 and an auxiliary input and voltage detection input circuit 502; the anti-prying power-failure detection circuit 501 is an LM2596-ADJ chip and a peripheral circuit thereof, and an LM1117-3.3 chip and a peripheral circuit thereof; the corresponding end of the LM2596-ADJ chip is respectively connected with the corresponding ends of the LM1117-3.3 chip and the STM32F103 chip; and the corresponding ends of the auxiliary input and voltage detection input circuit 502 are connected with the corresponding ends of the STM32F103 chip.

The power module 6 comprises a power supply, a voltage stabilizing circuit 601, a first buck conversion chip 602, a second buck conversion chip 604, an integrated circuit 603 and a buck circuit 605; the power supply outputs 5V voltage to the circuit through the voltage stabilizing circuit 601 for power supply, and the 5V voltage output by the voltage stabilizing circuit 601 correspondingly outputs 3.3V, 1.2V and 1.8V respectively through the first buck conversion chip 602, the second buck conversion chip 604, the integrated circuit 603 and the buck circuit 605 for power supply to the STM32F103 chip and the NUC972 chip; the first buck conversion chip 602 is set as an LM2596 chip and its peripheral circuits; the first buck conversion chip 602 is set as a first LP3204 chip and its peripheral circuits, and the corresponding end of the first LP3204 chip is connected with the corresponding end of the LM2596 chip; the second buck conversion chip 604 is set as a second LP3204 chip and its peripheral circuits, and the corresponding end of the second LP3204 chip is connected with the corresponding end of the LM2596 chip; the integrated circuit 603 is set as a G916 integrated circuit and a peripheral circuit thereof, and a corresponding end of the G916 integrated circuit 603 is connected with a corresponding end of the LM2596 chip; the voltage reduction circuit 605 is set as an AMS1117 chip and a peripheral circuit thereof, and a corresponding end of the AMS1117 chip is connected with a corresponding end of the LM2596 chip.

The driving module 7 includes a first driving circuit 701, a second driving circuit 702, and a third driving circuit 703; the first driving circuit 701 is provided with an MCP2551 chip and peripheral circuits thereof, and a corresponding end of the MCP2551 chip is connected with a corresponding end of the NUC972 chip; the second driving circuit 702 is set as a first MAX3485 chip and its peripheral circuits, and the corresponding end of the first MAX3485 chip is connected to the corresponding end of the NUC972 chip; the third driving circuit 703 is set as a second MAX3485 chip and its peripheral circuits, and the corresponding end of the second MAX3485 chip is connected to the corresponding end of the STM32F103 chip.

The interface module 8 comprises a UART debugging interface circuit 801, a wired network interface circuit 802, a four-way wiegand interface circuit 803 and an SWD debugging interface circuit 804; the wired network interface circuit is set as an RTL8201F chip and a peripheral circuit thereof, and a corresponding end of the RTL8201F chip is connected with a corresponding end of the NUC972 chip; the corresponding end of the wired network interface circuit is connected with the corresponding end of the NUC972 chip; and the corresponding ends of the Wiegand interface circuit and the SWD debugging interface circuit are connected with the corresponding end of the STM32F103 chip.

The download module 9 comprises a USB download circuit; the USB downloading circuit is set as a USB-MINI and a peripheral circuit thereof, and the corresponding end of the USB-MINI is connected with the corresponding end of the NUC972 chip.

The cloud forbidden gate controller also comprises a gate switch module 10, the gate switch module is set to be a gate switch circuit, and the corresponding end of the gate switch circuit is connected with the corresponding end of the STM32F103 chip.

The cloud forbidden gate controller also comprises a relay module 11, wherein the relay module comprises a relay output circuit, the relay circuit is set as an ULN2003 chip and a peripheral circuit thereof, and the corresponding end of the ULN2003 chip is connected with the corresponding end of the STM32F103 chip.

The wifi module 12 comprises a wifi circuit; the wifi circuit is set as an LTL8188EUS chip and a peripheral circuit thereof, and a corresponding end of the LTL8188EUS chip is connected with a corresponding end of the NUC972 chip.

The utility model discloses the theory of operation as follows:

firstly, when the circuit works, the input voltage of the circuit is 12V, the LM2596 chip of the anti-prying power-down detection circuit 501 is converted into 5V voltage to be output, the 5V power supply is converted into 3.3V and 1.2V respectively through the first buck conversion chip 602 and the LP3204 chip of the second buck conversion chip 604 to supply power to the STM32F103 chip and the NUC972 chip of the main control module 1 respectively, and the 5V voltage is converted into 1.8V through the G916 integrated circuit of the integrated circuit 603 to supply power to the STM32F103 chip of the main control module 1 and the SRAM inside the NUC972 chip; meanwhile, 5V is converted into 3.3V through the AMS1117 chip of the voltage reduction circuit 605 to supply power to other peripheral circuits;

secondly, the main control module 1 reads and writes data through a memory chip MT29F1G08ABAEA chip of the memory module 3, and an STM32F103 chip of the main control module 1 and a 2-channel serial port of a NUC972 chip are converted into an RS422 interface through a MAX3485 chip of the drive module 7 to be communicated with external RS422 equipment; the 2-channel CAN of the NUC972 chip of the main control module 1 communicates with an external CAN bus through a drive chip MCP2551 of the first drive circuit 701;

then one path of USB device interface of the NUC972 chip of the main control module 1 is connected to a USB socket through a resistance-capacitance filter circuit and is communicated with external USB equipment, and the other path of USB host interface is connected to a wifi module (12) RTL8188 so as to provide the function of a wifi network; the NUC972 of the main control module 1 is connected to a chip RTL8188 of the wifi module 12 through an RMII interface, and then is connected to a network socket to provide a function of wired connection network;

finally, the NUC972 chip of the main control module 1 monitors whether the program normally runs by using the SP706 watchdog chip of the watchdog module 2, and within a certain time, if the SP706 chip of the watchdog module 2 does not receive the zero clearing pulse signal, a reset signal is generated to reset the NUC972 chip of the main control module 1 to run again; the NUC972 chip of the main control module 1 drives the passive buzzer of the indicating module 4 through the triode to generate a prompt tone; directly driving an LED indicator lamp of the indicating module 4 through an IO port to generate a state indicating signal; and the external power failure detection and anti-prying signals are isolated by the triode and then are connected to an IO port of the NUC972 chip of the main control module 1.

The above only be the preferred embodiment of the utility model discloses a not consequently restriction the utility model discloses a patent range, all are in the utility model discloses a conceive, utilize the equivalent structure transform of what the content was done in the description and the attached drawing, or direct/indirect application all is included in other relevant technical field the utility model discloses a patent protection within range.

Claims

1. A cloud forbidden gate controller is characterized by comprising a main control module, a watchdog module, a storage module, an indication module, a detection module, a power supply module, a driving module, an interface module, a download module and a wifi module; the main control module corresponds the end respectively with watchdog module, storage module, instruction module, detection module, power module, drive module, interface module, download module, wifi module electric connection.

2. The cloud forbidden gate controller according to claim 1, wherein the master control module includes a first master control circuit and a second master control circuit, and the first master control circuit is set as a NUC972 chip and peripheral circuits thereof; the second main control circuit is set as an STM32F103 chip and a peripheral circuit thereof; and the corresponding end of the NUC972 chip is electrically connected with the corresponding end of the STM32F103 chip.

3. The cloud forbidden gate controller according to claim 2, wherein the watchdog module comprises a watchdog circuit, and the watchdog circuit is set as an SP706 chip and peripheral circuits thereof; and the corresponding end of the SP706 chip is respectively connected with the corresponding ends of the NUC972 chip and the STM32F103 chip.

4. The cloud forbidden gate controller of claim 3, wherein the storage module comprises TF card circuitry, storage circuitry; the TF card circuit comprises an ULN2003 chip and peripheral circuits thereof; the corresponding end of the ULN2003 chip is connected with the corresponding end of the NUC972 chip; the storage circuit is set to be an MT29F1G08ABAEA chip and a peripheral circuit thereof; and the corresponding end of the MT29F1G08ABAEA chip is connected with the corresponding end of the NUC972 chip.

5. The cloud forbidden gate controller according to claim 4, wherein the indication module comprises a buzzer and an LED, and a corresponding end of a circuit of the buzzer and the LED is connected with a corresponding end of a NUC972 chip.

6. The cloud forbidden gate controller of claim 5, wherein the detection module comprises a pick-proof power-down detection circuit, an auxiliary input and a voltage detection input circuit; the anti-prying power-failure detection circuit is set as an LM2596-ADJ chip and a peripheral circuit thereof, and an LM1117-3.3 chip and a peripheral circuit thereof; the corresponding end of the LM2596-ADJ chip is respectively connected with the corresponding ends of the LM1117-3.3 chip and the STM32F103 chip; and the corresponding ends of the auxiliary input and voltage detection input circuit are connected with the corresponding ends of the STM32F103 chip.

7. The cloud forbidden gate controller of claim 6, wherein the power module comprises a power supply, a voltage stabilizing circuit, a first buck conversion chip, a second buck conversion chip, an integrated circuit, and a buck circuit; the power supply outputs 5V voltage through the voltage stabilizing circuit to supply power to the circuit, and the 5V voltage output by the voltage stabilizing circuit correspondingly outputs 3.3V, 1.2V and 1.8V respectively through the first buck conversion chip, the second buck conversion chip, the integrated circuit and the buck circuit to supply power to the STM32F103 chip and the NUC972 chip.

8. The cloud forbidden gate controller according to claim 7, wherein the first buck conversion chip is set as an LM2596 chip and peripheral circuits thereof; the first buck conversion chip is set as a first LP3204 chip and a peripheral circuit thereof, and a corresponding end of the first LP3204 chip is connected with a corresponding end of the LM2596 chip; the second buck conversion chip is set as a second LP3204 chip and a peripheral circuit thereof, and a corresponding end of the second LP3204 chip is connected with a corresponding end of the LM2596 chip; the integrated circuit is a G916 integrated circuit and a peripheral circuit thereof, and the corresponding end of the G916 integrated circuit is connected with the corresponding end of the LM2596 chip; the voltage reduction circuit is set as an AMS1117 chip and a peripheral circuit thereof, and the corresponding end of the AMS1117 chip is connected with the corresponding end of the LM2596 chip.

9. The cloud forbidden gate controller of claim 7, wherein the driving module comprises a first driving circuit, a second driving circuit, and a third driving circuit; the first driving circuit is set as an MCP2551 chip and a peripheral circuit thereof, and a corresponding end of the MCP2551 chip is connected with a corresponding end of the NUC972 chip; the second driving circuit is set as a first MAX3485 chip and a peripheral circuit thereof, and a corresponding end of the first MAX3485 chip is connected with a corresponding end of the NUC972 chip; the third driving circuit is set as a second MAX3485 chip and a peripheral circuit thereof, and a corresponding end of the second MAX3485 chip is connected with a corresponding end of the STM32F103 chip.