CN210724694U

CN210724694U - Sine wave power signal generator

Info

Publication number: CN210724694U
Application number: CN201921942332.6U
Authority: CN
Inventors: 雷佳; 杨盼盼; 崔红卫
Original assignee: Shaanxi electronic technology research institute
Current assignee: Shaanxi Electronic Technology Research Institute Co ltd
Priority date: 2019-11-12
Filing date: 2019-11-12
Publication date: 2020-06-09
Anticipated expiration: 2029-11-12

Abstract

The utility model discloses a sine wave power signal generator, which comprises a reference voltage power supply, a singlechip control circuit, a signal generator and an operational amplifier; the reference voltage power supply is used for respectively supplying power to the singlechip control circuit, the signal generator and the operational amplifier; the single chip microcomputer control circuit is used for setting an LCD display value, namely outputting sine wave frequency and a sine wave effective value through an ADC sampling signal, and is also used for setting the output waveform and frequency of the signal generator; the signal generator is used for generating a sinusoidal signal according to the output waveform and the frequency set by the singlechip control circuit; the operational amplifier is used for amplifying the sinusoidal signal generated by the signal generator and outputting the sinusoidal signal. The utility model discloses an exchange 220V 10% power supply, can produce the sinusoidal alternating current signal of frequency at 2500Hz scope, sinusoidal voltage virtual value 31.8V, output sine wave distortion factor is less than or equal to 1%, output sine wave periodic error is less than or equal to 2%.

Description

Sine wave power signal generator

Technical Field

The utility model belongs to the technical field of the electron, concretely relates to sine wave power signal generator.

Background

The sine wave signal generator is a signal generating device commonly used in electronic technology, and is widely applied in the fields of electronic circuit design and experiments, measuring instruments, signal transmission, communication and the like.

At present, a common sine wave signal generator is mainly realized by adopting a sine wave oscillation analog circuit or a digital frequency synthesis (DDS) technology, main core devices of the generator are an integrated operational amplifier, a microprocessor and an FPGA device, the voltage of a working power supply of the device is limited, the output voltage of the generator is low (the amplitude does not exceed 15V), the current of the generator is small (mA level), and the generator has poor load capacity and is mainly used as a signal source.

SUMMERY OF THE UTILITY MODEL

In view of the above, the main objective of the present invention is to provide a sine wave power signal generator.

In order to achieve the above purpose, the technical scheme of the utility model is realized like this:

the embodiment of the utility model provides a sine wave power signal generator, including reference voltage power, singlechip control circuit, signal generator, operational amplifier;

the reference voltage power supply is used for respectively supplying power to the singlechip control circuit, the signal generator and the operational amplifier;

the single chip microcomputer control circuit is used for setting an LCD display value, namely outputting sine wave frequency and a sine wave effective value through an ADC sampling signal, and is also used for setting the output waveform and frequency of the signal generator;

the signal generator is used for generating a sinusoidal signal according to the output waveform and the frequency set by the singlechip control circuit;

the operational amplifier is used for amplifying the sinusoidal signal generated by the signal generator and outputting the sinusoidal signal.

In the above scheme, the reference voltage power supply includes a dc main power supply, a dc first auxiliary power supply, and a dc second auxiliary power supply;

the direct current main power supply is used for generating +/-28V and +/-15V direct current signals according to +/-28V alternating current signals input by the transformer;

the direct-current first auxiliary power supply is used for generating a 5V direct-current signal according to the +/-15V direct-current signal;

and the direct current second auxiliary power supply is used for generating a 3.3V direct current signal according to the +/-15V direct current signal.

In the above scheme, the dc main power supply includes a first connection port J1, a bridge rectifier diode D1, first to sixteenth capacitors C1 to C16, first to twelfth resistors R1 to R12, a second diode D2, a third diode D3, first to fourth transformers T1 to T4, a first three-terminal adjustable regulator U6, and a second three-terminal adjustable regulator U8, where the 1 st and 3 rd terminals of the first connection port J1 are respectively connected to the bridge rectifier diode D1, the 2 nd terminal is grounded, a first one of the first terminals of the bridge rectifier diode D1 is sequentially connected to the first transformer T1, the sixth resistor R6, and the first three-terminal adjustable regulator U6 outputs a +15V dc signal, and a second one of the second terminals is sequentially connected to the first resistor R1, the second resistor R2, the third transformer T3, and the fifth resistor R5 outputs a +28V dc signal; a first path of the other end of the first path is sequentially connected with a second transformer T2, a seventh resistor R7 and a second three-terminal adjustable voltage stabilizer U8 to output a-15V direct current signal, and a second path of the first path is sequentially connected with a fourth resistor R4, a third resistor R3, a fourth transformer T4 and an eighth resistor R8 to output a-28V direct current signal; a first capacitor C1 and a third capacitor C3 which are connected in series, a second capacitor C2 and a fourth capacitor C4 which are connected in series, a fifth capacitor C5 and a sixth capacitor C6 which are connected in series, a second diode D2 and a third diode D3 which are connected in series, a seventh capacitor C7 and an eighth capacitor C8 which are connected in series, a ninth capacitor C9 and a tenth capacitor C10 which are connected in series, an eleventh capacitor C11 and a twelfth capacitor C12 which are connected in series, a thirteenth capacitor C13 and a fourteenth capacitor C14 which are connected in series, and a fifteenth capacitor C15 and a sixteenth capacitor C16 which are connected in series are sequentially connected in parallel along the output direction between the two ends of the bridge rectifier diode D1.

In the scheme, the direct-current first auxiliary power supply comprises thirteenth resistors R13 to nineteenth resistors R19, a controllable precision voltage-stabilizing source U10 and seventeenth capacitors C17 to twenty-first capacitors C21, the thirteenth resistors R13 to seventeenth resistors R17 are connected in parallel, one ends of the thirteenth resistors R13 to seventeenth resistors R17 are connected in parallel, and the other ends of the thirteenth resistors R18 and the seventeenth resistors R19, the seventeenth capacitors C17, the eighteenth capacitors C18, the nineteenth capacitors C19, the twentieth capacitors C20 and the twenty-first capacitors C21 are connected in parallel in series in sequence through the controllable precision voltage-stabilizing source U10 and then output 5.0V direct-current signals; the controllable precision voltage regulator source U10 is also grounded.

In the above scheme, the dc second auxiliary power supply includes a third three-terminal adjustable regulator U7, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twentieth resistor R20, and a twenty-first resistor R21, one path of the +15V dc signal is input through the 3 rd end of the third three-terminal adjustable regulator U7, the other path of the +15V dc signal is grounded through the twenty-second capacitor C22, the 2 nd and 4 nd ends of the third three-terminal adjustable regulator U7 output 3.3V dc signals, and the twentieth resistor R20, the twenty-first resistor R21, the twenty-third capacitor C23, and the twenty-fourth capacitor C24, which are sequentially connected in parallel along the output direction, are connected at the 2 nd and 4 nd ends of the third three-terminal adjustable regulator U7; the No. 1 of the third three-terminal adjustable voltage regulator U7 is connected between a twentieth resistor R20 and a twenty-first resistor R21.

In the above solution, the single chip microcomputer control circuit includes a single chip microcomputer U1, an ISP interface J7, a forty-fourth resistor R44, a forty-fifth resistor R45, a forty-sixth resistor R46, a forty-eighth capacitor C48, a forty-ninth capacitor C49, a fifty-fifth capacitor C50, a fifty-first capacitor C51, a fifty-third capacitor C53, a fifty-fourth capacitor C54, a fifty-fifth capacitor C55, an amplifier U9B, and a liquid crystal display module, wherein the 1 st to 3 rd terminals of the single chip microcomputer U1 are respectively connected to ports corresponding to the ISP interface J7, the 4 th terminal is connected to a fifty-0V dc signal through a forty-sixth resistor R46, the 6 th, 18 th and 39 th terminals are commonly grounded, the 19 th to 26 th terminals are respectively connected to ports corresponding to the liquid crystal display module, the 28 th and 30 th terminals are respectively grounded, the 5 th, 17 th, 38 th, 27 th and 29 are commonly connected to a 5.0V dc signal, the 40 th to 44 th terminals are respectively connected to a port corresponding to a signal generator, and the fourth terminal is grounded, the other path is connected with the 7 th end of an amplifier U9B through a forty-fourth resistor R44, the 8 th end of the amplifier U9B is connected with +15.0V direct current signals in one path, the other path is grounded through a forty-eighth capacitor C48, a forty-ninth capacitor C49 is connected to the forty-eighth capacitor C48 in parallel, the 6 th end is connected between the 7 th end and the forty-fourth resistor R44, the 5 th end is grounded through a fifty-third capacitor C53 and a forty-fifth resistor R45 respectively, the 4 th end is connected with-15.0V direct current signals in one path, the other path is grounded through a fifty-capacitor C50, and a fifty-first capacitor C51 is connected to the fifty-fourth capacitor C50 in parallel; the 5 th end of the ISP interface J7 is grounded through a fifty-fifth capacitor C55.

In the above solution, the signal generator includes a chip U2, twenty-second to thirty-third resistors R22 to R30, twenty-sixth to forty-fourth capacitors C26 to C44, first to seventh inductors L1 to L7, a crystal oscillator Y1, and a second connection port J2, wherein the 1 st, 2 nd, and 3 st terminals of the chip U2 are respectively connected to the 1 st and 2 nd terminals of the second connection port J2 through the twenty-sixth and twenty-seventh capacitors C26 and C27, the 1 st terminal is further connected to the 1 st and 2 nd terminals of the second connection port J2 through the twenty-third resistor R23, and is connected to the 3 rd terminal of the second connection port J2 through the twenty-second resistor R22, the 3 rd terminal is connected to one end of a thirty-first capacitor C31 through the twenty-eighth capacitor C28, the 7 th terminal is connected to the other end of a thirty-first capacitor C5, and the 6 th terminals are respectively connected to thirty-third, ninth, thirty-third, ninth, and ninth capacitors C29, 583, 7, and 5738, 9. The 10 ends are connected in common and then connected with the 3 rd end of a crystal oscillator Y1 through a twenty-fourth resistor R24, the 20 th end is connected with the 2 nd end of an operational amplifier U3 through a second inductor L2, a third inductor L3 and a fourth inductor L4, the 19 th end is connected with the 3 rd end of the operational amplifier U3 through a fifth inductor L5, a sixth inductor L6 and a seventh inductor L7, the 17 th end is connected between the seventh inductor L7 and the 3 rd end of the operational amplifier U3 through a twenty-seventh resistor R27, the 18 th end and the 12 th end are connected in common and grounded, the 13 th end to the 16 th end are connected with a singlechip control circuit, the two ends of the second inductor L2 are respectively connected with a grounded twenty-fifth resistor R25 and a grounded thirty-fourth capacitor C34, the two ends of the fourth inductor L4 are respectively connected with a grounded fifth capacitor C35 and a grounded thirty-sixth capacitor C36, the two ends of the fifth inductor L5 are respectively connected with a grounded resistor R37 and a thirty-sixth capacitor C57323, two ends of the seventh inductor L7 are respectively connected with a thirty-eighth capacitor C38 and a thirty-ninth capacitor C39, the 4 th end of the crystal oscillator Y1 is connected with a 3.3V direct current signal through the inductor L1, and a thirty-second capacitor C32 and a thirty-third capacitor C33 are sequentially connected between the 4 th end and the 5 th end in parallel.

In the above scheme, a twenty-eighth resistor R28, a twenty-ninth resistor R29 and a thirty-third resistor R30 are sequentially connected in parallel between the 1 st end and the 8 th end of the operational amplifier U3, the 4 th end and the 7 th end are respectively connected to a-15V dc signal and a +15V dc signal, the 4 th end is further grounded through a forty-second capacitor C42 and a forty-third capacitor C43 which are connected in parallel, the 5 th end is grounded, the 6 th end is connected to a forty-fourth capacitor C44, and the 7 th end is further grounded through a forty-fourth capacitor C40 and a forty-first capacitor C41 which are connected in parallel.

Compared with the prior art, the utility model discloses an exchange 220V 10% power supply, can produce the sinusoidal alternating current signal of frequency at 2500Hz scope, sinusoidal voltage virtual value 31.8V, output sine wave distortion factor is less than or equal to 1%, output sine wave periodic error is less than or equal to 2%.

Drawings

Fig. 1 is a schematic diagram of a sine wave power signal generator according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a dc main power source in a sine wave power signal generator according to an embodiment of the present invention;

fig. 3 is a circuit diagram of a dc first auxiliary power supply in a sine wave power signal generator according to an embodiment of the present invention;

fig. 4 is a circuit diagram of a dc secondary power supply in a sine wave power signal generator according to an embodiment of the present invention;

fig. 5 is a circuit diagram of a control circuit of a single chip in a sine wave power signal generator according to an embodiment of the present invention;

fig. 6 is a circuit diagram of a liquid crystal display module in a sine wave power signal generator according to an embodiment of the present invention;

fig. 7 is a circuit diagram of a signal generator in a sine wave power signal generator according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The embodiment of the utility model provides a sine wave power signal generator, as shown in figure 1, including reference voltage power, single chip microcomputer control circuit, signal generator, operational amplifier;

The reference voltage power supply comprises a direct-current main power supply, a direct-current first auxiliary power supply and a direct-current second auxiliary power supply;

As shown in fig. 2, the dc main power supply includes a first connection port J1, a bridge rectifier diode D1, first to sixteenth capacitors C1 to C16, first to twelfth resistors R1 to R12, a second diode D2, a third diode D3, first to fourth transformers T1 to T4, a first three-terminal adjustable regulator U6, and a second three-terminal adjustable regulator U8, where the 1 st and 3 rd terminals of the first connection port J1 are respectively connected to the bridge rectifier diode D1, the 2 nd terminal is grounded, a first one of the terminals of the bridge rectifier diode D1 is sequentially connected to the first transformer T1, the sixth resistor R6, and the first three-terminal adjustable regulator U6 outputs a +15V dc signal, and a second one of the terminals is sequentially connected to the first resistor R1, the second resistor R2, the third transformer T3, and the fifth resistor R5 outputs a +28V dc signal; a first path of the other end of the first path is sequentially connected with a second transformer T2, a seventh resistor R7 and a second three-terminal adjustable voltage stabilizer U8 to output a-15V direct current signal, and a second path of the first path is sequentially connected with a fourth resistor R4, a third resistor R3, a fourth transformer T4 and an eighth resistor R8 to output a-28V direct current signal; a first capacitor C1 and a third capacitor C3 which are connected in series, a second capacitor C2 and a fourth capacitor C4 which are connected in series, a fifth capacitor C5 and a sixth capacitor C6 which are connected in series, a second diode D2 and a third diode D3 which are connected in series, a seventh capacitor C7 and an eighth capacitor C8 which are connected in series, a ninth capacitor C9 and a tenth capacitor C10 which are connected in series, an eleventh capacitor C11 and a twelfth capacitor C12 which are connected in series, a thirteenth capacitor C13 and a fourteenth capacitor C14 which are connected in series, and a fifteenth capacitor C15 and a sixteenth capacitor C16 which are connected in series are sequentially connected in parallel along the output direction between the two ends of the bridge rectifier diode D1.

As shown in fig. 3, the dc first auxiliary power supply includes thirteenth to nineteenth resistors R13 to R19, a controllable precision regulator U10, and seventeenth to twenty-first capacitors C17 to C21, the thirteenth to seventeenth resistors R13 to R17 are connected in parallel and have one end inputting +15V dc signals, and the other end outputting 5.0V dc signals after being connected in parallel with eighteenth and nineteenth resistors R18 and R19, seventeenth to seventeenth capacitors C17, eighteenth to C18, nineteenth to C19, twentieth to C20, and twenty-first to C21 in series sequentially through the controllable precision regulator U10; the controllable precision voltage regulator source U10 is also grounded.

As shown in fig. 4, the dc second auxiliary power supply includes a third three-terminal adjustable regulator U7, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twentieth resistor R20, and a twenty-first resistor R21, one path of the +15V dc signal is input through the 3 rd end of the third three-terminal adjustable regulator U7, the other path is grounded through the twenty-second capacitor C22, the 2 nd and 4 th ends of the third three-terminal adjustable regulator U7 output 3.3V dc signals, and the twentieth resistor R20, the twenty-first resistor R21, the twenty-third capacitor C23, and the twenty-fourth capacitor C24, which are sequentially connected in parallel along the output direction, are connected at the 2 nd and 4 th ends of the third three-terminal adjustable regulator U7; the No. 1 of the third three-terminal adjustable voltage regulator U7 is connected between a twentieth resistor R20 and a twenty-first resistor R21.

As shown in fig. 5, the single chip microcomputer control circuit includes a single chip microcomputer U1, an ISP interface J7, a forty-fourth resistor R44, a forty-fifth resistor R45, a forty-sixth resistor R46, a forty-eighth capacitor C48, a forty-ninth capacitor C49, a fifty-fifth capacitor C50, a fifty-first capacitor C51, a fifty-third capacitor C53, a fifty-fourth capacitor C54, a fifty-fifth capacitor C55, an amplifier U9B, and a liquid crystal display module, wherein the 1 st to 3 rd terminals of the single chip microcomputer U1 are respectively connected to ports corresponding to the ISP interface J7, the 4 th terminal is connected to a fifty-0V dc signal through a forty-sixteenth resistor R46, the 6 th, 18 th, and 39 th terminals are commonly grounded, the 19 th to 26 th terminals are respectively connected to ports corresponding to the liquid crystal display module, the 29 th and 30 th terminals are respectively grounded, the 5 th, 17 th, 38 th, 28, and 29 th terminals are commonly connected to 5.0V dc signals, the 40 th to 44 th terminal is respectively connected to a port of the signal generator, and the fourth, the other path is connected with the 7 th end of an amplifier U9B through a forty-fourth resistor R44, the 8 th end of the amplifier U9B is connected with +15.0V direct current signals in one path, the other path is grounded through a forty-eighth capacitor C48, a forty-ninth capacitor C49 is connected to the forty-eighth capacitor C48 in parallel, the 6 th end is connected between the 7 th end and the forty-fourth resistor R44, the 5 th end is grounded through a fifty-third capacitor C53 and a forty-fifth resistor R45 respectively, the 4 th end is connected with-15.0V direct current signals in one path, the other path is grounded through a fifty-capacitor C50, and a fifty-first capacitor C51 is connected to the fifty-fourth capacitor C50 in parallel; the 5 th end of the ISP interface J7 is grounded through a fifty-fifth capacitor C55.

As shown in FIG. 6, the 4 th to 14 th terminals of the LCD1602 of the LCD module are connected to the corresponding ports of the single chip microcomputer U1, and the 3 rd terminal is grounded through a forty-seventh resistor R47.

As shown in fig. 7, the signal generator includes a chip U2, twenty-second to thirty-second resistors R22 to R30, twenty-sixth to forty-fourth capacitors C26 to C44, first to seventh inductors L1 to L7, a crystal oscillator Y1, and a second connection port J2, wherein the 1 st, 2 nd and 3 st terminals of the chip U2 are respectively connected to the 1 st and 2 nd terminals of the second connection port J2 through the twenty-sixth and twenty-seventh capacitors C26 and C27, the 1 st terminal is further connected to the 1 st and 2 nd terminals of the second connection port J2 through the twenty-third resistor R23, and is connected to the 3 rd terminal of the second connection port J2 through the twenty-second resistor R22, the 3 rd terminal is connected to one end of a thirty-first capacitor C31 through the twenty-eighth capacitor C28, the 7 th terminal is connected to the other end of a thirty-first capacitor C5, and the 6 th terminals are respectively connected to the thirty-third, ninth, 30, 583-ninth, 7, 5738, and ninth capacitors C7 and the ninth, 9. The 10 ends are connected in common and then connected with the 3 rd end of a crystal oscillator Y1 through a twenty-fourth resistor R24, the 20 th end is connected with the 2 nd end of an operational amplifier U3 through a second inductor L2, a third inductor L3 and a fourth inductor L4, the 19 th end is connected with the 3 rd end of the operational amplifier U3 through a fifth inductor L5, a sixth inductor L6 and a seventh inductor L7, the 17 th end is connected between the seventh inductor L7 and the 3 rd end of the operational amplifier U3 through a twenty-seventh resistor R27, the 18 th end and the 12 th end are connected in common and grounded, the 13 th end to the 16 th end are connected with a singlechip control circuit, the two ends of the second inductor L2 are respectively connected with a grounded twenty-fifth resistor R25 and a grounded thirty-fourth capacitor C34, the two ends of the fourth inductor L4 are respectively connected with a grounded fifth capacitor C35 and a grounded thirty-sixth capacitor C36, the two ends of the fifth inductor L5 are respectively connected with a grounded resistor R37 and a thirty-sixth capacitor C57323, two ends of the seventh inductor L7 are respectively connected with a thirty-eighth capacitor C38 and a thirty-ninth capacitor C39, the 4 th end of the crystal oscillator Y1 is connected with a 3.3V direct current signal through the inductor L1, and a thirty-second capacitor C32 and a thirty-third capacitor C33 are sequentially connected between the 4 th end and the 5 th end in parallel.

As shown in fig. 7, a twenty-eighth resistor R28, a twenty-ninth resistor R29, and a thirty-third resistor R30 are sequentially connected in parallel between the 1 st end and the 8 th end of the operational amplifier U3, the 4 th end and the 7 th end are respectively connected to a-15V dc signal and a +15V dc signal, the 4 th end is further connected to ground through a forty-second capacitor C42 and a forty-third capacitor C43 which are connected in parallel, the 5 th end is connected to ground, the 6 th end is connected to a forty-fourth capacitor C44, and the 7 th end is further connected to ground through a forty-fourth capacitor C40 and a forty-first capacitor C41 which are connected in parallel.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims

1. A sine wave power signal generator is characterized by comprising a reference voltage power supply, a singlechip control circuit, a signal generator and an operational amplifier;

2. The sinusoidal power signal generator of claim 1, wherein the voltage reference source comprises a main dc power source, a first dc auxiliary power source, and a second dc auxiliary power source; the direct current main power supply is used for generating +/-28V and +/-15V direct current signals according to +/-28V alternating current signals input by the transformer;

3. The sine wave power signal generator of claim 2, the direct current main power supply comprises a first connecting port J1, a bridge rectifier diode D1, a first capacitor C1 to a sixteenth capacitor C16, a first resistor R1 to a twelfth resistor R12, a second diode D2, a third diode D3, a first transformer T1 to a fourth transformer T4, a first three-terminal adjustable voltage regulator U6 and a second three-terminal adjustable voltage regulator U8, the 1 st and 3 rd ends of the first connection port J1 are respectively connected with a bridge rectifier diode D1, the 2 nd end is grounded, a first path of one end of the bridge rectifier diode D1 is sequentially connected with a first transformer T1, a sixth resistor R6 and a first three-terminal adjustable voltage stabilizer U6 to output +15V direct current signals, and a second path of the bridge rectifier diode D1 is sequentially connected with a first resistor R1, a second resistor R2, a third transformer T3 and a fifth resistor R5 to output +28V direct current signals; a first path of the other end of the first path is sequentially connected with a second transformer T2, a seventh resistor R7 and a second three-terminal adjustable voltage stabilizer U8 to output a-15V direct current signal, and a second path of the first path is sequentially connected with a fourth resistor R4, a third resistor R3, a fourth transformer T4 and an eighth resistor R8 to output a-28V direct current signal; a first capacitor C1 and a third capacitor C3 which are connected in series, a second capacitor C2 and a fourth capacitor C4 which are connected in series, a fifth capacitor C5 and a sixth capacitor C6 which are connected in series, a second diode D2 and a third diode D3 which are connected in series, a seventh capacitor C7 and an eighth capacitor C8 which are connected in series, a ninth capacitor C9 and a tenth capacitor C10 which are connected in series, an eleventh capacitor C11 and a twelfth capacitor C12 which are connected in series, a thirteenth capacitor C13 and a fourteenth capacitor C14 which are connected in series, and a fifteenth capacitor C15 and a sixteenth capacitor C16 which are connected in series are sequentially connected in parallel along the output direction between the two ends of the bridge rectifier diode D1.

4. The sine wave power signal generator according to claim 3, wherein the dc first auxiliary power supply comprises a thirteenth resistor R13 to a nineteenth resistor R19, a controllable precision regulator U10, a seventeenth capacitor C17 to a twenty-first capacitor C21, the thirteenth resistor R13 to the seventeenth resistor R17 are connected in parallel and have one end inputting a +15V dc signal, and the other end outputting a 5.0V dc signal after being connected in parallel with an eighteenth resistor R18 and a nineteenth resistor R19, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, a twentieth capacitor C20 and a twenty-first capacitor C21 in series in turn through the controllable precision regulator U10; the controllable precision voltage regulator source U10 is also grounded.

5. The sine wave power signal generator according to claim 4, wherein the dc second auxiliary power supply comprises a third three-terminal adjustable regulator U7, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twentieth resistor R20, a twenty-first resistor R21, the +15V dc signal is inputted through the 3 rd terminal of the third three-terminal adjustable regulator U7 in one path, and is grounded through the twenty-second capacitor C22 in the other path, the 2 nd and 4 nd terminals of the third three-terminal adjustable regulator U7 output 3.3V dc signals, and the twentieth resistor R20 and the twenty-first resistor R21, the twenty-third capacitor C23, and the twenty-fourth capacitor C24 are connected in series in the output direction sequentially at the 2 nd and 4 th terminals of the third three-terminal adjustable regulator U7; the No. 1 of the third three-terminal adjustable voltage regulator U7 is connected between a twentieth resistor R20 and a twenty-first resistor R21.

6. A sine wave power signal generator according to any of claims 1-5, wherein said SCM control circuit comprises a SCM U1, ISP interface J7, forty-fourth resistor R44, forty-fifth resistor R45, forty-sixth resistor R46, forty-eighth capacitor C48, forty-ninth capacitor C49, fifty capacitor C50, fifty-first capacitor C51, fifty-third capacitor C53, fifty-fourth capacitor C54, fifty-fifth capacitor C55, amplifier U9B, and LCD module, the 1 st-3 th terminals of said SCM U1 are connected to the ports corresponding to ISP interface J7, the 4 th terminals are connected to 5.0V DC signal through a forty-sixth resistor R46, the 6 th terminals, 18 th terminals, 39 th terminals are connected to ground, the 19 th terminals to 26 th terminals are connected to the ports corresponding to LCD module, the 28 th and 30 th terminals are connected to ground, the 5 th terminals, 17 th terminals 38, 27 th and 29V DC signal are connected to 5.0, 40-44 ends are respectively connected with a port corresponding to a signal generator, one path of the 32 end is grounded through a fifty-fourth capacitor C54, the other path is connected with the 7 th end of an amplifier U9B through a forty-fourth resistor R44, the 8 th end of the amplifier U9B is connected with +15.0V direct current signals in a first path, the other path is grounded through a forty-eighth capacitor C48, a forty-ninth capacitor C49 is connected to the forty-eighth capacitor C48 in parallel, the 6 th end is connected between the 7 th end and the forty-fourth resistor R44, the 5 th end is grounded through a fifty-third capacitor C53 and a forty-fifth resistor R45 in a second path, the 4 th end is connected with-15.0V direct current signals in a first path, the other path is grounded through a fifty-fourth capacitor C50, and the first capacitor C51 is connected to the second capacitor C50 in parallel; the 5 th end of the ISP interface J7 is grounded through a fifty-fifth capacitor C55.

7. The sine wave power signal generator according to claim 6, wherein the signal generator comprises a chip U2, twenty-second to thirty-second resistors R22 to R30, twenty-sixth to forty-fourth capacitors C26 to C44, first to seventh inductors L1 to L7, a crystal oscillator Y1, and a second connection port J2, wherein the 1 st, 2 nd and 3 rd terminals of the chip U2 are respectively connected to the 1 st and 2 nd terminals of the second connection port J2 through twenty-sixth and twenty-seventh capacitors C26 and C27, the 1 st terminal is further connected to the 1 st and 2 nd terminals of the second connection port J2 through a twenty-third resistor R23, and is connected to the 3 rd terminal of the second connection port J2 through a twenty-second resistor R22, the 3 rd terminal is connected to one end of a thirty-eighth capacitor C28, a third terminal is connected to the other terminal of a third capacitor C31, a third terminal 7 is connected to the other terminal of the eleventh capacitor C31, and a ninth terminal of the ninth capacitor C29 and the ninth terminal of the ninth capacitor C29, A thirty-third capacitor C30 is connected between the 3 rd end and the 7 th end, the 7 th, 8 th, 9 th and 10 th ends are connected with the 3 rd end of the crystal oscillator Y1 through a twenty-fourth resistor R24 after being connected in common, the 20 th end is connected with the 3 rd end of the operational amplifier U3 through a second inductor L2, a third inductor L3 and a fourth inductor L4, the 19 th end is connected with the 3 rd end of the operational amplifier U3 through a fifth inductor L5, a sixth inductor L6 and a seventh inductor L7, the 17 th end is connected between the seventh inductor L7 and the 3 rd end of the operational amplifier U3 through a twenty-seventh resistor R27, the 18 th and 12 th ends are connected in common to ground, the 13 th to 16 th ends are connected with the singlechip control circuit, the two ends of the second inductor L2 are connected with a thirty-fifth resistor R25 connected to ground and a fourth capacitor C34 connected to ground, the two ends of the thirty-third inductor C35 connected with the grounded inductor and the sixth inductor R5, two ends of the seventh inductor L7 are respectively connected with a thirty-eighth capacitor C38 and a thirty-ninth capacitor C39, the 4 th end of the crystal oscillator Y1 is connected with a 3.3V direct current signal through the inductor L1, and a thirty-second capacitor C32 and a thirty-third capacitor C33 are sequentially connected between the 4 th end and the 5 th end in parallel.

8. The sine wave power signal generator of claim 7, wherein a twenty-eighth resistor R28, a twenty-ninth resistor R29 and a thirty-third resistor R30 are connected in parallel between the 1 st end and the 8 th end of the operational amplifier U3 in sequence, the 4 th end and the 7 th end are respectively connected to a-15V dc signal and a +15V dc signal, the 4 th end is further connected to ground through a forty-second capacitor C42 and a forty-third capacitor C43 which are connected in parallel, the 5 th end is connected to ground, the 6 th end is connected to a forty-fourth capacitor C44, and the 7 th end is further connected to ground through a forty-fourth capacitor C40 and a forty-first capacitor C41 which are connected in parallel.