CN210724198U - Flexible direct current converter station direct current polar region protection system - Google Patents
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Abstract
The utility model discloses a flexible direct current converter station direct current polar region protection system, including converter transformer T1, converter transformer T1' S output divide into three routes, wherein one way through change valve side neutral point electric current IacZ sampling module ground connection, wherein another way is connected with two smoothing reactors respectively through the start-up circuit, the free end of one of them smoothing reactor L1 divide into two the tunnel behind anodal direct current IdP sampling module, first way through anodal direct current voltage UdP sampling module ground connection, the second way is connected with the one end of switch S1; the free end of the other smoothing reactor L2 is divided into two paths after passing through a negative direct current IdN sampling module, the first path is grounded through a negative direct current UdN sampling module, and the second path is connected with one end of a switch S2; and the signal output end of the neutral point current IacZ sampling module at the variable valve side is respectively connected with the signal input end of the direct-current voltage unbalance module and the signal input end of the direct-current field area grounding overcurrent protection module. The system has the advantages of multiple protection functions and the like.
Description
Technical Field
The utility model relates to a direct current protection device technical field especially relates to a flexible direct current converter station direct current polar region protection system.
Background
The flexible direct current transmission adopts a voltage source type converter, and active power and reactive power can be independently and quickly controlled and controlled, so that the stability of the system is improved, the fluctuation of the frequency and the voltage of the system is inhibited, and the steady-state performance of a grid-connected alternating current system is improved. With the increasing exhaustion of fossil energy and the increasing improvement of environmental pressure, China and even the world face strategic adjustment of energy structure, and large-scale development and utilization of new energy are imperative. The flexible direct-current power grid is an important technical direction for solving the problems of new energy grid connection and consumption, and compared with flexible direct-current power transmission at multiple ends and two ends, the flexible direct-current power grid has higher requirements on the reliability of a system, and can quickly act when the system fails, and the area for isolating the fault influence is as small as possible.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem how to provide a flexible direct current converter station direct current polar region protection system that has multiple protect function, safe in utilization.
In order to solve the technical problem, the utility model discloses the technical scheme who takes is: a protection system for a direct current pole region of a flexible direct current converter station is characterized in that: the converter transformer T1 is included, the output end of the converter transformer T1 is divided into three paths, one path is grounded through a neutral point current IacZ sampling module on a transformer side, the other path is respectively connected with two smoothing reactors through a starting circuit, the free end of one smoothing reactor L1 is divided into two paths after passing through an anode direct current IdP sampling module, the first path is grounded through an anode direct current voltage UdP sampling module, and the second path is connected with one end of a switch S1; the free end of the other smoothing reactor L2 is divided into two paths after passing through a negative direct current IdN sampling module, the first path is grounded through a negative direct current UdN sampling module, and the second path is connected with one end of a switch S2; the signal output end of the neutral point current IacZ sampling module at the variable valve side is respectively connected with the signal input end of the direct-current voltage unbalance module and the signal input end of the direct-current field area grounding overcurrent protection module; the signal output end of the positive direct current IdP sampling module is respectively connected with the signal input end of the direct current low-voltage overcurrent protection module, the signal input end of the 50Hz protection module, the signal input end of the direct current overvoltage protection module and the signal input end of the direct current undervoltage protection module; the output end of the positive direct-current voltage UdP sampling module is respectively connected with the signal input end of the direct-current low-voltage overcurrent protection module, the signal input end of the direct-current overvoltage protection module, the signal input end of the direct-current undervoltage protection module and the signal input end of the direct-current voltage unbalance module; the signal output end of the negative direct current IdN sampling module is respectively connected with the signal input end of the 50Hz protection module, the signal input end of the direct current low-voltage overcurrent protection module, the signal input end of the direct current overvoltage protection module and the signal input end of the direct current undervoltage protection module; the output end of the negative direct-current voltage UdN sampling module is respectively connected with the signal input end of the direct-current low-voltage overcurrent protection module, the signal input end of the direct-current overvoltage protection module, the signal input end of the direct-current undervoltage protection module and the signal input end of the direct-current voltage unbalance module.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: this application the system has unbalanced voltage protect function, direct current field ground connection overcurrent protection function, direct current overvoltage protection function, direct current low-voltage protect function, direct current low-voltage overcurrent protection function and 50Hz protect function, and the function is various, can ensure the stability of flexible direct current converter station operation, and the security is high.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a schematic block diagram of a system according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of a dc pole fault point in an embodiment of the present invention;
FIG. 3 is a schematic diagram of the voltage unbalance protection measurement point and the protection range in the embodiment of the present invention;
fig. 4 is a logic block diagram of voltage imbalance protection in an embodiment of the present invention;
fig. 5 is a logic block diagram of current blocking voltage imbalance protection in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a voltage unbalance protection fault point in an embodiment of the present invention;
fig. 7 is a schematic diagram of the dc field ground overcurrent protection measuring point and the protection range in the embodiment of the present invention;
fig. 8 is a logic block diagram of dc field ground overcurrent protection in an embodiment of the present invention;
fig. 9 is a schematic diagram of a dc field ground overcurrent protection fault point in the embodiment of the present invention;
fig. 10 shows the dc overvoltage protection measurement points and the protection ranges in the embodiment of the present invention;
fig. 11 is a logic block diagram of current blocking voltage protection in an embodiment of the present invention;
fig. 12 is a logic block diagram of dc overvoltage protection in an embodiment of the present invention;
fig. 13 is a schematic diagram of a dc overvoltage protection fault point in an embodiment of the present invention;
fig. 14 shows the dc low voltage protection measurement point and the protection range in the embodiment of the present invention;
fig. 15 is a logic block diagram of dc low voltage protection in an embodiment of the present invention;
fig. 16 is a schematic diagram of a dc low voltage protection fault point according to an embodiment of the present invention;
fig. 17 shows dc low voltage over-current protection measurement points and protection ranges according to an embodiment of the present invention;
fig. 18 is a logic block diagram of dc low voltage over-current protection in an embodiment of the present invention;
fig. 19 is a schematic diagram of a dc low voltage overcurrent protection fault point in an embodiment of the present invention;
FIG. 20 shows the protection range and the protection points of 50Hz in the embodiment of the present invention;
fig. 21 is a logic block diagram of 50Hz protection in an embodiment of the present invention;
FIG. 22 is a schematic diagram of a 50Hz protection fault point in an embodiment of the present invention;
wherein: 1. a valve side neutral point current IacZ sampling module; 2. starting a loop; 3. a positive electrode direct current IdP sampling module; 4. a positive DC voltage UdP sampling module; 5. a negative dc current IdN sampling module; 6. negative dc voltage UdN sampling module.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be implemented in other ways different from the specific details set forth herein, and one skilled in the art may similarly generalize the present invention without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As shown in fig. 1, the embodiment of the utility model discloses a flexible direct current converter station direct current polar region protection system, including converter transformer T1, converter transformer T1' S output divide into three routes, wherein one way through become valve side neutral point current IacZ sampling module 1 ground connection, wherein another way is connected with two smoothing reactors respectively through start-up circuit 2, the free end of one of them smoothing reactor L1 divide into two the tunnel behind anodal direct current IdP sampling module 3, first way through anodal direct current voltage UdP sampling module 4 ground connection, the second way is connected with the one end of switch S1; the free end of the other smoothing reactor L2 is divided into two paths after passing through the negative direct current IdN sampling module 5, the first path is grounded through the negative direct current UdN sampling module 6, and the second path is connected with one end of a switch S2; the signal output end of the neutral point current IacZ sampling module 1 at the variable valve side is respectively connected with the signal input end of the direct-current voltage unbalance module and the signal input end of the direct-current field area grounding overcurrent protection module; the signal output end of the positive direct current IdP sampling module 3 is respectively connected with the signal input end of the direct current low-voltage overcurrent protection module, the signal input end of the 50Hz protection module, the signal input end of the direct current overvoltage protection module and the signal input end of the direct current undervoltage protection module; the output end of the positive direct-current voltage UdP sampling module 4 is respectively connected with the signal input end of the direct-current low-voltage overcurrent protection module, the signal input end of the direct-current overvoltage protection module, the signal input end of the direct-current undervoltage protection module and the signal input end of the direct-current voltage unbalance module; the signal output end of the negative direct current IdN sampling module 5 is respectively connected with the signal input end of the 50Hz protection module, the signal input end of the direct current low-voltage overcurrent protection module, the signal input end of the direct current overvoltage protection module and the signal input end of the direct current undervoltage protection module; the output end of the negative dc voltage UdN sampling module 6 is connected to the signal input end of the dc low voltage overcurrent protection module, the signal input end of the dc overvoltage protection module, the signal input end of the dc undervoltage protection module, and the signal input end of the dc voltage unbalance module, respectively.
The protection range of the direct current polar region is shown in fig. 2, the main protection region is a direct current polar line, and the measured values of each measuring point comprise neutral point current IacZ at the side of the connecting transformer valve, positive and negative direct current voltages UdP and UdN, and positive and negative direct current currents IdP and IdN. The number of the measuring points is 4 in total for the protection of the direct current polar region. The dc electrode region protection is classified into 5 types, which are specifically shown in table 1, and the coordination relationship between the protections is shown in table 2.
TABLE 1 DC polar region protection configuration table
TABLE 2 coordination relationship between the protection of DC pole protection area
Voltage unbalance protection function:
protection purpose and scope, as shown in fig. 3, the voltage unbalance protection belongs to the dc pole area protection, which is mainly aimed at the dc pole or the asymmetric fault of the single pole grounding, and the protection is used as the backup protection of the dc single pole grounding fault.
Protection configuration and fixed value:
the discrimination formula is as follows: the voltage criterion | UdP + UdN | > U _ set;
the current blocking voltage criterion is | UdP + UdN | > U _ set & IacZ > I _ set;
the voltage unbalance protection has 3 sections, the voltage unbalance protection has 1 section and 2 sections which only judge the average value of one cycle of direct current voltage, and the voltage unbalance protection has 3 sections which judge the average value of the direct current voltage and the effective value of a neutral point at the side of a connecting variable valve. The constants are shown in the following table:
TABLE 3 bridge arm overcurrent definite value table
Protection principle and logic block diagram:
fig. 4 is a protection logic block diagram of the voltage unbalance protection 1-stage and 2-stage, under the conditions of protection control word input, protection input state, protection pressing plate input, and no MU fault, comparing an absolute value of the sum of UdP and UdN (the average value of one cycle is respectively taken by UdP and UdN) with a fixed value, timing by a time relay, outputting a protection start flag and an exit matrix, issuing the exit matrix and an OK/BAD flag of MU to FPGA, and determining a final protection exit by an FPGA exit truth table.
Fig. 5 is a logic diagram of the 3-stage current blocking voltage unbalance protection of the voltage unbalance protection, under the conditions of protection control word input, protection input state, protection pressing plate input, and no fault of the MU, the absolute value of the sum of the sums of UdP and UdN (the average value of one cycle is respectively taken by UdP and UdN) and the effective value of the neutral point current IacZ at the side of the connecting variable valve are compared with the fixed value, and then the time is counted by a time relay, the protection start flag and the exit matrix are output, the exit matrix and the OK/BAD flag of the MU are issued to the FPGA, and the final protection exit is judged by the FPGA exit truth table.
Test verification and check:
and (3) related test items: as shown in fig. 6, the voltage unbalance protection should operate when a unipolar grounded asymmetrical fault occurs in the dc pole and the fault points are F6 bridge arm valve group ground fault, F7 dc bus ground fault, and F8 dc pole line ground fault.
TABLE 4 Voltage unbalance protection test matrix
Development of the test
The F6 bridge arm valve group ground fault, the F7 direct current bus ground fault and the F8 direct current pole line ground fault tests are carried out in the FPT/DPT test, so that the unbalanced voltage and overcurrent protection can act correctly, and the unbalanced voltage and overcurrent protection and the unbalanced direct current voltage T2 can act correctly.
The trial has covered all.
TABLE 5 test development
Note: "√" indicates that an experiment has been performed, "×" indicates that no experiment has been performed, and "-" indicates that no experiment need be performed.
DC field ground overcurrent protection function:
the protection purpose and scope, as shown in fig. 7, the dc field ground overcurrent protection belongs to the dc pole area protection, and is used as the main protection of the dc field single-point ground fault.
Protection configuration and constant value
The discrimination formula is as follows:
|IacZ|>I_set；
the direct current field earth overcurrent protection has 2 sections, wherein the 1 section adopts full wave root mean square value to judge, the 2 section adopts half wave root mean square value, namely, the judgment is carried out in a 10ms data window, the 1 section outlet alarms, and the 2 section outlet trips. The constants are shown in the following table:
table 6 dc field earth overcurrent protection fixed value table
Protection principle and logic block diagram:
fig. 8 is a logic diagram of protection of 1-stage and 2-stage dc field ground overcurrent, which compares the rms value of the neutral point current IacZ of the coupling transformer side with a fixed value under the conditions of protection control word input, protection input state, protection pressing plate input, and no MU fault, outputs a protection start flag and an exit matrix after timing by a time relay, issues the exit matrix and the OK/BAD flag of the MU to the FPGA, and determines the final protection exit by the FPGA exit truth table.
Test verification and check:
in the related test items, as shown in fig. 9, when an F2 ac connection bus ground fault, an F4 bridge arm reactor ground fault, an F5 bridge arm gang change valve side ground fault, an F6 converter area unipolar ground fault, an F7 bridge arm valve group ground fault, and an F8 dc bus ground fault occur, the dc field ground overcurrent protection should be performed.
TABLE 7 AC FREQUENCY PROTECTION TEST MATRIX
The test development, FPT/DPT test development, is shown in Table 8:
TABLE 8 test development
Note: "√" indicates that an experiment has been performed, "×" indicates that no experiment has been performed, and "-" indicates that no experiment need be performed.
The direct current overvoltage protection function:
the protection purpose and range, as shown in fig. 10, the dc overvoltage protection belongs to dc pole area protection, and the protection system is overvoltage caused by control abnormality, tap operation error, lightning stroke, dc pole ground fault, dc pole open circuit and other faults. The direct current overvoltage protection is taken as the backup protection of the overvoltage protection of the converter valve body in consideration of the overvoltage capacity of the valve and the overvoltage protection function in valve control.
Protection configuration and constant value
The discrimination formula is as follows:
voltage criterion
|UdP- UdN |>U_set1
Current blocking voltage criterion:
|UdP|>U_set2&|IdP|<I_set；
Or |UdN|>U_set2&|IdN|<I_set；
the direct current overvoltage protection has 3 sections, the direct current voltage average value UdP of one cycle and the voltage between poles of UdN calculation are adopted for judging in the sections 1 and 2, the section 1 gives an alarm, and the section 2 gives an trip. And 3, a current blocking voltage section, calculating interelectrode voltage by adopting the average value UdP and UdN of the direct current voltage of one cycle, judging by adopting direct current IdP and IdN, and tripping an outlet. The current locking voltage section mainly reflects the open-circuit fault of a direct-current pole, the voltage fixed value takes unipolar direct-current voltage as a reference, and the current fixed value adopts a direct-current pole line open-circuit criterion threshold. The constant values are shown in Table 9:
table 9 dc field earth overcurrent protection fixed value table
Protection principle and logic block diagram:
fig. 11 is a logic diagram of protection logic for 3-stage current blocking voltage of dc overvoltage protection, where the average values of IdP and IdN (1 cycle) are taken under the conditions of protection control word input, protection input state, protection pressing plate input, no fault of MU, and closed position of dc isolation knife, to ensure that the average values of IdP and IdN are once greater than 0.05 times of the rated dc current of the valve, and after 1 second time delay is satisfied, it is determined that IdP and IdN are less than the fixed value and UdP and UdN are greater than the fixed value, and a protection start flag and an exit matrix are output after timing by a time relay, and the exit matrix and an OK/BAD flag of MU are issued to FPGA, and a final protection exit (an exit is determined by an FPGA exit truth table that the positive and negative poles satisfy one of them).
Fig. 12 is a logic diagram of protection in sections 1 and 2 of dc field ground overcurrent, where, under the conditions of protection control word input, protection input state, protection pressing plate input, and no MU fault, the average values UdP and UdN of the positive and negative dc voltages of one cycle are taken to calculate the inter-electrode voltage, compare with the fixed value, and then time is counted by a time relay, and a protection start flag and an exit matrix are output, and the exit matrix and the OK/BAD flag of the MU are issued to the FPGA, and the final protection exit is determined by the FPGA exit truth table.
Test verification and check: as shown in fig. 13, the protection is against overvoltage caused by control abnormality, tap operation error, lightning strike, dc ground fault, dc line open, and the like. When the pole lines are open, the protected 3-segment current blocking voltage segment should act.
TABLE 10 AC FREQUENCY PROTECTION TEST MATRIX
Direct current low voltage protection function:
the protection purpose and scope, as shown in fig. 14, the dc low voltage protection belongs to the dc pole area protection, and detects the symmetric voltage drop fault on the dc positive and negative buses.
Protection configuration and fixed value:
the discrimination formula is as follows:
UdP-UdN|<U_set2&|UdP+UdN|<U_set_unb；
the direct-current low-voltage protection has 1 section in total, judgment is carried out by adopting a mean value of a cycle of positive voltage UdP and negative voltage UdN, and when the interelectrode voltage is smaller than a low-voltage threshold fixed value and the bipolar unbalanced voltage is smaller than an unbalanced threshold fixed value, the outlet trips after action delay is reached. The constants are shown in the following table:
Protection principle and logic block diagram: fig. 15 is a logic block diagram of dc low voltage protection, in which the average value of the dc positive voltage UdP and the dc negative voltage UdN is obtained in the protection control word on state, the protection pressing plate on state, the MU no fault condition, and the inverter unlock state. When the inverter is unlocked, the interelectrode voltage | UdP-UdN | is greater than the low voltage constant value and lasts for 1s, the protection is opened, and when the protection is operated or the inverter is locked, the protection is exited. After the protection is opened, the inter-electrode voltage | UdP-UdN | is compared with a low voltage fixed value and is lower than a fixed value outlet, the unbalanced voltage | UdP + UdN | is compared with an unbalanced fixed value and is lower than the fixed value outlet, when two criteria are simultaneously output, the protection is finally output to a time relay to time, a protection starting mark and an outlet matrix are output, the outlet matrix and an OK/BAD mark of the MU are issued to the FPGA, and the final protection outlet is judged through an FPGA outlet truth table.
Test verification and check: in the related test items, as shown in fig. 16, the dc low voltage protection mainly reflects the symmetrical voltage drop on the dc positive and negative buses.
Direct current low voltage overcurrent protection function:
the protection purpose and scope, as shown in fig. 17, the dc low-voltage overcurrent protection belongs to dc electrode area protection, protects the whole dc system, detects ground short circuit faults caused by various reasons, mainly reflects faults of dc electrode bipolar short circuit, and needs to be matched with other protection reflecting ground faults and overcurrent capacity of dc equipment to be used as main protection of dc system protection, and simultaneously uses dc overcurrent protection as backup.
Protection configuration and fixed value:
the discrimination formula is as follows:
|UdP- UdN |<U_set2&(|IdP|>I_set or |IdN|>I_set)
the direct current low voltage over-current protection has 1 section in total, positive and negative electrode voltages UdP and UdN and positive and negative electrode currents IdP and IdN are adopted for judgment, when the interelectrode voltage is smaller than a low voltage threshold fixed value and the current of the positive electrode or the negative electrode is larger than a high current threshold fixed value, and after action delay is achieved, an outlet trips. The constant values are shown in Table 12:
TABLE 12 DC LOW-VOLTAGE OVER-CURRENT FIXED-VALUE TABLE
Protection principle and logic block diagram: fig. 18 is a logic block diagram of dc low-voltage overcurrent protection, in which, in the FPGA, when a protection control word is turned on, a protection turn-on state, a protection pressing plate is turned on, and the MU is in a no-fault state, the maximum three-phase values of the upper arm current IbP and the lower arm current IbN are compared with an overcurrent fixed value, the absolute value of the voltage between the poles is calculated from the positive electrode voltage UdP and the negative electrode voltage UdN, the absolute value of the voltage between the poles is compared with a low-voltage fixed value, when the voltage is lower than the fixed value and the corresponding current is greater than the fixed value and continues for 200us, the protection start flag corresponding to each of the three phases is output to the DSP, when any one of the three currents is greater than the fixed value, the exit matrix FPGA is output, the. In the DSP, when the protection control word is put into, the protection put into state, the protection pressing plate is put into and the MU has no fault, the action mark of the upper bridge arm or the lower bridge arm is received and then exported to a time relay, and a start mark is set and a protection action message is sent.
Test verification and check:
and (3) related test items: as shown in fig. 19, the dc low-voltage overcurrent protection is mainly against F6 and F8 dc double short-circuit faults, and is a valve-controlled dc double short-circuit fault backup protection.
Table 13 dc low voltage overcurrent protection test matrix
Test development conditions: the FPT/DPT test develops F6 and F8 direct current bipolar short-circuit faults, and both the faults are tripped by the valve control direct current bipolar short-circuit protection first action.
TABLE 14 test development
| Sequence of steps Number (C) | Test conditions | Broadside F6 Failure point | Broadside F8 Failure point | Cloud south side F6 Failure point | Cloud south side |
| 1 | STATCOM operation on south of clouds and reactive power Rate 400Mvar | √ | √ | √ | √ |
| 2 | STATCOM operation on Guangxi side with reactive power Rate 400MVar | √ | √ | √ | √ |
| 3 | Converter double end latched state of charge | √ | √ | √ | √ |
| 4 | Independent operation of the soft and straight units, DC power 200MW | √ | √ | √ | √ |
| 5 | Independent operation of the soft and straight units, DC power 1000MW | √ | √ | √ | √ |
| 6 | The conventional direct current and flexible direct current double unit operates, DC power 10MW | √ | √ | √ | √ |
| 7 | The conventional direct current and flexible direct current double unit operates, DC power 1000MW | √ | √ | √ | √ |
50Hz protection function:
purpose and scope of protection: as shown in fig. 20, the 50Hz protection belongs to the dc pole zone protection, and mainly reflects an increase in the fundamental current component on the dc line due to a fault such as a bridge arm reactor flashover.
Protection configuration and fixed value: the discrimination formula is as follows:
IdP_50Hz>IdP_DC*C_set；
Or IdN_50Hz>IdN_DC *C_set；
the 50Hz protection has 2 sections, the outlet of the section 1 is alarmed, the outlet of the section 2 is tripped, the current fundamental component adopts Fourier filtering (one cycle), the current direct-current component adopts sampling value low-pass filtering, the outlet of the section 1 is alarmed, and the outlet of the section 2 is tripped. The constants are shown in the following table:
table 1550 Hz protection fixed value table
The 50Hz protection criterion is as follows:
IdP_50Hz>I_set_50Hz&IdP_DC>I_set_DC&IdP_50Hz>IdP_DC*C_set
Or IdN_50Hz>I_set_50Hz&IdN_DC>I_set_DC&IdN_50Hz>IdN_DC*C_set
protection principle and logic block diagram: fig. 21 is a logic diagram of 50Hz 1-stage and 2-stage protection, under the conditions of protection control word input, protection input state, protection pressing plate input, and MU no fault, taking IdP and IdN sampling values to perform fourier filtering and low-pass filtering, comparing the processed IdP and IdN fundamental wave components and dc components with current threshold values, comparing the ratio of the processed IdP and IdN fundamental wave components to the dc component with a ratio fixed value, outputting a protection start flag and an exit matrix after timing by a time relay, issuing the exit matrix and OK/BAD flags of the MU to the FPGA, and determining the final protection exit by the FPGA exit truth table.
Test verification and check: as shown in fig. 22, the 50Hz protection aims at a fault that a current fundamental component on a direct current line is increased due to a fault such as flashover between ends of a bridge arm reactor during system operation, and a large harmonic is generated to affect the system operation.
Table 1650 Hz protection test matrix
| Serial number | Related failure test items | Main | Backup protection | |
| 1 | Bridge arm reactor end-to-end flashover | 50Hz protection (81-I) | Is free of |
Test development conditions:
a turn-to-turn flashover fault test project of the reactor of the side bridge arm in Guangxi of Yunnan province is developed in the FPT/DPT test, and correct actions are protected.
TABLE 17 test development
| Sequence of steps Number (C) | Test conditions | Cloud south bridge arm reactor Flashover between turns | Guangxi side bridge arm reactor Flashover between turns |
| 1 | Independent operation of the soft and straight units, DC power 1000MW | √ | √ |
| 2 | Normal DC and soft DC dual unit operation, DC Flow power 10MW | √ | √ |
| 3 | Normal DC and soft DC dual unit operation, DC Flow power 1000MW | √ | √ |
Note: "√" indicates that an experiment has been performed, "×" indicates that no experiment has been performed, and "-" indicates that no experiment need be performed.
Claims (1)
1. A protection system for a direct current pole region of a flexible direct current converter station is characterized in that: the converter transformer T1 is included, the output end of the converter transformer T1 is divided into three paths, one path is grounded through a neutral point current IacZ sampling module (1) on the side of the transformer valve, the other path is respectively connected with two smoothing reactors through a starting loop (2), the free end of one smoothing reactor L1 is divided into two paths after passing through an anode direct current IdP sampling module (3), the first path is grounded through an anode direct current voltage UdP sampling module (4), and the second path is connected with one end of a switch S1; the free end of the other smoothing reactor L2 is divided into two paths after passing through a negative direct current IdN sampling module (5), the first path is grounded through a negative direct current UdN sampling module (6), and the second path is connected with one end of a switch S2; the signal output end of the neutral point current IacZ sampling module (1) at the variable valve side is respectively connected with the signal input end of the direct-current voltage unbalance module and the signal input end of the direct-current field area grounding overcurrent protection module; the signal output end of the positive direct current IdP sampling module (3) is respectively connected with the signal input end of the direct current low-voltage overcurrent protection module, the signal input end of the 50Hz protection module, the signal input end of the direct current overvoltage protection module and the signal input end of the direct current undervoltage protection module; the output end of the positive direct-current voltage UdP sampling module (4) is respectively connected with the signal input end of the direct-current low-voltage overcurrent protection module, the signal input end of the direct-current overvoltage protection module, the signal input end of the direct-current undervoltage protection module and the signal input end of the direct-current voltage unbalance module; the signal output end of the negative direct current IdN sampling module (5) is respectively connected with the signal input end of the 50Hz protection module, the signal input end of the direct current low-voltage overcurrent protection module, the signal input end of the direct current overvoltage protection module and the signal input end of the direct current undervoltage protection module; the output end of the negative direct voltage UdN sampling module (6) is respectively connected with the signal input end of the direct current low voltage overcurrent protection module, the signal input end of the direct current overvoltage protection module, the signal input end of the direct current undervoltage protection module and the signal input end of the direct current voltage unbalance module.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112134450A (en) * | 2020-08-24 | 2020-12-25 | 许继集团有限公司 | Method and device for matching direct current energy consumption device with direct current protection |
| CN112886556A (en) * | 2021-03-04 | 2021-06-01 | 中国南方电网有限责任公司 | Single-phase earth fault control protection method for flexible direct current transmission alternating current connection line area |
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2019
- 2019-11-14 CN CN201921965000.XU patent/CN210724198U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112134450A (en) * | 2020-08-24 | 2020-12-25 | 许继集团有限公司 | Method and device for matching direct current energy consumption device with direct current protection |
| CN112886556A (en) * | 2021-03-04 | 2021-06-01 | 中国南方电网有限责任公司 | Single-phase earth fault control protection method for flexible direct current transmission alternating current connection line area |
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