CN210720562U - Sampling early warning system of electronic transformer acquisition unit for GIS - Google Patents
Sampling early warning system of electronic transformer acquisition unit for GIS Download PDFInfo
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Abstract
The utility model discloses a GIS is with sampling early warning system of electronic transformer collection unit, including AD sampling module, FPGA module and power monitoring module, AD sampling module and power monitoring module are connected to the FPGA module, AD sampling module is connected with sampling working power supply, power monitoring module still is connected to sampling working power supply, AD sampling module is used for analog input signal's analog-to-digital conversion, power monitoring module is used for real-time detection AD sampling module's sampling working power supply voltage, to FPGA module feedback sampling working power supply state, the FPGA module has self-checking module. The utility model discloses effectively solve current sampling safeguard measure and not consider the inside unusual influence, unable prevention AD power fluctuation, the unusual scheduling problem of module communication to the acquisition unit of sampling module.
Description
Technical Field
The utility model belongs to the technical field of the digital transformer substation of electric power system, concretely relates to GIS is with sampling early warning system of electronic type mutual-inductor collection unit.
Background
The electronic transformer for the GIS is a combined active electronic transformer matched with a gas insulated switch, fully utilizes the insulation structural characteristic of GIS gas, has the characteristics of simple and reliable insulation, small volume, light weight, good linearity and the like, can effectively reduce the occupied area of the GIS, transmits sampling signals through optical fibers, reduces secondary cables of a transformer substation, has strong anti-interference capability, and is suitable for the development of the digital transformer substation technology.
The GIS electronic transformer comprises a sensing coil, a collecting unit, a merging unit and the like. The merging unit is usually placed in a substation room and connected with the electronic transformer acquisition unit through optical fibers, and is less influenced by the interference of the field environment. The acquisition unit is placed near mutual-inductor body on the spot, and operating environment is abominable, and in the field operation in-process, external disturbance signal is great to acquisition unit sampling circuit's influence, then causes metering error gently, then probably samples inefficacy and leads to the rear end protection device malfunction, brings very big influence for the safe operation of transformer substation. Therefore, the reliability of the sampled data is a key technical point for the research of the electronic transformer acquisition unit for the GIS.
The electronic transformer acquisition unit used in the field of the existing transformer substation generally adopts an integrated box body structure design with a shielding net, so that the influence of space radiation interference on an internal loop of the acquisition unit is reduced; by improving the electromagnetic compatibility of the power supply module of the acquisition unit, the stability of a power supply system of a sampling loop is guaranteed, and abnormal sampling caused by power supply interference is avoided; a filtering module is arranged in an analog quantity signal input loop to inhibit aliasing high-frequency interference in a small signal output by the transformer body. The method starts from the sampling anti-interference measure of the acquisition unit, and isolates the interference signal outside the sampling module, thereby reducing the possibility of sampling abnormity, but the influence of the internal abnormity of the sampling module on the acquisition unit is not considered, and the sampling invalidation phenomenon caused by the problems of AD power supply fluctuation, module communication abnormity and the like can not be prevented. Therefore, a real-time monitoring and early warning system of the sampling module of the acquisition unit needs to be researched, so that the sampling reliability of the acquisition unit of the electronic transformer for the GIS is further enhanced.
Disclosure of Invention
The to-be-solved technical problem of the utility model is: the utility model provides a GIS is with sampling early warning system of electronic transformer collection unit, solves the problem that present GIS is with electronic transformer collection unit sampling reliability is not enough, influences the transformer substation operation security when field usage, does not consider the sampling invalid problem that the influence of sampling module internal anomaly to the collection unit, can't prevent AD power fluctuation, reasons such as module communication anomaly arouse to current sampling safeguard measure.
The utility model discloses the technical scheme who takes does: the utility model provides a GIS is with sampling early warning system of electronic type mutual-inductor collection unit, including AD sampling module, FPGA module and power monitoring module, AD sampling module and power monitoring module are connected to the FPGA module, AD sampling module is connected with sampling working power supply, power monitoring module still is connected to sampling working power supply, AD sampling module is used for analog input signal's analog-to-digital conversion, power monitoring module is used for real-time detection AD sampling module's sampling working power supply voltage, to FPGA module feedback sampling working power supply state, the FPGA module has self-checking module.
Preferably, the circuit of the power supply monitoring module comprises an OPA comparator, an IN + input terminal of the OPA comparator is connected to the sampling operating power supply through a voltage dividing circuit, a V + power terminal of the OPA comparator is connected with a decoupling circuit, an OUT output terminal of the OPA comparator is connected to the VCC power supply and the FPGA module through a pull-up resistor R4 and an impedance matching resistor R3, respectively, and an IN-reference input terminal of the OPA comparator is connected to a REF reference terminal of the OPA comparator.
Preferably, the voltage divider circuit includes a resistor R1 and a resistor R2 connected IN series, one end of the resistor R1 is connected to the sampling operation power supply, the other end of the resistor R2 is connected to ground, and the IN + input end is connected to a connection point between the resistor R1 and the resistor R2.
Preferably, the decoupling circuit comprises two capacitors C1 and C2 connected in parallel, one end of each capacitor C1 is connected to the VCC power supply and the V + power supply, and the other end of each capacitor C2 is grounded.
Preferably, the AD sampling module employs an 18-bit successive approximation type analog-to-digital converter AD 7982.
Preferably, the FPGA module is connected to a constant temperature crystal oscillator, and the constant temperature crystal oscillator is an OCXO 50.
Preferably, the FPGA module adopts Xilinx Spartan-6 series product XC6SLX 150.
The utility model has the advantages that: compared with the prior art, the utility model discloses an effect as follows:
(1) the utility model discloses connect the FPGA module at AD sampling module, and monitor the state of sampling working power supply alone through power monitoring module, if FPGA self-checking, AD sampling module or power monitoring module take place unusually, unusual signal feedback is to the FPGA module, the FPGA module reports this signal of sampling to external system, the signal of this time acquisition is invalid, thereby effectively solve current sampling safeguard measure and not consider the influence of sampling module internal anomaly to the collection unit, can't prevent AD power fluctuation, module communication abnormal grade problem;
(2) the clock stability of the system is detected through the FPGA clock management module, the accuracy of sampling trigger control time is detected through sampling interruption and recovery, and the abnormal running of FPGA logic is detected through the output of the monitoring chip, so that the clock and logic self-check of the FPGA main control module is realized;
(3) the voltage monitoring module of the sampling working power supply monitors the power supply change of AD sampling in real time, is simple to realize and strong in reliability, and can effectively reflect the voltage fluctuation state of the sampling power supply in time;
(4) the working state of the AD chip is actively detected in the sampling process, the effectiveness of the sampling data is verified in real time, and the reliability of the AD module in the sampling conversion and communication processes is ensured.
Drawings
FIG. 1 is a flow chart of the present invention;
FIG. 2 is a schematic diagram of a sampling early warning system;
FIG. 3 is a schematic diagram of a power monitoring module.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific embodiments.
Example (b): as shown in fig. 1-3, a sampling early warning system of an electronic transformer acquisition unit for a GIS comprises an AD sampling module, an FPGA module and a power supply monitoring module, wherein the AD sampling module and the power supply monitoring module are connected to the FPGA module, the AD sampling module is connected with a sampling working power supply, the power supply monitoring module is also connected to the sampling working power supply, the AD sampling module is used for analog-to-digital conversion of an analog input signal, the power supply monitoring module is used for detecting the sampling working power supply voltage of the AD sampling module in real time and feeding back the sampling working power supply state to the FPGA module, the FPGA module is provided with a self-checking module, and the FPGA module is a core part of the sampling early warning system, so that on one hand, the AD sampling module is driven to complete analog quantity sampling, and on the other hand, the output of a sampling abnormal warning signal is controlled by combining the AD working state, the sampling power supply state and the self working state; the constant temperature crystal oscillator is responsible for providing a stable and reliable system clock for the FPGA module.
Preferably, as shown IN fig. 2, the circuit of the power supply monitoring module includes an OPA comparator, an IN + input terminal of the OPA comparator is connected to the sampling operating power supply through a voltage dividing circuit, a V + power terminal of the OPA comparator is connected to a decoupling circuit, an OUT output terminal of the OPA comparator is connected to the VCC power supply and the FPGA module through a pull-up resistor R4 and an impedance matching resistor R3, and an output impedance matching resistor R4 is used to stabilize an output level; the output pull-up resistor R4 ensures that the output level of the comparator is normal, the IN-reference input end of the OPA comparator is connected to the REF reference end of the OPA comparator, the IN-reference input end is the internal reference voltage of the comparator, the OPA comparator controls the OUT signal to output high level or low level by comparing the voltage of the input signals IN + and IN-, and the V + end and the V-end of the OPA comparator are the working power supply input of the comparator; the voltage division circuit comprises a resistor R1 and a resistor R2 which are connected IN series, one end of the voltage division circuit is connected with a sampling working power supply, the other end of the voltage division circuit is grounded, and the IN + input end of the voltage division circuit is connected to a connection point between the resistor R1 and the resistor R2; the decoupling circuit comprises a capacitor C1 and a capacitor C2 which are connected in parallel, one end of the capacitor C1 and one end of the capacitor C2 are connected with a VCC power supply and a V + power supply end, the other end of the capacitor C2 is grounded, the decoupling circuit of C1 and C2 is adopted to filter power supply noise, when the power supply voltage of the sampling module is greater than a threshold value, the OUT terminal of the comparator outputs a high level signal, otherwise, a low level signal is output.
The OPA comparator employs a TLV3011 with voltage reference, where TLV3011 is a low power consumption open-drain output comparator with an unconstrained on-chip reference voltage. The maximum quiescent current is 5uA, and the single power supply working voltage is from 1.8V to 5.5V. Integrates a 1.242V reference voltage with the maximum drift less than 100ppm/° C and can stably work under the capacitance load of maximum 10nF, and can provide the output current of maximum 0.5 mA. TLV3011 can be used for small-scale SOT23-6 packaging or SC70 packaging, and the working temperature ranges from-40 ℃ to +125 ℃.
Preferably, the AD sampling module employs an 18-bit successive approximation type analog-to-digital converter AD7982, and the sampling rate is 1000kSPS at most, so that an analog-to-digital conversion function with high precision and high sampling rate can be realized. The AD7982 is powered by a 2.5V single power supply, and a low-power-consumption, high-speed and 18-bit non-missing code sampling ADC, an internal conversion clock and a multifunctional serial interface port are arranged in the AD 7982. On the rising edge of the transition signal, the device samples the voltage difference between the differential input pins. The reference voltage is externally supplied and may be set as a power supply voltage. The power consumption and the throughput rate of the device are in a linear change relationship. Supporting SPI communication mode and daisy chain interlink mode and providing an optional busy indication.
Preferably, the FPGA module is connected with a constant temperature crystal oscillator, the constant temperature crystal oscillator adopts a high-precision constant temperature crystal oscillator OCXO50, a clock signal of the FPGA module is provided by the high-precision constant temperature crystal oscillator OCXO50, the working temperature of the OCXO50 constant temperature crystal oscillator is-40 to 85 ℃, the temperature drift characteristic is less than 1ppb, the low phase noise of-160 dBc/1KHz and the low aging of maximum 10ppb/year are realized, and the accuracy of module time sequence control and the stability of long-term working are ensured.
Preferably, the FPGA module adopts Xilinx Spartan-6 series products XC6SLX150, and the XC6SLX150 comprises 147443 logic units, 4824Kb Block RAM special memory and 6 CMT clock management modules based on a 45nm low-power consumption process, so that the FPGA module has rich resources and high running speed, and realizes perfect balance of cost performance and power consumption. The FPGA module is a main control module of the sampling early warning system, on one hand, drives the AD chip to realize high-speed analog-to-digital conversion and obtain analog quantity sampling data, and on the other hand, detects self-checking signals, sampling power monitoring signals and AD state monitoring signals in the FPGA and controls the output and return of alarm signals. Based on the real-time property and high-precision constant-temperature crystal oscillator of the FPGA, a sampling early warning signal with low time delay and small clock jitter is provided.
Example 2: as shown in fig. 1-3, an early warning method of a sampling early warning system of an electronic transformer acquisition unit for a GIS includes: before sampling, firstly, whether a clock, interruption and watchdog module of the FPGA module work normally is checked, the FPGA module is subjected to self-checking, and secondly, the voltage state of the current sampling working power supply is detected, so that the working stability of the sampling module is ensured. After the AD sampling module carries out high-speed sampling, whether the running state of the AD sampling module is normal or not is detected, finally, if an abnormal state exists in the AD sampling process and the voltage of a sampling working power supply is abnormal, an abnormal signal is collected by the power supply monitoring module and fed back to the FPGA module, the FPGA module outputs a sampling abnormal alarm signal and informs an external device that the sampling is invalid; the method comprises the following specific steps:
the specific technical steps are as follows:
step 1: FPGA module self-checking
Before sampling begins, the FPGA module needs to detect whether the current working state is normal. The FPGA module self-checking comprises three parts, namely, internal clock management module self-checking, sampling interruption module self-checking and watchdog module self-checking;
(1) self-checking of a clock management module: whether the current output clock of the clock management module is LOCKED with the input clock or not, namely whether the system working clock of the FPGA is stable or not is judged by monitoring a clock Locking (LOCKED) mark of the clock management module in the FPGA. When the LOCKED is set, the system clock of the FPGA module is indicated to work normally;
(2) sampling interruption self-checking: sampling trigger interruption output to the AD module is acquired through an internal input pin, and whether the interval period and the effective pulse width meet the requirements or not is detected. The sampling precision of the AD module is prevented from being influenced by inconsistent sampling trigger time caused by crystal oscillator clock offset or internal logic abnormity;
(3) self-checking of the watchdog: the FPGA module controls the work of the watchdog monitoring chip to monitor the output state of the watchdog monitoring chip in real time. When logic abnormality occurs in the FPGA and dog feeding cannot be performed, a monitoring chip counter overflows, and an abnormal signal is output to inform an FPGA module;
after the FPGA module is normally self-checked in the step 1, the power supply system of the detection sampling module in the step 2 is entered;
step 2: sampling operating power supply monitoring
A sampling working power supply monitoring loop is set up through a hardware loop, and the output voltage state of a sampling module power supply system is detected in real time;
the power state of the sampling module directly affects the reliability of the AD sampling. When the sampling working power supply voltage is lower, the AD chip can not work normally, and meanwhile, the AD sampling reference voltage fluctuates, so that sampling output is invalid. The voltage of the sampling working power supply is directly detected through a peripheral circuit, and when the voltage is lower than a threshold value, an abnormal signal of the sampling working power supply is output, so that the sampling working power supply is reliably monitored;
after the FPGA module detects that the sampling working power supply is normal through the step 2, the FPGA module enters the step 3 and starts high-speed AD sampling;
and step 3: AD high speed sampling
By adopting high-speed AD (analog-to-digital) conversion, abnormal conditions such as loss of high-frequency components of original signals, large sampling precision errors or unstable sampling data and the like caused by insufficient sampling rate of an analog loop are avoided, and meanwhile, the realization precision of a back-end software algorithm can be effectively improved;
the multi-channel AD conversion chip is synchronously driven in parallel through the FPGA module, and a hundred-megabyte clock and the AD module are adopted for interactive sampling. And after the rising edge of the sampling interruption is monitored each time, the FPGA module sets a CNV conversion signal of the AD chip and informs the AD chip of converting the cached input analog quantity. And then after the inherent conversion time delay, the FPGA module monitors a BUSY BUSY indication signal of the AD chip. And after the busy indication signal is reset, reading the AD sampling data through the SPI interface. Inputting 18-bit sampling data bit by bit, capturing the data at the falling edge of the SPI clock each time, resetting the FPGA sampling logic after all data bits are transmitted, and waiting for the next sampling process;
after the AD sampling is finished, the FPGA module enters a step 4 to detect whether the AD working state is abnormal or not;
and 4, step 4: AD status monitoring
In each AD sampling process, the FPGA can regularly detect a busy indication mark and a sampling completion mark fed back by the AD sampling module. After the AD chip starts conversion, if a busy indication mark is not returned after the maximum conversion time (710 ns) of the AD chip is exceeded, or a sampling completion mark is not set after one sampling interruption is exceeded, the AD sampling module is considered to work abnormally;
after the AD state monitoring is finished, the FPGA module enters step 5 to judge whether a sampling abnormal mark needs to be output or not;
and 5: sampling abnormal signal output
When the FPGA module is abnormal in self-checking in the step 1, or the sampling working power supply is abnormal in monitoring in the step 2, or the AD working state is abnormal in monitoring in the step 4, outputting a sampling abnormal alarm signal through the step 5;
when the sampling is abnormal, an alarm signal is immediately output, and the back-end equipment is informed that the sampling cannot be used in real time; after the sampling abnormity disappears, the alarm signal returns after the jitter elimination delay, and the reliability of the sampling system for outputting the sampling is ensured;
the sampling alarm signal can be directly output through an internal port line of the acquisition unit, and can also be indirectly output in a mode of sampling a message state word.
The early warning system and the early warning method have the advantages that:
(1) the utility model discloses connect the FPGA module at AD sampling module, and monitor the state of sampling working power supply alone through power monitoring module, if FPGA self-checking, AD sampling module or power monitoring module take place unusually, unusual signal feedback is to the FPGA module, the FPGA module reports this signal of sampling to external system, the signal of this time acquisition is invalid, thereby effectively solve current sampling safeguard measure and not consider the influence of sampling module internal anomaly to the collection unit, can't prevent AD power fluctuation, module communication abnormal grade problem;
(2) the clock stability of the system is detected through the FPGA clock management module, the accuracy of sampling trigger control time is detected through sampling interruption and recovery, and the abnormal running of FPGA logic is detected through the output of the monitoring chip, so that the clock and logic self-check of the FPGA main control module is realized;
(3) the voltage monitoring module of the sampling working power supply monitors the power supply change of AD sampling in real time, is simple to realize and strong in reliability, and can effectively reflect the voltage fluctuation state of the sampling power supply in time;
(4) the working state of the AD chip is actively detected in the sampling process, the effectiveness of the sampled data is verified in real time, and the reliability of the AD module in the sampling conversion and communication processes is ensured;
(5) when all the abnormal states of the modules disappear, the alarm signal is delayed to return after being eliminated, and the reliability of the early warning system when the sampling abnormal state is unstable is improved;
(6) the early warning system is realized based on a high-instantaneity FPGA processor and a high-precision constant-temperature crystal oscillator, has lower signal output delay and clock jitter, and meets the requirement of a high-sampling-rate application environment.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention, therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (7)
1. The utility model provides a GIS is with sampling early warning system of electronic type mutual-inductor collection unit which characterized in that: including AD sampling module, FPGA module and power monitoring module, AD sampling module and power monitoring module are connected to the FPGA module, AD sampling module is connected with sampling working power supply, power monitoring module still is connected to sampling working power supply, AD sampling module is used for analog input signal's analog-to-digital conversion, power monitoring module is used for the sampling working power supply voltage of real-time detection AD sampling module, to FPGA module feedback sampling working power supply state, the FPGA module has self-checking module.
2. The sampling early warning system of the electronic transformer acquisition unit for the GIS according to claim 1, characterized in that: the circuit of the power supply monitoring module comprises an OPA comparator, the IN + input end of the OPA comparator is connected to a sampling working power supply through a voltage division circuit, the V + power supply end of the OPA comparator is connected with a decoupling circuit, the OUT output end of the OPA comparator is connected to a VCC power supply and an FPGA module through a pull-up resistor R4 and an impedance matching resistor R3 respectively, and the IN-reference input end of the OPA comparator is connected to the REF reference end of the OPA comparator.
3. The sampling early warning system of the electronic transformer acquisition unit for the GIS according to claim 2, characterized in that: the voltage division circuit comprises a resistor R1 and a resistor R2 which are connected IN series, one end of the voltage division circuit is connected with the sampling working power supply, the other end of the voltage division circuit is grounded, and the IN + input end of the voltage division circuit is connected to a connection point between the resistor R1 and the resistor R2.
4. The sampling early warning system of the electronic transformer acquisition unit for the GIS according to claim 2, characterized in that: the decoupling circuit comprises two capacitors C1 and C2 which are connected in parallel, one end of the capacitor is connected with a VCC power supply and a V + power supply end, and the other end of the capacitor is grounded.
5. The sampling early warning system of the electronic transformer acquisition unit for the GIS according to claim 1, characterized in that: the AD sampling module adopts an 18-bit successive approximation type analog-to-digital converter AD 7982.
6. The sampling early warning system of the electronic transformer acquisition unit for the GIS according to claim 1, characterized in that: the FPGA module is connected with a constant-temperature crystal oscillator, and the constant-temperature crystal oscillator adopts a constant-temperature crystal oscillator OCXO 50.
7. The sampling early warning system of the electronic transformer acquisition unit for the GIS according to claim 1, characterized in that: the FPGA module adopts Xilinx Spartan-6 series product XC6SLX 150.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110441592A (en) * | 2019-09-17 | 2019-11-12 | 贵州电网有限责任公司 | A kind of the sampling early warning system and method for GIS electronic mutual inductor acquisition unit |
| CN110716503A (en) * | 2019-10-10 | 2020-01-21 | 西安航天动力试验技术研究所 | High-precision thrust servo controller |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110441592A (en) * | 2019-09-17 | 2019-11-12 | 贵州电网有限责任公司 | A kind of the sampling early warning system and method for GIS electronic mutual inductor acquisition unit |
| CN110441592B (en) * | 2019-09-17 | 2024-05-07 | 贵州电网有限责任公司 | Sampling early warning system and method of electronic transformer acquisition unit for GIS |
| CN110716503A (en) * | 2019-10-10 | 2020-01-21 | 西安航天动力试验技术研究所 | High-precision thrust servo controller |
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