CN210670531U - Signal receiving and decoding circuit - Google Patents
Signal receiving and decoding circuit Download PDFInfo
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- CN210670531U CN210670531U CN201922103220.8U CN201922103220U CN210670531U CN 210670531 U CN210670531 U CN 210670531U CN 201922103220 U CN201922103220 U CN 201922103220U CN 210670531 U CN210670531 U CN 210670531U
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Abstract
The utility model discloses a signal reception decoding circuit, it is applied to on computer and the peripheral product of computer, including signal reception circuit, first signal coupling circuit, transistor signal amplifier circuit, second signal coupling circuit, operational amplification circuit, third signal coupling circuit, speaker and power, signal reception circuit is connected with power and first signal coupling circuit electricity, first signal coupling circuit is connected with transistor signal amplifier circuit electricity, transistor signal amplifier circuit is connected with power and second signal coupling circuit electricity, operational amplification circuit's signal input part is connected with second signal coupling circuit's signal output part electricity, operational amplification circuit's signal output part is connected with third signal coupling circuit's signal input part electricity; and the signal output end of the third signal coupling circuit is electrically connected with the loudspeaker. The utility model has the advantages of can better filtering noise.
Description
Technical Field
The utility model relates to a computer audio signal processing technology field, in particular to signal reception decoding circuit.
Background
Audio signals as a streaming media signal have a plurality of transmission modes, wherein the transmission mode of wireless communication (e.g. fourth generation mobile phone mobile communication standard) is a new and more important one. When an audio transmission technology including a wireless communication transmission mode appears in a broadcast terminal, a wireless communication module is only a data transmission channel, and a processor and a memory are required to be built outside to complete decoding and other works, so that the structure of the broadcast terminal is complex and the cost is increased; meanwhile, when the application scene and the user requirement change, the transmission modes may need to be combined to generate a new terminal product. It is common practice to repeatedly change the circuit layout to meet new market demands. However, the decoded signal is usually noisy in the transmission process, resulting in poor output sound quality and being unable to meet the requirements.
SUMMERY OF THE UTILITY MODEL
The technical problem solved by the utility model is to provide a signal reception decoding circuit that can better filtering noise.
The utility model provides a signal reception decoding circuit, including signal reception circuit, first signal coupling circuit, transistor signal amplification circuit, second signal coupling circuit, operational amplification circuit, third signal coupling circuit, speaker and power, signal reception circuit with the power reaches first signal coupling circuit electricity is connected for receive audio signal and decode audio signal; the first signal coupling circuit is electrically connected with the transistor signal amplifying circuit and is used for coupling the decoded audio signal to the transistor signal amplifying circuit; the transistor signal amplifying circuit is electrically connected with the power supply and the second signal coupling circuit and is used for amplifying the signal output by the first signal coupling circuit and outputting the amplified signal to the second signal coupling circuit; the signal input end of the operational amplification circuit is electrically connected with the signal output end of the second signal coupling circuit, and the signal output end of the operational amplification circuit is electrically connected with the signal input end of the third signal coupling circuit; and the signal output end of the third signal coupling circuit is electrically connected with the loudspeaker.
Preferably, the signal receiving circuit includes an antenna, a signal receiving decoding chip, a first capacitor, and a first resistor, a first end of the first capacitor is electrically connected to a third pin of the signal receiving decoding chip, and a second end of the first capacitor is electrically connected to a fourth pin of the signal receiving decoding chip; the first end of the first resistor is electrically connected with the sixth pin of the signal receiving decoding chip, and the second end of the first resistor is electrically connected with the fifth pin of the signal receiving decoding chip and grounded.
Preferably, the first signal coupling circuit includes a second capacitor, a first end of the second capacitor is electrically connected to the sixth pin of the signal receiving and decoding chip, and a second end of the second capacitor is electrically connected to the transistor signal amplifying circuit.
Preferably, the transistor signal amplifying circuit includes a second resistor, a third resistor, and a first transistor, a first end of the second resistor is electrically connected to the power supply, and a second end of the second resistor is electrically connected to a collector of the first transistor; a first end of the third resistor is electrically connected with a second end of the second resistor, and a second end of the third resistor is electrically connected with a second end of the second capacitor; and the base electrode of the first triode is electrically connected with the second end of the second capacitor, and the emitting electrode of the first triode is grounded.
Preferably, the second signal coupling circuit includes a third capacitor, a first end of the third capacitor is electrically connected to the second end of the second resistor, and a second end of the third capacitor is electrically connected to the operational amplifier circuit.
Preferably, the operational amplifier circuit includes a fourth resistor, a fourth capacitor, and an operational amplifier, a first end of the fourth resistor is electrically connected to a second end of the third capacitor and a first pin of the operational amplifier, a second end of the fourth resistor is grounded, a first end of the fourth capacitor is electrically connected to a sixth pin of the operational amplifier, and a second end of the fourth capacitor is electrically connected to a fifth pin of the operational amplifier.
Preferably, the third leg of the operational amplifier is grounded.
Preferably, the third signal coupling circuit includes a fifth capacitor, a first end of the fifth capacitor is electrically connected to the fourth pin of the operational amplifier, and a second end of the fifth capacitor is electrically connected to the speaker.
The utility model discloses following beneficial effect has: the utility model is electrically connected with the power supply and the first signal coupling circuit through the signal receiving circuit to receive the audio signal and decode the audio signal; the first signal coupling circuit is electrically connected with the transistor signal amplifying circuit so as to couple the decoded audio signal to the transistor signal amplifying circuit; the transistor signal amplifying circuit is electrically connected with the power supply and the second signal coupling circuit so as to amplify the signal output by the first signal coupling circuit and output the amplified signal to the second signal coupling circuit; the signal output end of the operational amplification circuit is electrically connected with the signal input end of the third signal coupling circuit; and the signal output end of the third signal coupling circuit is electrically connected with the loudspeaker. In addition, the technical scheme of integrating decoding and signal receiving reduces a large amount of repeated labor, reduces the cost, and avoids the problem of carrying out a large amount of repeated labor in the process of repeatedly changing the circuit layout to meet new market requirements.
Drawings
Fig. 1 is a circuit diagram of the signal receiving and decoding circuit of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples. It should be noted that, if there is no conflict, the embodiments and various features in the embodiments of the present invention may be combined with each other, and all are within the scope of the present invention.
Referring to fig. 1, the present invention provides a signal receiving and decoding circuit, which includes a signal receiving circuit 1, a first signal coupling circuit 2, a transistor signal amplifying circuit 3, a second signal coupling circuit 4, an operational amplifying circuit 5, a third signal coupling circuit 6, a speaker 7 and a power Vcc, wherein the signal receiving circuit 1 is electrically connected to the power Vcc and the first signal coupling circuit 2, and is configured to receive an audio signal and decode the audio signal, that is, the circuit integrates signal receiving and decoding. The first signal coupling circuit 2 is electrically connected to the transistor signal amplifying circuit 3, and is configured to couple the decoded audio signal to the transistor signal amplifying circuit 3.
The transistor signal amplifying circuit 3 is electrically connected to the power Vcc and the second signal coupling circuit 4, and is configured to amplify the signal output by the first signal coupling circuit 2 and output the amplified signal to the second signal coupling circuit 4. The signal input end of the operational amplifier circuit 5 is electrically connected with the signal output end of the second signal coupling circuit 4, and the signal output end of the operational amplifier circuit 5 is electrically connected with the signal input end of the third signal coupling circuit 6. The signal output end of the third signal coupling circuit 6 is electrically connected with the loudspeaker 7.
The signal receiving circuit 1 comprises an antenna L, a signal receiving decoding chip U1, a first capacitor C1 and a first resistor R1, wherein the antenna L is electrically connected with a second pin (IN pin) of the signal receiving decoding chip U1, a first end of the first capacitor C1 is electrically connected with a third pin (L0 pin) of the signal receiving decoding chip U1, and a second end of the first capacitor C1 is electrically connected with a fourth pin (L1 pin) of the signal receiving decoding chip U1. The first end of the first resistor R1 is electrically connected with the sixth pin (OUT pin) of the signal receiving decoding chip U1, and the second end of the first resistor R1 is electrically connected with the fifth pin of the signal receiving decoding chip U1 and grounded.
In this embodiment, the signal receiving and decoding chip U1 is JDD400, and compared with the prior art, the technical solution of integrating decoding and signal receiving together reduces a lot of repetitive labor, reduces cost, and avoids the problem of performing a lot of repetitive labor during repeatedly changing circuit layout to meet new market requirements.
The first signal coupling circuit 2 comprises a second capacitor C2, a first end of the second capacitor C2 is electrically connected with the sixth pin of the signal receiving decoding chip U1, and a second end of the second capacitor C2 is electrically connected with the transistor signal amplifying circuit 3. Through the first signal coupling circuit 2, the noise signal output by the signal receiving decoding chip U1 can be filtered.
The transistor signal amplifying circuit 3 comprises a second resistor R2, a third resistor R3 and a first triode Q, wherein a first end of the second resistor R2 is electrically connected with a power supply Vcc, and a second end of the second resistor R2 is electrically connected with a collector of the first triode Q. The first end of the third resistor R3 is electrically connected with the second end of the second resistor R2, and the second end of the third resistor R3 is electrically connected with the second end of the second capacitor C2. The base electrode of the first triode Q is electrically connected with the second end of the second capacitor C2, and the emitter electrode of the first triode Q is grounded.
The second signal coupling circuit 4 includes a third capacitor C3, a first terminal of the third capacitor C3 is electrically connected to a second terminal of the second resistor R2, and a second terminal of the third capacitor C3 is electrically connected to the operational amplifier circuit 5. By means of the second signal coupling circuit 4, noise signals output by the further transistor signal amplifying circuit 3 can be filtered out.
The operational amplifier circuit 5 includes a fourth resistor R4, a fourth capacitor C4, and an operational amplifier U2, wherein a first end of the fourth resistor R4 is electrically connected to a second end of the third capacitor C3 and a first pin of the operational amplifier U2, a second end of the fourth resistor R4 is grounded, a first end of the fourth capacitor C4 is electrically connected to a sixth pin of the operational amplifier U2, and a second end of the fourth capacitor C4 is electrically connected to a fifth pin of the operational amplifier U2. The third leg of the operational amplifier U2 is connected to ground. In this embodiment, the model of the operational amplifier circuit 5 is LM 386. Because the monopole gain of triode amplification is relatively low, can not form the degree of depth feedback like operational amplifier U2, consequently, the utility model discloses a set up operational amplifier circuit 5 is in order to solve this problem.
The third signal coupling circuit 6 comprises a fifth capacitor C5, a first terminal of the fifth capacitor C5 is electrically connected to the fourth pin of the operational amplifier U2, and a second terminal of the fifth capacitor C5 is electrically connected to the speaker 7. Noise signals can be further filtered out through the third signal coupling circuit 6, so that the signals which can be output are pure.
To sum up, the utility model discloses a signal receiving circuit 1 with power Vcc reaches 2 electricity of first signal coupling circuit are connected to receive audio signal and decode audio signal. The first signal coupling circuit 2 is electrically connected to the transistor signal amplifying circuit 3 to couple the decoded audio signal to the transistor signal amplifying circuit 3. The transistor signal amplifying circuit 3 is electrically connected to the power Vcc and the second signal coupling circuit 4, so as to amplify the signal output by the first signal coupling circuit 2 and output the amplified signal to the second signal coupling circuit 4. And the signal output end of the operational amplification circuit 5 is electrically connected with the signal input end of the third signal coupling circuit 6. The signal output end of the third signal coupling circuit 6 is electrically connected with the loudspeaker 7. In addition, the technical scheme of integrating decoding and signal receiving reduces a large amount of repeated labor, reduces the cost, and avoids the problem of carrying out a large amount of repeated labor in the process of repeatedly changing the circuit layout to meet new market requirements.
The signal receiving and decoding circuit provided by the present invention is introduced in detail, and a specific example is applied to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the concrete implementation and the application scope. To sum up, this description content only does the embodiment of the utility model, not therefore the restriction the patent scope of the utility model, all utilize the equivalent structure or the equivalent flow transform that the content of the description and the attached drawing was done, or directly or indirectly use in other relevant technical field, all the same reason is included in the patent protection scope of the utility model, should not be understood as right the utility model discloses a restriction.
Claims (8)
1. A signal receiving and decoding circuit is characterized by comprising a signal receiving circuit, a first signal coupling circuit, a transistor signal amplifying circuit, a second signal coupling circuit, an operational amplifying circuit, a third signal coupling circuit, a loudspeaker and a power supply, wherein the signal receiving circuit is electrically connected with the power supply and the first signal coupling circuit and is used for receiving an audio signal and decoding the audio signal; the first signal coupling circuit is electrically connected with the transistor signal amplifying circuit and is used for coupling the decoded audio signal to the transistor signal amplifying circuit; the transistor signal amplifying circuit is electrically connected with the power supply and the second signal coupling circuit and is used for amplifying the signal output by the first signal coupling circuit and outputting the amplified signal to the second signal coupling circuit; the signal input end of the operational amplification circuit is electrically connected with the signal output end of the second signal coupling circuit, and the signal output end of the operational amplification circuit is electrically connected with the signal input end of the third signal coupling circuit; and the signal output end of the third signal coupling circuit is electrically connected with the loudspeaker.
2. The signal receiving and decoding circuit according to claim 1, wherein the signal receiving circuit comprises an antenna, a signal receiving and decoding chip, a first capacitor, and a first resistor, the antenna is electrically connected to the second pin of the signal receiving and decoding chip, a first end of the first capacitor is electrically connected to the third pin of the signal receiving and decoding chip, and a second end of the first capacitor is electrically connected to the fourth pin of the signal receiving and decoding chip; the first end of the first resistor is electrically connected with the sixth pin of the signal receiving decoding chip, and the second end of the first resistor is electrically connected with the fifth pin of the signal receiving decoding chip and grounded.
3. The signal receiving and decoding circuit of claim 2, wherein the first signal coupling circuit comprises a second capacitor, a first end of the second capacitor is electrically connected to the sixth pin of the signal receiving and decoding chip, and a second end of the second capacitor is electrically connected to the transistor signal amplifying circuit.
4. The signal receiving and decoding circuit of claim 3, wherein the transistor signal amplifying circuit comprises a second resistor, a third resistor, and a first transistor, a first end of the second resistor is electrically connected to a power source, and a second end of the second resistor is electrically connected to a collector of the first transistor; a first end of the third resistor is electrically connected with a second end of the second resistor, and a second end of the third resistor is electrically connected with a second end of the second capacitor; and the base electrode of the first triode is electrically connected with the second end of the second capacitor, and the emitting electrode of the first triode is grounded.
5. The signal receiving and decoding circuit of claim 4, wherein the second signal coupling circuit comprises a third capacitor, a first end of the third capacitor is electrically connected to the second end of the second resistor, and a second end of the third capacitor is electrically connected to an operational amplifier circuit.
6. The signal receiving and decoding circuit of claim 5, wherein the operational amplifier circuit comprises a fourth resistor, a fourth capacitor, and an operational amplifier, a first terminal of the fourth resistor is electrically connected to a second terminal of the third capacitor and a first pin of the operational amplifier, a second terminal of the fourth resistor is grounded, a first terminal of the fourth capacitor is electrically connected to a sixth pin of the operational amplifier, and a second terminal of the fourth capacitor is electrically connected to a fifth pin of the operational amplifier.
7. The signal receiving decoding circuit of claim 6, wherein the third pin of the operational amplifier is grounded.
8. The signal receiving and decoding circuit of claim 6, wherein the third signal coupling circuit comprises a fifth capacitor, a first terminal of the fifth capacitor is electrically connected to the fourth pin of the operational amplifier, and a second terminal of the fifth capacitor is electrically connected to the speaker.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922103220.8U CN210670531U (en) | 2019-11-29 | 2019-11-29 | Signal receiving and decoding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922103220.8U CN210670531U (en) | 2019-11-29 | 2019-11-29 | Signal receiving and decoding circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210670531U true CN210670531U (en) | 2020-06-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201922103220.8U Active CN210670531U (en) | 2019-11-29 | 2019-11-29 | Signal receiving and decoding circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210670531U (en) |
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2019
- 2019-11-29 CN CN201922103220.8U patent/CN210670531U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518000 Guangdong city of Shenzhen province Futian District Che Kung Temple Tairan nine road Haisong building B-1303 Patentee after: Shenzhen smart Micro Intelligent Technology Co., Ltd Address before: 518000 Guangdong city of Shenzhen province Futian District Che Kung Temple Tairan nine road Haisong building B-1303 Patentee before: JWIPC TECHNOLOGY DEVELOPMENT Ltd. |
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| CP01 | Change in the name or title of a patent holder |