CN210670530U - Computer sleep wake-up circuit - Google Patents
Computer sleep wake-up circuit Download PDFInfo
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- CN210670530U CN210670530U CN201921848998.5U CN201921848998U CN210670530U CN 210670530 U CN210670530 U CN 210670530U CN 201921848998 U CN201921848998 U CN 201921848998U CN 210670530 U CN210670530 U CN 210670530U
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Abstract
The utility model discloses a computer sleep wake-up circuit, which comprises a time delay circuit, a first switch circuit, an adjusting circuit, a resonance circuit, a loudspeaker, a second switch circuit and a power supply, wherein the time delay circuit is electrically connected with the first switch circuit and the second switch circuit and is used for controlling the on-off of the first switch circuit; the first switch circuit is electrically connected with the adjusting circuit and used for controlling the adjusting circuit; the adjusting circuit is electrically connected with the second switch circuit and the resonant circuit and is used for adjusting the voltage output to the resonant circuit; the resonance circuit is electrically connected with the loudspeaker and is used for controlling the loudspeaker to sound; the second switch circuit is electrically connected with the power supply and used for controlling the on-off of the power supply. The utility model has the advantages of simple circuit structure, humanization, user experience are good.
Description
Technical Field
The utility model relates to a computer technology field, in particular to use computer sleep wake-up circuit on computer.
Background
One third of the life of a person spends in sleep, and more or less for school, work or entertainment, each person suffers from problems of insufficient sleep, insomnia, poor sleep and insufficient energy after waking. Here we intend to create high quality sleep with a sophisticated sleep system.
Currently, sleep problems are concentrated in the aspects of difficulty in falling asleep, light sleep, early awakening and the like. And long-term low-quality sleep can cause distraction, fatigue, weakness, even headache, dreaminess, hyperhidrosis and memory deterioration, and can cause a series of clinical symptoms and induce a series of physical and mental diseases in severe cases. In order to work on time, people usually set an alarm clock to remind people through the alarm clock, and then the sound of the alarm clock is usually fixed, so that people are usually awakened by the alarm clock in sleep. Therefore, the existing alarm is not humanized and has poor user experience.
SUMMERY OF THE UTILITY MODEL
The utility model provides a technical problem be, provide a humanized, user experience good computer sleep wake-up circuit.
The utility model provides a computer sleep wake-up circuit, which comprises a time delay circuit, a first switch circuit, an adjusting circuit, a resonance circuit, a loudspeaker, a second switch circuit and a power supply, wherein the time delay circuit is electrically connected with the first switch circuit and the second switch circuit and is used for controlling the on-off of the first switch circuit; the first switch circuit is electrically connected with the adjusting circuit and used for controlling the adjusting circuit; the adjusting circuit is electrically connected with the second switch circuit and the resonant circuit and is used for adjusting the voltage output to the resonant circuit; the resonance circuit is electrically connected with the loudspeaker and is used for controlling the loudspeaker to sound; the second switch circuit is electrically connected with the power supply and used for controlling the on-off of the power supply.
Preferably, the delay circuit includes a first resistor, a first capacitor, a second capacitor and a first chip, a first end of the first resistor is electrically connected to a first end of the first capacitor and a second pin and a sixth pin of the first chip, and a second end of the first resistor is grounded; the second end of the first capacitor is electrically connected with the fourth pin and the eighth pin of the first chip; the first end of the second capacitor is electrically connected with the fifth pin of the first chip, and the second end of the second capacitor is grounded; the first pin of the first chip is grounded, the third pin of the first chip is electrically connected with the first switch circuit, and the eighth pin of the first chip is electrically connected with the second switch circuit.
Preferably, the first switch circuit comprises a first diode and a second resistor, a first end of the first diode is electrically connected with the third pin of the first chip, and a second end of the first diode is electrically connected with a first end of the second resistor; the first end of the second resistor is electrically connected with the adjusting circuit, and the second end of the second resistor is grounded.
Preferably, the adjusting circuit comprises a third resistor and a first triode, a first end of the third resistor is electrically connected with a collector of the first triode, and a second end of the third resistor is electrically connected with a base of the first triode; and the collector of the first triode is electrically connected with the second switch circuit, the base of the first triode is electrically connected with the first end of the second resistor, and the emitter of the first triode is electrically connected with the resonance circuit.
Preferably, the resonant circuit includes a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a second chip, a first end of the fourth resistor is electrically connected to the emitter of the first triode, and a second end of the fourth resistor is electrically connected to a first end of the fifth resistor and a seventh pin of the second chip; the second end of the fifth resistor is electrically connected with the first end of the third capacitor, the second pin of the second chip and the ground pin; the second end of the third capacitor is grounded; a first end of the fourth capacitor is electrically connected with a fifth pin of the second chip, and a second end of the fourth capacitor is electrically connected with the loudspeaker and the first pin of the second chip; the first end of the fifth capacitor is electrically connected with the first end of the fourth resistor, the fourth corner pin and the eighth pin of the second chip, and the second end of the fifth capacitor is grounded; and the first end of the sixth capacitor is electrically connected with the third pin of the second chip, and the second end of the sixth capacitor is connected with the loudspeaker.
Preferably, the second switching circuit includes a second triode and a sixth resistor, an emitter of the second triode is electrically connected to the eighth pin of the first chip and a collector of the first triode, a base of the second triode is electrically connected to a first end of the sixth resistor, and the collector of the second triode is electrically connected to a second end of the sixth resistor and the power supply.
Preferably, the first chip and the second chip are both 555 chips.
The utility model discloses following beneficial effect has: the utility model discloses a cooperation between delay circuit, first switch circuit, adjusting circuit, resonant circuit, speaker, second switch circuit and the power, when reaching user setting's time, computer controller control the second switch is opened, makes the power do the delay circuit power supply makes and passes through adjusting circuit exports extremely resonant circuit's voltage is by little grow to make resonant circuit control the sound of speaker is by the sound production of little grow. The user is awakened by the sound of the loudspeaker slowly in the sleep process, so that the intelligent sleep control device is humanized, good in user experience, simple in circuit structure and low in cost.
Drawings
Fig. 1 is a circuit diagram of the sleep wake-up circuit of the computer of the present invention.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings and examples. It should be noted that, if there is no conflict, the embodiments and various features in the embodiments of the present invention may be combined with each other, and all are within the scope of the present invention.
Referring to fig. 1, the present invention provides a sleep wake-up circuit for a computer, which includes a delay circuit 1, a first switch circuit 2, an adjusting circuit 3, a resonant circuit 4, a speaker 5, a second switch circuit 6 and a power Vcc, wherein the delay circuit 1 is electrically connected to the first switch circuit 2 and the second switch circuit 6 for controlling the on/off of the first switch circuit 2. The first switch circuit 2 is electrically connected to the adjustment circuit 3, and is configured to control the adjustment circuit 3. The adjusting circuit 3 is electrically connected to the second switch circuit 6 and the resonant circuit 4, and is configured to adjust the magnitude of the voltage output to the resonant circuit 4. The resonant circuit 4 is electrically connected with the loudspeaker 5 and is used for controlling the loudspeaker 5 to sound. The second switch circuit 6 is electrically connected with the power supply Vcc and is used for controlling the on-off of the power supply Vcc.
The delay circuit 1 comprises a first resistor R1, a first capacitor C1, a second capacitor C2 and a first chip U1, wherein a first end of the first resistor R1 is electrically connected with a first end of the first capacitor C1 and a second pin and a sixth pin of the first chip U1, and a second end of the first resistor R1 is grounded. The second end of the first capacitor C1 is electrically connected to the fourth pin and the eighth pin of the first chip U1. The first end of the second capacitor C2 is electrically connected with the fifth pin of the first chip U1, and the second end of the second capacitor C2 is grounded. The first pin of the first chip U1 is grounded, the third pin of the first chip U1 is electrically connected to the first switch circuit 2, and the eighth pin of the first chip U1 is electrically connected to the second switch circuit 6. The first capacitor C1 is charged slowly, so that the first switch circuit 2 is turned on in a delayed manner.
The first switch circuit 2 includes a first diode D having a first terminal electrically connected to the third pin of the first chip U1, and a second resistor R2 having a second terminal electrically connected to the first terminal of the second resistor R2. A first terminal of the second resistor R2 is electrically connected to the adjusting circuit 3, and a second terminal of the second resistor R2 is grounded. The switch circuit has the advantages of simple structure and low cost, and does not need a complex transistor switch circuit.
The adjusting circuit 3 comprises a third resistor R3 and a first triode Q1, wherein a first end of the third resistor R3 is electrically connected with a collector of the first triode Q1, and a second end of the third resistor R3 is electrically connected with a base of the first triode Q1. The collector of the first transistor Q1 is electrically connected to the second switch circuit 6, the base of the first transistor Q1 is electrically connected to the first end of the second resistor R2, and the emitter of the first transistor Q1 is electrically connected to the resonant circuit 4.
The resonant circuit 4 includes a fourth resistor R4, a fifth resistor R5, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, and a second chip U2, wherein a first end of the fourth resistor R4 is electrically connected to an emitter of the first triode Q1, and a second end of the fourth resistor R4 is electrically connected to a first end of the fifth resistor R5 and a seventh pin of the second chip U2. The second end of the fifth resistor R5 is electrically connected with the first end of the third capacitor C3, the second pin of the second chip U2 and the ground pin. The second terminal of the third capacitor C3 is grounded. A first terminal of the fourth capacitor C4 is electrically connected to the fifth pin of the second chip U2, and a second terminal of the fourth capacitor C4 is electrically connected to the speaker 5 and the first pin of the second chip U2. The first end of the fifth capacitor C5 is electrically connected to the first end of the fourth resistor R4 and the fourth and eighth pins of the second chip U2, and the second end of the fifth capacitor C5 is grounded. A first end of the sixth capacitor C6 is electrically connected to the third pin of the second chip U2, and a second end of the sixth capacitor C6 is connected to the speaker 5.
The second switch circuit 6 comprises a second triode Q2 and a sixth resistor R6, wherein an emitter of the second triode Q2 is electrically connected with an eighth pin of the first chip U1 and a collector of the first triode Q1, a base of the second triode Q2 is electrically connected with a first end of the sixth resistor R6 and is used for being electrically connected with a computer controller, and a collector of the second triode Q2 is electrically connected with a second end of the sixth resistor R6 and a power supply Vcc. The first chip U1 and the second chip U2 are both 555 chips. When the time set by the user is reached, the computer controller controls the second switch circuit 6 to be switched on, the first capacitor C1 starts to be charged, the third pin of the first chip U1 outputs a low level, the diode D is cut off, the voltage output by the first triode is low, and the sound of the loudspeaker is small. On the contrary, when the first capacitor C1 is fully charged, the diode D is turned on, the voltage output by the first triode is high, and the sound of the speaker is loud.
To sum up, the utility model discloses a cooperation between delay circuit 1, first switch circuit 2, adjusting circuit 3, resonant circuit 4, speaker 5, second switch circuit 6 and the power Vcc, when reaching the time that the user set for, computer controller control second switch circuit 6 is opened, makes power Vcc do delay circuit 1 power supply makes to pass through adjusting circuit 3 output extremely resonant circuit 4's voltage is by little grow to make resonant circuit 4 control speaker 5's sound is by the sound production of little grow. The user is awakened by the sound of the loudspeaker 5 slowly during sleeping, so that the system is more humanized and has good user experience.
The computer sleep wake-up circuit provided by the present invention is introduced in detail, and a specific example is applied to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the concrete implementation and the application scope. To sum up, this description content only does the embodiment of the utility model, not therefore the restriction the patent scope of the utility model, all utilize the equivalent structure or the equivalent flow transform that the content of the description and the attached drawing was done, or directly or indirectly use in other relevant technical field, all the same reason is included in the patent protection scope of the utility model, should not be understood as right the utility model discloses a restriction.
Claims (8)
1. A computer sleep wake-up circuit is characterized by comprising a delay circuit, a first switch circuit, an adjusting circuit, a resonance circuit, a loudspeaker, a second switch circuit and a power supply, wherein the delay circuit is electrically connected with the first switch circuit and the second switch circuit and is used for controlling the on-off of the first switch circuit; the first switch circuit is electrically connected with the adjusting circuit and used for controlling the adjusting circuit; the adjusting circuit is electrically connected with the second switch circuit and the resonant circuit and is used for adjusting the voltage output to the resonant circuit; the resonance circuit is electrically connected with the loudspeaker and is used for controlling the loudspeaker to sound; the second switch circuit is electrically connected with the power supply and used for controlling the on-off of the power supply.
2. The computer sleep wake-up circuit according to claim 1, wherein the delay circuit comprises a first resistor, a first capacitor, a second capacitor and a first chip, a first end of the first resistor is electrically connected to a first end of the first capacitor and a second pin and a sixth pin of the first chip, and a second end of the first resistor is grounded; the second end of the first capacitor is electrically connected with the fourth pin and the eighth pin of the first chip; the first end of the second capacitor is electrically connected with the fifth pin of the first chip, and the second end of the second capacitor is grounded; the first pin of the first chip is grounded, the third pin of the first chip is electrically connected with the first switch circuit, and the eighth pin of the first chip is electrically connected with the second switch circuit.
3. The computer sleep wake-up circuit according to claim 2, wherein the first switch circuit comprises a first diode and a second resistor, a first terminal of the first diode is electrically connected to the third pin of the first chip, and a second terminal of the first diode is electrically connected to a first terminal of the second resistor; the first end of the second resistor is electrically connected with the adjusting circuit, and the second end of the second resistor is grounded.
4. The computer sleep wake-up circuit according to claim 3, wherein the adjusting circuit comprises a third resistor and a first triode, a first end of the third resistor is electrically connected with a collector of the first triode, and a second end of the third resistor is electrically connected with a base of the first triode; and the collector of the first triode is electrically connected with the second switch circuit, the base of the first triode is electrically connected with the first end of the second resistor, and the emitter of the first triode is electrically connected with the resonance circuit.
5. The computer sleep wake-up circuit according to claim 4, wherein the resonant circuit comprises a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, and a second chip, wherein a first end of the fourth resistor is electrically connected to the emitter of the first transistor, and a second end of the fourth resistor is electrically connected to a first end of the fifth resistor and a seventh pin of the second chip; the second end of the fifth resistor is electrically connected with the first end of the third capacitor, the second pin of the second chip and the ground pin; the second end of the third capacitor is grounded; a first end of the fourth capacitor is electrically connected with a fifth pin of the second chip, and a second end of the fourth capacitor is electrically connected with the loudspeaker and the first pin of the second chip; the first end of the fifth capacitor is electrically connected with the first end of the fourth resistor, the fourth corner pin and the eighth pin of the second chip, and the second end of the fifth capacitor is grounded; and the first end of the sixth capacitor is electrically connected with the third pin of the second chip, and the second end of the sixth capacitor is connected with the loudspeaker.
6. The sleep wake-up circuit of claim 5, wherein the second switching circuit comprises a second transistor and a sixth resistor, an emitter of the second transistor is electrically connected to the eighth pin of the first chip and a collector of the first transistor, a base of the second transistor is electrically connected to a first terminal of the sixth resistor, and a collector of the second transistor is electrically connected to a second terminal of the sixth resistor and the power supply.
7. The sleep wake-up circuit of claim 5, wherein the first chip and the second chip are both 555 chips.
8. The computer sleep wake-up circuit according to claim 2, wherein the first capacitor is an electrolytic capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921848998.5U CN210670530U (en) | 2019-10-30 | 2019-10-30 | Computer sleep wake-up circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921848998.5U CN210670530U (en) | 2019-10-30 | 2019-10-30 | Computer sleep wake-up circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210670530U true CN210670530U (en) | 2020-06-02 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921848998.5U Active CN210670530U (en) | 2019-10-30 | 2019-10-30 | Computer sleep wake-up circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210670530U (en) |
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2019
- 2019-10-30 CN CN201921848998.5U patent/CN210670530U/en active Active
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Address after: 518000 Guangdong city of Shenzhen province Futian District Che Kung Temple Tairan nine road Haisong building B-1303 Patentee after: Shenzhen smart Micro Intelligent Technology Co., Ltd Address before: 518000 Guangdong city of Shenzhen province Futian District Che Kung Temple Tairan nine road Haisong building B-1303 Patentee before: JWIPC TECHNOLOGY DEVELOPMENT Ltd. |