CN210670026U - Output buffer for audio analyzer - Google Patents
Output buffer for audio analyzer Download PDFInfo
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- CN210670026U CN210670026U CN201920893430.9U CN201920893430U CN210670026U CN 210670026 U CN210670026 U CN 210670026U CN 201920893430 U CN201920893430 U CN 201920893430U CN 210670026 U CN210670026 U CN 210670026U
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Abstract
The utility model discloses an output buffer for audio analyzer, including input buffer circuit and output buffer circuit, input buffer circuit will receive audio analyzer's signal and export for after buffering, fortune are put output buffer circuit, output buffer circuit is buffered the signal once more, after fortune is put output for the load simultaneously with this signal feedback to input buffer circuit, connect the input signal that its output signal range of setting for after being surveyed the article equals the article to be surveyed basically, this can conveniently measure the input signal range of being surveyed the article, avoid loaded down with trivial details impedance to calculate, promoted efficiency of software testing.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the field of electricity, in particular to an output buffer for an audio analyzer.
[ background of the invention ]
At present, the customized DSP power amplifier high-level input impedances of different customers are different, some of the customized DSP power amplifier high-level input impedances are only 100 omega or 47 omega, and the minimum output impedance of the balanced interface of the audio analyzer is also 100 omega. When a tested object with input impedance of only 47 omega is tested, the maximum output of the audio analyzer is 16Vrms, but a signal received by the tested object is only 5.12Vrms, so that the tested object can not meet the testing requirement.
Some methods in the prior art use the existing car power amplifier chip as the output buffer of the audio analyzer, but the audio quality output by the existing consumption-level and car-level power amplifier chips often cannot meet the test requirement, because the test result shows that the signal to noise ratio is only 105dB and the separation degree is only 90dB at most, the signal quality of the tested product is seriously influenced.
[ summary of the invention ]
In order to solve the above problems, the present invention provides an output buffer for an audio analyzer, which can reduce output impedance, maintain output voltage, and obtain an accurate test result.
In order to achieve the purpose, the invention provides the following technical scheme:
the output buffer for the audio analyzer comprises an input buffer circuit 1 and an output buffer circuit 2, wherein the input buffer circuit 1 outputs a signal received by the audio analyzer 3 to the output buffer circuit 2 after buffering and operational amplification, and the output buffer circuit 2 outputs the signal to a load 4 after buffering again and operational amplification and simultaneously feeds back the signal to the input buffer circuit 1.
As a preferred embodiment, further defined is: the model of the operational amplifier U1 is NE 5532.
As a preferred embodiment, further defined is: the input buffer circuit 1 comprises an operational amplifier U1, a pin 3 of the operational amplifier U1 is electrically connected with a differential signal input IN + end and one end of a resistor R12, the other end of the resistor R12 is grounded, a pin 2 of the operational amplifier U1 is a feedback signal input end, a pin 4 of the operational amplifier U1 is electrically connected with one end of capacitors C4 and C5 which are connected IN parallel and one end of a resistor R16, the other end of the capacitors C4 and C5 which are connected IN parallel is grounded, the other end of the resistor R16 is connected with a negative 15V voltage, a pin 8 of the operational amplifier U1 is electrically connected with one end of capacitors C1 and C3 which are connected IN parallel and one end of a resistor R2, the other end of the capacitor R2 is connected with a positive 15V voltage, the other end of the capacitors C1 and C3 which are connected IN parallel is grounded, and a pin 1 of the operational amplifier U1 is a signal output OUT.
As a preferred embodiment, further defined is: the output buffer circuit 2 includes a resistor R8, one end of the resistor R8 is electrically connected to the DV end, the other end of the resistor R2 is electrically connected to the negative electrode of the diode D2 and the positive electrode of the diode D3, the positive electrode of the diode D2 is electrically connected to the negative electrode of the diode D1, the positive electrode of the diode D1 is electrically connected to one end of the resistor R1, the base of the transistor Q1, and one end of the capacitor C2, the other end of the resistor R1 is electrically connected to the collector of the transistor Q1, the collector of the transistor Q2, the collector of the transistor Q3, positive 15V voltage, and one end of the capacitor C9, the other end of the capacitor C9 is grounded, the negative electrode of the diode D3 is electrically connected to the positive electrode of the diode D4, the negative electrode of the diode D4 is electrically connected to one end of the resistor R17, one end of the capacitor C6, the collector of the transistor Q6, and the other end of the resistor R17 is, A collector of the transistor Q4, a collector of the transistor Q5, a negative 15V voltage, and one end of a capacitor C10 are electrically connected, the other end of the capacitor C10 is grounded, the other end of the capacitor C6 is electrically connected with one end of a resistor R13, the other end of the resistor R13 is electrically connected with one end of a resistor R5, a junction between the resistor R13 and the resistor R5 is grounded, the other end of the resistor R5 is electrically connected with the other end of the capacitor C2, an emitter of the transistor Q1 is electrically connected with an emitter of the transistor Q1 through a resistor R1, an emitter of the transistor Q1 is electrically connected with the emitter of the transistor Q1 through a resistor R1 and a resistor R1 connected in series, the emitter of the transistor Q1 is electrically connected with the emitter of the transistor Q1 through a resistor R1 and a resistor R1 connected in series, two junctions are electrically connected between the emitter of the transistor Q1 and the resistor R1 with a base of the transistor Q1, two nodes are arranged between the emitter of the triode Q6 and the resistor R9, one node is electrically connected with the base of the triode Q4 through the resistor R14, the other node is electrically connected with the base of the triode Q5 through the resistor R15, and the node between the resistor R6 and the resistor R10 is connected with the node between the resistor R7 and the resistor R11 and then connected with an AMP _ OUT end.
The beneficial effects of the invention are as follows:
1. the invention solves the problem that the audio output quality of a product cannot be accurately measured by using an AP audio analyzer due to too low input impedance of some DSP power amplifiers customized by customers.
2. The invention also solves the problem that the production line can not measure the DSP power amplifier with low input impedance.
3. This output buffer is because output impedance is lower, consequently, connects its output signal amplitude of setting after the measured article and is equal to the input signal of measured article basically, and this input signal amplitude that can conveniently measure the measured article avoids loaded down with trivial details impedance to calculate, has promoted efficiency of software testing.
[ description of the drawings ]
FIG. 1 is a schematic diagram of the inventive structure;
FIG. 2 is a circuit diagram of an input buffer circuit;
fig. 3 is a circuit diagram of an output buffer circuit.
[ detailed description ] embodiments
The invention is described in further detail below with reference to the following figures and detailed description:
as shown in fig. 1-3, an output buffer for an audio analyzer includes an input buffer circuit 1 and an output buffer circuit 2, where the input buffer circuit 1 buffers and amplifies a signal received by the audio analyzer 3 and outputs the signal to the output buffer circuit 2, the output buffer circuit 2 buffers and amplifies the signal again and outputs the signal to a load 4, and simultaneously feeds back the signal to the input buffer circuit 1, and a model of the operational amplifier U1 is NE 5532.
IN this embodiment, the input buffer circuit 1 includes an operational amplifier U1, a pin 3 of the operational amplifier U1 is electrically connected to a differential signal input IN + terminal and one end of a resistor R12, the other end of the resistor R12 is grounded, a pin 2 of the operational amplifier U1 is a feedback signal input terminal, a pin 4 of the operational amplifier U1 is electrically connected to one end of capacitors C4 and C5 connected IN parallel and one end of a resistor R16 connected IN parallel, the other end of the capacitors C4 and C5 connected IN parallel is grounded, the other end of the resistor R16 is connected to a negative 15V voltage, a pin 8 of the operational amplifier U1 is electrically connected to one end of capacitors C1 and C3 connected IN parallel and one end of a resistor R2, the other end of the resistor R2 is connected to a positive 15V voltage, the other end of the capacitors C1 and C3 connected IN parallel is grounded, and a pin 1 of the operational amplifier U1 is a signal output OUT + terminal.
In this embodiment, the output buffer circuit 2 includes a resistor R8, one end of the resistor R8 is electrically connected to the DV terminal, the other end of the resistor R2 is electrically connected to the negative electrode of the diode D2 and the positive electrode of the diode D3, the positive electrode of the diode D2 is electrically connected to the negative electrode of the diode D1, the positive electrode of the diode D1 is electrically connected to one end of the resistor R1, the base of the transistor Q1, and one end of the capacitor C2, the other end of the resistor R1 is electrically connected to the collector of the transistor Q1, the collector of the transistor Q2, the collector of the transistor Q3, the positive 15V voltage, and one end of the capacitor C9, the other end of the capacitor C9 is grounded, the negative electrode of the diode D3 is electrically connected to the positive electrode of the diode D4, the negative electrode of the diode D4 is electrically connected to one end of the resistor R17, one end of the capacitor C6, the collector of the transistor Q6, and the other end of the resistor R17, A collector of the transistor Q4, a collector of the transistor Q5, a negative 15V voltage, and one end of a capacitor C10 are electrically connected, the other end of the capacitor C10 is grounded, the other end of the capacitor C6 is electrically connected with one end of a resistor R13, the other end of the resistor R13 is electrically connected with one end of a resistor R5, a junction between the resistor R13 and the resistor R5 is grounded, the other end of the resistor R5 is electrically connected with the other end of the capacitor C2, an emitter of the transistor Q1 is electrically connected with an emitter of the transistor Q1 through a resistor R1, an emitter of the transistor Q1 is electrically connected with the emitter of the transistor Q1 through a resistor R1 and a resistor R1 connected in series, the emitter of the transistor Q1 is electrically connected with the emitter of the transistor Q1 through a resistor R1 and a resistor R1 connected in series, two junctions are electrically connected between the emitter of the transistor Q1 and the resistor R1 with a base of the transistor Q1, two nodes are arranged between the emitter of the triode Q6 and the resistor R9, one node is electrically connected with the base of the triode Q4 through the resistor R14, the other node is electrically connected with the base of the triode Q5 through the resistor R15, and the node between the resistor R6 and the resistor R10 is connected with the node between the resistor R7 and the resistor R11 and then connected with an AMP _ OUT end.
The working principle and the working process are as follows:
1. the differential signal of the audio analyzer 3 is input from the pin 3 in fig. 2, and after input buffering, the signal is output from the pin 1 to the DV interface of the output buffer line.
2. The output buffer circuit of fig. 3 adopts a fully-discrete design, a signal is given to the load 4 from the output AMP _ OUT end and is fed back to the pin 2, the output buffer circuit 2 adopts a darlington connection mode to enable the audio analyzer 3 to output 15.5Vrms, carry 47 omega, output signals 15.5Vrms, the output signals are not lower than 99%, the signal-to-noise ratio is greater than 140dB, the absolute value of the separation degree is greater than 130dB, the frequency response curve is flat and straight, and the test requirements of the instrument are met.
3. The design of the buffer is realized by following the voltage of the input signal, and in a certain range, the buffer is not limited by the magnitude of load impedance, and the output buffer circuit is pushed by using a discrete device, so that the output current is improved, and the equivalent impedance is reduced.
Claims (3)
1. The output buffer for the audio analyzer is characterized by comprising an input buffer circuit (1) and an output buffer circuit (2), wherein the input buffer circuit (1) outputs a signal received by the audio analyzer (3) to the output buffer circuit (2) after buffering and operational amplification, and the output buffer circuit (2) outputs the signal to a load (4) after buffering and operational amplification again and simultaneously feeds the signal back to the input buffer circuit (1).
2. The output buffer for audio analyzer according to claim 1, wherein the input buffer circuit (1) includes an operational amplifier U1, pin 3 of the operational amplifier U1 is electrically connected to the differential signal input IN + terminal and one terminal of the resistor R12, the other end of the resistor R12 is grounded, pin 2 of the operational amplifier U1 is a feedback signal input terminal, the pin 4 of the operational amplifier U1 is electrically connected with one end of the capacitor C4 and the capacitor C5 which are connected in parallel and one end of the resistor R16 respectively, the other end of the capacitor C4 and the capacitor C5 which are connected in parallel is grounded, the other end of the resistor R16 is connected with negative 15V voltage, the pin 8 of the operational amplifier U1 is electrically connected with one end of the capacitor C1 and the capacitor C3 which are connected in parallel and one end of the resistor R2 respectively, the other end of the R2 is connected with positive 15V voltage, the other end of the capacitor C1 and the capacitor C3 which are connected in parallel is grounded, and the pin 1 of the operational amplifier U1 is a signal output OUT + end.
3. The output buffer for audio analyzer according to claim 2, wherein the output buffer circuit (2) comprises a resistor R8, one end of the resistor R8 is electrically connected to the DV terminal, the other end of the resistor R2 is electrically connected to the cathode of the diode D2 and the anode of the diode D3, the anode of the diode D2 is electrically connected to the cathode of the diode D1, the anode of the diode D1 is electrically connected to one end of the resistor R1, the base of the transistor Q1 and one end of the capacitor C2, the other end of the resistor R1 is electrically connected to the collector of the transistor Q1, the collector of the transistor Q2, the collector of the transistor Q3, the positive 15V voltage and one end of the capacitor C9, the other end of the capacitor C9 is grounded, the cathode of the diode D3 is electrically connected to the anode of the diode D4, and the cathode of the diode D4 is electrically connected to the anode of the one end of the resistor R17 and the cathode of the diode D17, One end of a capacitor C6 and a collector of a transistor Q6 are electrically connected, the other end of the resistor R17 is electrically connected with a collector of a transistor Q6, a collector of a transistor Q4, a collector of a transistor Q5, a negative 15V voltage, and one end of a capacitor C10, respectively, the other end of the capacitor C10 is grounded, the other end of the capacitor C6 is electrically connected with one end of a resistor R13, the other end of the resistor R13 is electrically connected with one end of a resistor R5, a junction between the resistor R13 and the resistor R13 is grounded, the other end of the resistor R13 is electrically connected with the other end of the capacitor C13, an emitter of the transistor Q13 is electrically connected with an emitter of the transistor Q13 through the resistor R13 and the emitter of the transistor Q13, an emitter of the transistor Q13 is electrically connected with the emitter of the transistor Q13 through the resistor R13 and the emitter of the transistor Q13 in series, two junctions are provided between the emitter of the transistor Q13 and the resistor R13, one node is electrically connected with the base of the triode Q2 through a resistor R3, the other node is electrically connected with the base of the triode Q3 through a resistor R4, two nodes are arranged between the emitter of the triode Q6 and a resistor R9, one node is electrically connected with the base of the triode Q4 through a resistor R14, the other node is electrically connected with the base of the triode Q5 through a resistor R15, and the node between the resistor R6 and the resistor R10 is connected with the node between the resistor R7 and the resistor R11 and then connected with an AMP _ OUT end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920893430.9U CN210670026U (en) | 2019-06-13 | 2019-06-13 | Output buffer for audio analyzer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920893430.9U CN210670026U (en) | 2019-06-13 | 2019-06-13 | Output buffer for audio analyzer |
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| Publication Number | Publication Date |
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| CN210670026U true CN210670026U (en) | 2020-06-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201920893430.9U Active CN210670026U (en) | 2019-06-13 | 2019-06-13 | Output buffer for audio analyzer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116566338A (en) * | 2023-04-27 | 2023-08-08 | 先歌国际影音股份有限公司 | Audio amplifying circuit |
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2019
- 2019-06-13 CN CN201920893430.9U patent/CN210670026U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116566338A (en) * | 2023-04-27 | 2023-08-08 | 先歌国际影音股份有限公司 | Audio amplifying circuit |
| CN116566338B (en) * | 2023-04-27 | 2024-02-09 | 先歌国际影音股份有限公司 | Audio amplifying circuit |
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