CN210629353U

CN210629353U - Driving capability self-adaptive direct-current voltage conversion circuit

Info

Publication number: CN210629353U
Application number: CN201921719516.6U
Authority: CN
Inventors: 周勇; 徐平; 于江
Original assignee: Ningbo Chaosuda Communication Technology Co ltd
Current assignee: Ningbo Chaosuda Communication Technology Co ltd
Priority date: 2019-10-15
Filing date: 2019-10-15
Publication date: 2020-05-26
Anticipated expiration: 2029-10-15

Abstract

The utility model relates to a power management field provides a drive ability self-adaptation DC voltage converting circuit, including drive control circuit and a plurality of group by switch PMOS pipe, power PMOS pipe, the DC voltage converting circuit that potential control circuit constitutes, drive control circuit output corresponding quantity's switching signal be connected with the grid one-to-one of switch PMOS pipe respectively, the drain electrode of switch PMOS pipe be connected with the grid one-to-one of power PMOS pipe respectively, potential control circuit output control signal also be connected with the grid one-to-one of power PMOS pipe respectively, the drain electrode of power PMOS pipe all is connected to the output potential and supplies power for load circuit, the output potential feed back level signal to drive control circuit and potential control circuit's input. The utility model discloses a drive ability self-adaptation direct current voltage conversion circuit can self-adaptively adjust voltage and drive current for the load power supply.

Description

Driving capability self-adaptive direct-current voltage conversion circuit

Technical Field

The utility model relates to a power management field more precisely relates to a drive ability self-adaptation direct current voltage converting circuit.

Background

The dc voltage conversion circuit is a commonly used power management chip in an integrated circuit chip, and the low dropout linear voltage regulator circuit is often used in the field of on-chip power management due to its characteristics of fast response, good ripple characteristics, and convenient integration. However, because the size of the power tube is fixed in the conventional scheme, the output driving capability of the low dropout linear voltage regulator circuit is also fixed. In the application field with large variation of load power consumption characteristics, the output voltage has large fluctuation, especially in a load circuit with extremely low power consumption in standby and sharply increased power consumption in working, the low-dropout linear voltage regulator circuit in the traditional scheme is difficult to meet the design requirements in both standby and working conditions, and the working reliability of the load circuit is affected.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is to provide a drive ability self-adaptation direct current voltage converting circuit, can be suitable for the great load circuit of load consumption characteristic change, to load circuit's different working property, voltage and drive current for the load power supply are adjusted to the self-adaptation ground.

The technical solution of the utility model is to provide a driving capability self-adaptive DC voltage conversion circuit, which comprises a driving control circuit and a plurality of groups of DC voltage conversion circuits composed of a switch PMOS tube, a power PMOS tube and a potential regulating circuit, the source ends and body ends of the switch PMOS tube and the power PMOS tube are both connected with a power supply, the driving control circuit outputs a corresponding number of switching signals which are respectively connected with the grids of the PMOS transistors in a one-to-one correspondence way, the drain electrodes of the switch PMOS tubes are respectively connected with the grid electrodes of the power PMOS tubes in a one-to-one correspondence way, the output regulation signals of the potential regulation and control circuit are respectively connected with the grids of the power PMOS tubes in a one-to-one correspondence way, the drain electrodes of the power PMOS tubes are connected to an output potential and supply power to the load circuit, and the output potential feeds a level signal back to the input ends of the drive control circuit and the potential regulation and control circuit.

Compared with the prior art, the utility model discloses a have following advantage: the level signal of the output potential is fed back to the drive control circuit and the potential regulation and control circuit, so that the switch PMOS tube can be controlled to be switched on and off, the power PMOS tube is further controlled to be switched on or switched off, and the voltage drop of the load circuit and the drive current of the load circuit are adaptively regulated.

Preferably, the potential regulating circuit comprises a reference voltage source, an operational amplifier, a resistor R1 and a resistor R2; the reference voltage source generates a reference voltage which is electrically connected with the inverting input end of the operational amplifier; one end of the resistor R1 is connected with the input end of the potential regulating circuit, the other end of the resistor R1 is simultaneously connected with one end of the resistor R2 and the non-inverting input end of the operational amplifier, and the other end of the resistor R2 is grounded; the operational amplifier outputs a regulation signal. By adopting the structure, the grid voltage value of the resistance value of the power PMOS transistor can be set and regulated by adjusting the reference voltage generated by the reference voltage source and the resistances of the resistor R1 and the resistor R2.

Preferably, the drive control circuit comprises a weakening judgment module, an enhancing judgment module, a plurality of stages of triggers of which the number corresponds to that of the switch PMOS tubes, and a forward transmission unit and a reverse transmission unit of which the number corresponds to that of the triggers; in the multi-stage trigger, the input of the first stage trigger is connected with a high level, the output of each stage of trigger is transmitted to the input of the next stage trigger through a forward transmission unit, the output of each stage of trigger except the second stage is transmitted to the input of the previous stage trigger through a reverse transmission unit, and the input of the last stage trigger is connected with a low level through a reverse transmission unit; the weakening judgment module outputs a weakening signal for controlling the on or off of the reverse transmission unit; the enhancement judging module outputs an enhancement signal for controlling the on or off of the forward transmission unit; the input ends of the weakening judgment module and the strengthening judgment module are the input ends of the drive control circuit. By adopting the structure, the power PMOS tubes can be adaptively adjusted to be switched on or switched off one by one, and further the voltage and the driving current for supplying power to the load are gradually adjusted.

Preferably, the weakening judgment module comprises a reference voltage source, an operational amplifier, a resistor R3 and a resistor R4; the reference voltage source generates a reference voltage which is electrically connected with the inverting input end of the operational amplifier; one end of the resistor R3 is connected with the input end of the weakening judgment module, the other end of the resistor R3 is simultaneously connected with one end of the resistor R4 and the non-inverting input end of the operational amplifier, and the other end of the resistor R4 is grounded; and the output signal of the operational amplifier is modulated by the inverter and then outputs a weakening signal. With this structure, the analog signal output by the operational amplifier becomes a digital signal after being modulated by the inverter, and the on/off of the reverse transmission unit can be reliably controlled.

Preferably, the enhancement judging module comprises a reference voltage source, an operational amplifier, a resistor R5 and a resistor R6; the reference voltage source generates a reference voltage which is electrically connected with the inverting input end of the operational amplifier; one end of the resistor R5 is connected with the input end of the enhancement judging module, the other end of the resistor R5 is simultaneously connected with one end of the resistor R6 and the non-inverting input end of the operational amplifier, and the other end of the resistor R6 is grounded; and the output signal of the operational amplifier is modulated by the two-stage inverter and then outputs an enhanced signal. By adopting the structure, the analog signal output by the operational amplifier becomes a digital signal after being modulated by the two-stage inverter, and the on or off of the forward transmission unit can be reliably controlled.

Preferably, the forward transmission unit and the reverse transmission unit are both transmission gate structures. The structure is adopted to transmit signals, and the circuit is simple.

Drawings

Fig. 1 is an overall circuit diagram of the driving capability adaptive dc voltage converting circuit of the present invention.

Fig. 2 is a circuit diagram of the electric potential regulating module of the present invention.

Fig. 3 is a circuit diagram of the driving regulation module of the present invention.

Fig. 4 is a circuit diagram of the weakening judgment module of the present invention.

Fig. 5 is a circuit diagram of the enhancement judgment module of the present invention.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification.

It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "including," and/or "containing," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Further, when a statement such as "… at least one" appears after the list of listed features, the entire listed feature is modified rather than modifying individual elements in the list.

As shown in fig. 1, in the driving capability adaptive dc voltage converting circuit of the present invention, K1, K2, K3, and K4 are four small PMOS transistors, P1, P2, P3, and P4 are four large power PMOS transistors, a voltage control module B1 is used for generating control voltage signals VC1, VC2, VC3, and VC4, and a driving control module B2 is used for generating switching signals VK1, VK2, VK3, and VK 4. The source ends of K1, K2, K3 and K4 are all connected with a power supply VDD, the grid ends of the K1, K2, K4 are respectively connected with switching signals VK1, VK2, VK3 and VK4, and the drain ends of the K8926, K3526 and K3552 are respectively connected with the grid ends of P1, P2, P3 and P4; the source ends of the P1, the P2, the P3 and the P4 are all connected with a power supply VDD, the drain ends of the P1, the P2, the P3 and the P4 are all connected to an output potential Vout, and the output potential Vout is used for supplying power to a load circuit; the output voltage Vout is also fed back to the voltage regulation block B1 and the input terminal Vsin of the driving regulation block B2. The design requirement of the output potential Vout in this embodiment is 1.2V. When the grid of the PMOS tube is connected with a high level, the two ends of the source and the drain are in a high-resistance disconnection state; when the grid of the PMOS tube is connected with a low level, the source and drain ends are in a low-resistance conduction state; the grid of the PMOS tube is connected with low levels with different sizes, and the on-resistances at the two ends of the source and the drain of the PMOS tube are different; the body ends of all the PMOS tubes are connected with a power supply VDD.

The utility model discloses a potential control module contains four same circuits, and the output of every circuit is regulation and control electric potential VC1, VC2, VC3 and VC4 respectively, as shown in fig. 2, every circuit includes a reference voltage source B1_ D1, an operational amplifier B1_ D2, resistance R1 and resistance R2; the reference voltage source B1_ D1 generates a reference voltage independent of temperature, power supply voltage and process parameter floating, which is electrically connected to the inverting input terminal of the operational amplifier B1_ D2; one end of the resistor R1 is connected with the input end Vsin, the other end of the resistor R1 is simultaneously connected with one end of the resistor R2 and the non-inverting input end of the operational amplifier B1_ D2, and the other end of the resistor R2 is grounded; the operational amplifier B1_ D2 outputs the regulated potential VC. In this embodiment, the reference voltage generated by the reference voltage source B1_ D1 is 0.9V, the resistor R1 and the resistor R2 are 2000 ohms and 6000 ohms, respectively, the Vsin terminal is a pin through which the output potential Vout is connected, and the non-inverting input terminal of the operational amplifier B1_ D2 is connected to the resistor R1 and the resistor R2 to divide the sampling potential. If the electric potential of Vout is higher, the output electric potential VC of the operational amplifier B1_ D2 is increased, and since the grid voltage of the power PMOS tube is finally controlled by the regulation electric potential VC, and the higher the grid voltage of the PMOS tube is, the larger the on-resistance of the PMOS tube is, the voltage drop on the power PMOS tube is increased, the voltage drop of the load circuit is reduced, namely the effect of reducing the output electric potential Vout is realized. If the Vout potential is low, the output potential VC of the operational amplifier B1_ D2 is lowered, and since the lower the gate voltage of the PMOS transistor is, the smaller the on-resistance thereof becomes, the voltage drop across the power PMOS transistor decreases, and the voltage drop across the load circuit increases, that is, the output potential Vout increases.

As shown in fig. 3, the driving regulation module of the present invention includes four flip-flops DFF1, DFF2, DFF3, DFF4, outputs of which are respectively switching signals VK1, VK2, VK3, VK4, an input terminal of DFF1 is connected to power supply VDD, an input terminal of DFF2 is connected to transmission gates T1, T2, an input terminal of DFF3 is connected to transmission gates T3, T4, an input terminal of DFF4 is connected to transmission gates T5, T6; control signals of the transmission gates T1, T3 and T5 are inverted signals VEN of enhancement signals VE and VE output by the enhancement judgment module B3, and input ends of the control signals are respectively connected with switching signals VK1, VK2 and VK 3; the control signals of the transmission gates T6, T4, and T2 are inverted signals VDN of the muting signals VD and VD output by the muting judgment module B4, and input ends of the muting signals VDN are respectively connected to the power ground, the switching signal VK4, and the switching signal VK 3. Clock signals externally connected with the four flip-flops DFF1, DFF2, DFF3 and DFF4 are all low-frequency signals with the MHz magnitude.

The mute judgment module B4 is shown in FIG. 4 and comprises a reference voltage source B4_ D1, an operational amplifier B4_ D2, a resistor R3 and a resistor R4; the reference voltage source B4_ D1 generates a reference voltage independent of temperature, power supply voltage and process parameter floating, which is electrically connected to the inverting input terminal of the operational amplifier B4_ D2; one end of the resistor R3 is connected with the input end Vsin, the other end of the resistor R3 is simultaneously connected with one end of the resistor R4 and the non-inverting input end of the operational amplifier B4_ D2, and the other end of the resistor R4 is grounded; the output end of the operational amplifier B4_ D2 is connected with an inverter, and the inverter outputs the weakening signal VD. In this embodiment, the reference voltage generated by the reference voltage source B4_ D1 is 0.9V, the resistor R3 and the resistor R4 are 2000 ohms and 6000 ohms, respectively, the Vsin terminal is a pin through which the output potential Vout is connected, and the non-inverting input terminal of the operational amplifier B4_ D2 is connected to the resistor R3 and the resistor R4 to divide the sampling potential. If the potential Vout input by the Vsin terminal is higher than 1.25V, weakening the signal VD to be low level; conversely, if the potential Vout input at the Vsin terminal is lower than or equal to 1.25V, the mute signal VD becomes high.

The circuit of the enhancement judgment module B3 is shown in fig. 5, and includes a reference voltage source B3_ D1, an operational amplifier B3_ D2, a resistor R5 and a resistor R6; the reference voltage source B3_ D1 generates a reference voltage independent of temperature, power supply voltage and process parameter floating, which is electrically connected to the inverting input terminal of the operational amplifier B3_ D2; one end of the resistor R5 is connected with the input end Vsin, the other end of the resistor R5 is simultaneously connected with one end of the resistor R6 and the non-inverting input end of the operational amplifier B3_ D2, and the other end of the resistor R6 is grounded; the output of the operational amplifier B3_ D2 is terminated by two inverters which finally output the enhanced signal VE. In this embodiment, the reference voltage generated by the reference voltage source B3_ D1 is 0.9V, the resistor R5 and the resistor R6 are 2000 ohms and 6000 ohms, respectively, the Vsin terminal is a pin through which the output potential Vout is connected, and the non-inverting input terminal of the operational amplifier B3_ D2 is connected to the resistor R5 and the resistor R6 to divide the sampling potential. If the potential Vout input by the Vsin terminal is lower than 1.15V, the enhanced signal VE is at a low level; on the contrary, if the potential Vout of the Vsin terminal input is higher than or equal to 1.15V, the enhancement signal VE is high level.

In fig. 3, DFF1 samples one supply voltage VDD every clock cycle, i.e., is always high; if the output potential Vout is greater than 1.25V, VE is high level, VEN is low level, VD is low level, VDN is high level; if Vout is greater than 1.15V and less than 1.25V, VE is high level, VEN is low level, VD is high level, VDN is low level; if Vout is less than 1.15V, VE is low, VEN is high, VD is high, VDN is low. Three transmission gates of T1, T3 and T5 are turned on when VE is low level and VEN is high level, when Vout is continuously less than 1.15V, high level signals are transmitted to the VK1 output end of DFF1 after the first clock period, are transmitted to the VK2 output end of DFF2 after the second clock period, are transmitted to the VK2 output end of DFF2 after the third clock period, and are transmitted to the VK4 output end of DFF4 after the fourth clock period, the forward shift transmission characteristic is presented, and thus K1, K2, K3 and K4 are sequentially turned off. Three transmission gates T2, T4 and T6 are turned on when VD is low level and VDN is high level, when Vout is continuously larger than 1.25V, a low level signal is transmitted to the VK4 output terminal of DFF4 after the first clock period, is transmitted to the VK3 output terminal of DFF3 after the second clock period, and is transmitted to the VK2 output terminal of DFF2 after the third clock period, the characteristic of reverse shift transmission is presented, and K4, K3 and K2 are turned on in sequence. When Vout is between 1.15V and 1.25V, all transmission gates are turned off, and all flip-flops keep the original value.

The utility model discloses a driving capability self-adaptation direct current voltage converting circuit's theory of operation as follows:

after the circuit is electrified, when Vout in an initial state is at a low potential and VK1 is also at a low level, the K1 tube is conducted, because the source and drain ends of the K1 tube are in a low-resistance conducting state, the K1 tube forcibly pulls up the gate voltage of the P1 tube, and the P1 tube is in a high-resistance off state at the moment and cannot supply power to a load circuit; after the working state is entered, the switching signal VK1 is at a high level, the K1 tube is closed, and because the source and drain ends of the K1 tube are in a high-impedance disconnection state, the grid potential of the P1 tube is only controlled by VC1, and the control potential signals VC1, VC2, VC3 and VC4 are all at a low level, so that the P1 tube is in a normal working state and supplies power to a load circuit.

Because the DFF1 is connected with a high-level signal, the DFF1 always outputs a high-level VK1 signal, the K1 tube is always turned off, and the P1 tube is always turned on. If the value of Vout is lower than 1.15V, the power PMOS transistor which is connected needs to be increased, at the moment, the transmission gates T1, T3 and T5 are connected, DFF2 samples the VK1 value of high level through the transmission gate T1 in the next clock period, so that both VK1 and VK2 are high level, K1 and K2 are both off, and P1 and P2 are both connected; if the Vout is still lower than 1.15V in the next clock cycle, DFF3 samples the VK2 value to high level through the T3 transmission gate, so that VK1, VK2 and VK3 are all high level, K1, K2 and K3 are all turned off, and P1, P2 and P3 are all turned on; if the Vout is still lower than 1.15V in the next clock cycle, the DFF4 samples the VK3 value to a high level through the T5 transmission gate, so that the VK1, the VK2, the VK3 and the VK4 are all high levels, the K1, the K2, the K3 and the K4 are all turned off, and the P1, the P2, the P3 and the P4 are all turned on.

The driving control module B2 detects the value of the output potential Vout every clock cycle, and if it is higher than 1.25V, it needs to reduce the power PMOS transistors in operation, i.e. reduce the on-state P1, P2, P3, P4, and at this time, the transmission gates T6, T4, T2 are turned on. Because the T6 is connected with a low-level signal, the DFF4 outputs a VK4 signal with a low level, the K4 tube is conducted, the grid electrode of the P4 tube is forced to be pulled to a high level, and the P4 tube is turned off; if Vout is still higher than 1.25V in the next clock cycle, DFF3 will sample VK4 value to low level through T4 transmission gate, so that VK3 and VK4 are both low level, K3 and K4 are both turned on, and P3 and P4 are both turned off; if Vout is still higher than 1.25 in the next clock cycle, DFF2 samples VK3 to low level through T2 transmission gate, so that VK2, VK3 and VK4 are all low level, K2, K3 and K4 are all turned on, and P2, P3 and P4 are all turned off. Therefore, the power PMOS tubes in the working state are closed in sequence, the voltage value of the output potential Vout is reduced in a self-adaptive mode, and the driving current of the load circuit is reduced.

The utility model discloses an among the drive ability self-adaptation direct current voltage conversion circuit, large size power PMOS pipe P quantity can increase and decrease as required, is not restricted to 4 of this embodiment, simultaneously also the circuit in the quantity of the PMOS pipe K of corresponding increase and decrease small-size, electric potential regulation and control module B1 and the circuit of drive regulation and control module, makes PMOS pipe K of small-size, switching signal VK, regulation and control electric potential signal VC all unanimous with the quantity of large size power PMOS pipe P.

Claims

1. A driving capability self-adaptive direct-current voltage conversion circuit is characterized by comprising a driving control circuit and a plurality of groups of direct-current voltage conversion circuits consisting of switch PMOS tubes, power PMOS tubes and a potential regulation and control circuit, wherein the source ends and the body ends of the switch PMOS tubes and the power PMOS tubes are connected with a power supply, the driving control circuit outputs corresponding numbers of switch signals and is respectively connected with grids of the switch PMOS tubes in a one-to-one correspondence manner, drain electrodes of the switch PMOS tubes are respectively connected with the grids of the power PMOS tubes in a one-to-one correspondence manner, the potential regulation and control circuit outputs regulation and control signals and is also respectively connected with the grids of the power PMOS tubes in a one-to-one correspondence manner, the drain electrodes of the power PMOS tubes are connected to output potentials and supply power for a load circuit, and the output potentials feed level signals back to input ends of the driving control circuit and the potential regulation.

2. The driving capability adaptive DC voltage converting circuit according to claim 1, wherein the voltage level control circuit comprises a reference voltage source, an operational amplifier, a resistor R1 and a resistor R2; the reference voltage source generates a reference voltage which is electrically connected with the inverting input end of the operational amplifier; one end of the resistor R1 is connected with the input end of the potential regulating circuit, the other end of the resistor R1 is simultaneously connected with one end of the resistor R2 and the non-inverting input end of the operational amplifier, and the other end of the resistor R2 is grounded; the operational amplifier outputs a regulation signal.

3. The driving capability self-adaptive direct-current voltage conversion circuit according to claim 1, wherein the driving control circuit comprises a weakening judgment module, an enhancement judgment module, a plurality of stages of triggers corresponding to the number of the PMOS transistors, and forward transmission units and reverse transmission units corresponding to the number of the triggers; in the multi-stage trigger, the input of the first stage trigger is connected with a high level, the output of each stage of trigger is transmitted to the input of the next stage trigger through a forward transmission unit, the output of each stage of trigger except the second stage is transmitted to the input of the previous stage trigger through a reverse transmission unit, and the input of the last stage trigger is connected with a low level through a reverse transmission unit; the weakening judgment module outputs a weakening signal for controlling the on or off of the reverse transmission unit; the enhancement judging module outputs an enhancement signal for controlling the on or off of the forward transmission unit; the input ends of the weakening judgment module and the strengthening judgment module are the input ends of the drive control circuit.

4. The driving capability adaptive DC voltage converting circuit according to claim 3, wherein the weakening judgment module comprises a reference voltage source, an operational amplifier, a resistor R3 and a resistor R4; the reference voltage source generates a reference voltage which is electrically connected with the inverting input end of the operational amplifier; one end of the resistor R3 is connected with the input end of the weakening judgment module, the other end of the resistor R3 is simultaneously connected with one end of the resistor R4 and the non-inverting input end of the operational amplifier, and the other end of the resistor R4 is grounded; and the output signal of the operational amplifier is modulated by the inverter and then outputs a weakening signal.

5. The driving capability adaptive DC voltage converting circuit according to claim 3, wherein the boosting decision module comprises a reference voltage source, an operational amplifier, a resistor R5 and a resistor R6; the reference voltage source generates a reference voltage which is electrically connected with the inverting input end of the operational amplifier; one end of the resistor R5 is connected with the input end of the enhancement judging module, the other end of the resistor R5 is simultaneously connected with one end of the resistor R6 and the non-inverting input end of the operational amplifier, and the other end of the resistor R6 is grounded; and the output signal of the operational amplifier is modulated by the two-stage inverter and then outputs an enhanced signal.

6. The adaptive-driving-capability DC voltage converting circuit according to claim 3, wherein the forward transmission unit and the reverse transmission unit are transmission gate structures.