CN210607268U - Chip structure - Google Patents
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- CN210607268U CN210607268U CN201922074484.5U CN201922074484U CN210607268U CN 210607268 U CN210607268 U CN 210607268U CN 201922074484 U CN201922074484 U CN 201922074484U CN 210607268 U CN210607268 U CN 210607268U
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Abstract
The application provides a chip structure, and relates to the technical field of semiconductors. The chip structure comprises a substrate, a plurality of functional layers and functional electrodes, wherein the substrate is connected with the substrate layer by layer; the functional electrode is arranged on one side of the functional layer far away from the substrate; wherein, any one layer of the functional layers is provided with a through hole; the chip structure further comprises a detection electrode, and the detection electrode is arranged in the through hole. The chip structure provided by the application has the effects of distinguishing the defect properties and physical mechanisms of different functional layers and influencing the chip characteristics.
Description
Technical Field
The utility model relates to the field of semiconductor technology, particularly, relate to a chip architecture.
Background
An epitaxial structure of a High Electron Mobility Transistor (HEMT) includes a plurality of functional layers, and properties such as an energy band structure, a doping characteristic, and defect distribution of each layer are different, and an electrical mechanism of the HEMT is very complex. HEMT device characteristics such as threshold stability, dynamic resistance, reverse leakage and breakdown characteristics, etc. are also affected.
Therefore, it is necessary to perform a test analysis on the HEMT device to analyze the influence of each functional layer on the device parameters.
At present, the influence of the defect of the bulk material on the device is generally analyzed by using an external back potential, namely a test is carried out by applying a test voltage on a substrate, but the defect property and the influence mechanism of different positions of an epitaxial layer are difficult to distinguish by the test.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a chip architecture to solve be difficult to distinguish the defect nature and the influence mechanism of different functional layers among the prior art.
In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:
in a first aspect, the present application provides a chip structure, comprising:
a substrate;
a plurality of functional layers and functional electrodes connected with the substrate layer by layer; the functional electrode is arranged on one side of the functional layer far away from the substrate; wherein any one of the functional layers is provided with a through hole;
and the detection electrode is arranged on the through hole.
Furthermore, through holes are formed in the periphery of any one of the functional layers, and the detection electrodes are laid on the surfaces of the through holes.
Further, the plurality of functional layers include a buffer layer, a stress release layer, a high resistance layer, a channel layer, a barrier layer, and a cap layer, and the substrate, the buffer layer, the stress release layer, the high resistance layer, the channel layer, the barrier layer, and the cap layer are stacked layer by layer.
Further, the functional layers are all nitride functional layers.
Furthermore, the material for manufacturing the buffer layer comprises AlN, the material for manufacturing the stress release layer comprises AlGaN, the material for manufacturing the high-resistance layer comprises GaN, the material for manufacturing the channel layer comprises GaN, the material for manufacturing the barrier layer comprises AlGaN, and the material for manufacturing the cap layer comprises GaN.
In a second aspect, the present application further provides a method for manufacturing a chip structure, where the method includes:
providing a substrate;
sequentially extending a plurality of functional layers along the substrate;
manufacturing a through hole in any one of the functional layers;
and manufacturing a detection electrode on the through hole, and manufacturing a functional electrode on one layer far away from the substrate in the functional layers.
Further, the step of forming a via hole in any one of the functional layers includes:
and etching the functional layers around the chip structure to a target functional layer.
In a third aspect, the present application further provides a chip performance testing method, where the method is applied to the chip structure, and the method includes:
controlling the chip structure to be in different working states;
and applying a detection voltage on the detection electrode to test the working characteristics of the chip structure.
Further, the step of applying a detection voltage to the detection electrode to test the operating characteristics of the chip structure comprises:
and applying detection voltage to the detection electrode and the substrate to test the working characteristics of the chip structure.
Compared with the prior art, the method has the following beneficial effects:
the application provides a chip structure, which comprises a substrate, and a plurality of functional layers and functional electrodes which are connected with the substrate layer by layer; the functional electrode is arranged on one side of the functional layer far away from the substrate; wherein, any one layer of the functional layers is provided with a through hole; and the detection electrode is arranged on the through hole. Because the chip structure provided by the application can be provided with the through hole in any one functional layer, when the chip structure is in a conducting or cut-off state, the defect properties and the influence mechanism of different functional layers can be distinguished by applying test voltage on the test electrode of any one functional layer.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a cross-sectional view of a chip structure according to an embodiment of the present disclosure.
Fig. 2 is a schematic flowchart of a chip structure manufacturing method according to an embodiment of the present disclosure.
Fig. 3 is another schematic flowchart of a chip structure manufacturing method according to an embodiment of the present disclosure.
Fig. 4 is a schematic flowchart of a chip performance testing method according to an embodiment of the present application.
Fig. 5 is another schematic flowchart of a chip performance testing method provided in an embodiment of the present application.
In the figure: 100-chip architecture; 110-a substrate; 120-a buffer layer; 130-a stress release layer; 140-a high resistance layer; 150-a channel layer; 160-barrier layer; 170-a cap layer; 180-functional electrodes; 190-a detection electrode; 200-through hole.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.
In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
First embodiment
As described in the background, currently, for the analysis of chip structure, the influence of bulk material defects on the device is generally analyzed by applying an external back potential, i.e. a test is performed by applying a test voltage on a substrate, but such a test is difficult to distinguish the defect properties and influence mechanisms at different positions of an epitaxial layer.
When the device is in a reverse turn-off state, a high electric field can also extend into the whole epitaxial layer along the vertical direction, and charge and discharge of charges can be caused by the dislocation, the defect, the heterojunction structure and other factors of the material, so that the performance of the device is influenced.
It can be understood that the crystal quality, defect distribution, doping concentration, energy band width, surface roughness, polarization degree and other factors of different epitaxial layers are different, and the superposition effect is very complicated to reflect on the working characteristics of the HEMT device. Thus, applying voltages to different functional layers can affect device performance to varying degrees.
In view of this, the present application provides a chip structure, which applies voltages to different electrodes by providing through holes and detection electrodes on different functional layers, and further analyzes defect distribution and physical mechanisms of different epitaxial layers by detecting changes in device characteristics.
Referring to fig. 1, as a possible implementation manner of the present application, the chip structure 100 includes a substrate 110, a plurality of functional layers, a functional electrode 180, and a detection electrode 190, where the substrate 110 and the functional layers are connected layer by layer, and the functional electrode 180 is disposed on a side of the functional layers away from the substrate 110. And any one of the plurality of functional layers is provided with a through hole 200, and the detection electrode 190 is mounted in the through hole 200.
That is, when the chip structure 100 is fabricated, functional layers are first epitaxially grown on the substrate 110, and the through holes 200 are fabricated, and corresponding electrodes are fabricated at the same time. By applying voltage on different functional layers, the defect properties and influence mechanisms of different positions of the epitaxial layer are researched, and the operation of workers is facilitated.
It should be noted that as a possible implementation manner of the present application, the substrate 110 described in the present application may be any one of a sapphire substrate, a silicon carbide substrate, a diamond substrate, and a gallium nitride homogeneous substrate, and each functional layer is epitaxially grown on the substrate 110, which is not limited in this application.
Moreover, the chip structure 100 provided by the present application may be a HEMT structure, that is, the buffer layer 120, the stress release layer 130, the high resistance layer 140, the channel layer 150, the barrier layer 160, and the cap layer 170 are included in the plurality of functional layers described in the present application, and the substrate 110, the buffer layer 120, the stress release layer 130, the high resistance layer 140, the channel layer 150, the barrier layer 160, and the cap layer 170 are stacked layer by layer, and a gate electrode, a source electrode, and a drain electrode are disposed on the cap layer 170.
As a possible implementation manner of the present application, the plurality of functional layers provided in the present application are all nitride functional layers. For example, the buffer layer 120 is made of AlN, the stress relieving layer 130 is made of AlGaN, the high-resistance layer 140 is made of GaN, the channel layer 150 is made of GaN, the barrier layer 160 is made of AlGaN, and the cap layer 170 is made of GaN. Of course, it is understood that the functional layers of the present application may be made of other materials, for example, binary to quaternary compounds of Al, In, Ga, or N, and the present application does not limit the materials of the functional layers as long as the normal operation of the chip structure 100 can be achieved.
Moreover, when the via 200 is fabricated, etching is actually performed along the direction from the cap layer 170 to the substrate 110 to expose the target layer, for example, when it is required to determine the influence of voltage applied to the channel layer 150 on the device performance, a portion of the cap layer 170 and the barrier layer 160 may be etched away to expose the channel layer 150, and the detection electrode 190 may be fabricated on the channel layer 150. However, when the chip is turned on or off, a voltage is applied to the detection electrode 190, thereby detecting the influence of the voltage applied to the channel layer 150 on the device performance.
As a possible implementation manner of the present application, after testing the influence of different functional layers on the device performance after applying a voltage, a plurality of chip structures 100 may be simultaneously fabricated, and the through hole 200 of each chip structure 100 is disposed on different functional layers, for example, the through hole 200 is disposed on any one of the buffer layer 120, the stress release layer 130, the high resistance layer 140, the channel layer 150, and the barrier layer 160. And further, the influence of the voltage on the device performance is compared when the voltage is applied to different functional layers.
In order to make the voltage application more uniform, the through holes 200 are formed around any one of the plurality of functional layers, and the detection electrodes 190 are formed on the surfaces of the through holes 200, in order to form the through holes 200. That is, the through holes 200 are disposed around the chip structure 100, and when a voltage is applied, the voltage can be applied around the chip, so that the obtained result is more accurate.
Further, applying voltages across different functional layers as described in this application studies the leakage mechanism of each layer and the impact on the device, including but not limited to:
1. and adding high voltage to the detection electrode of the through hole so as to test the working characteristics of the device.
2. And adding high voltage to the detection electrode of the through hole so as to test the electric leakage of the substrate.
3. And adding scanning voltage to the detection electrode of the through hole, changing conditions such as scanning speed, polarity and the like, and testing the working characteristics of the device.
4. And testing capacitance-voltage (C-V) curves between the detection electrode of the through hole and the device electrode, and analyzing the device characteristics.
5. And testing a capacitance-voltage (C-V) curve between the detection electrode of the through hole and the substrate, and analyzing the material characteristics.
6. Various tests are carried out under the condition of variable temperature.
Second embodiment
Referring to fig. 2, the present application further provides a method for manufacturing a chip structure, including:
s101, providing a substrate.
And S102, sequentially extending a plurality of functional layers along the substrate.
S103, manufacturing a through hole in any one of the functional layers.
And S104, manufacturing a detection electrode on the through hole, and manufacturing a functional electrode on one layer far away from the substrate in the plurality of functional layers.
Referring to fig. 3, S103 may include:
and S1031, etching the plurality of functional layers around the chip structure to a target functional layer.
Of course, when the function electrode and the detection electrode are formed, they may be:
depositing source-drain metal and alloy to form ohmic contact, depositing a gate dielectric layer, depositing a gate metal layer, depositing through hole metal and forming contact.
And, the method further comprises depositing a passivation layer, which is not limited in any way in this application.
It should be noted that, in other embodiments, steps of the manufacturing method of the chip structure may be exchanged, for which the present implementation does not limit the steps of the manufacturing method of the chip structure at all, and any exchange of steps in other embodiments is included in the scope of the present invention.
Third embodiment
Referring to fig. 4, the present application further provides a chip performance testing method, which is applied to the chip structure according to the first embodiment, and the method includes:
s201, controlling the chip structure to be in different working states.
S202, applying a detection voltage on the detection electrode to test the working characteristics of the chip structure.
When the chip structure is in different working states, voltages can be applied to different functional layers or substrates so as to test the influence on the performance of the device. The operating characteristics of the chip structure include, but are not limited to, leakage, threshold voltage, turn-on current, etc. of the test chip.
In addition, after a voltage is applied to the function, the current can flow to the cap layer or the substrate, and when the voltage is analyzed to influence the device, the current only needs to flow to the cap layer.
In view of the above, in order to reduce the influence of the current flowing to the substrate, in the present application, referring to fig. 5, S202 may be:
and applying detection voltage to the detection electrode and the substrate to test the working characteristics of the chip structure.
By applying the detection voltage on the detection electrode and the substrate simultaneously, an equipotential can be formed between the functional layer provided with the detection electrode and the substrate, and then after the voltage is applied on the detection electrode, the direction of the current is only towards the capping layer, so that the effect is better.
In summary, the present application provides a chip structure, which includes a substrate, and a plurality of functional layers and functional electrodes connected to the substrate layer by layer; the functional electrode is arranged on one side of the functional layer far away from the substrate; wherein, any one layer of the functional layers is provided with a through hole; and the detection electrode is arranged on the through hole. Because the chip structure provided by the application can be provided with the through hole in any one functional layer, when the chip structure is in a conducting or cut-off state, the defect properties and the influence mechanism of different functional layers can be distinguished by applying test voltage on the test electrode of any one functional layer.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (6)
1. A chip structure, comprising:
a substrate;
a plurality of functional layers and functional electrodes connected with the substrate layer by layer; the functional electrode is arranged on one side of the functional layer far away from the substrate; wherein any one of the functional layers is provided with a through hole;
and the detection electrode is arranged on the through hole.
2. The chip structure according to claim 1, wherein a through hole is formed around any one of the functional layers, and the detection electrode is disposed on a surface of the through hole.
3. The chip structure of claim 1, wherein the plurality of functional layers comprise a buffer layer, a stress relief layer, a high resistance layer, a channel layer, a barrier layer, and a cap layer, the substrate, the buffer layer, the stress relief layer, the high resistance layer, the channel layer, the barrier layer, and the cap layer being stacked layer-by-layer.
4. The chip structure according to claim 3, wherein the plurality of functional layers are all nitride functional layers.
5. The chip structure according to claim 4, wherein the buffer layer is made of AlN, the stress relieving layer is made of AlGaN, the high-resistance layer is made of GaN, the channel layer is made of GaN, the barrier layer is made of AlGaN, and the cap layer is made of GaN.
6. The chip structure according to claim 1, wherein the substrate is any one of a sapphire substrate, a silicon carbide substrate, a diamond substrate, and a gallium nitride homogeneous substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111962157A (en) * | 2020-07-24 | 2020-11-20 | 山东天岳先进材料科技有限公司 | Healing method of silicon carbide crystal micropipe, silicon carbide product and application |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111962157A (en) * | 2020-07-24 | 2020-11-20 | 山东天岳先进材料科技有限公司 | Healing method of silicon carbide crystal micropipe, silicon carbide product and application |
| CN111962157B (en) * | 2020-07-24 | 2021-09-28 | 山东天岳先进科技股份有限公司 | Healing method of silicon carbide crystal micropipe, silicon carbide product and application |
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Address after: 510651 No. 363, Changxin Road, Guangzhou, Guangdong, Tianhe District Patentee after: Institute of semiconductors, Guangdong Academy of Sciences Address before: 510000 363 Changxin Road, Tianhe District, Guangzhou, Guangdong. Patentee before: GUANGDONG INSTITUTE OF SEMICONDUCTOR INDUSTRIAL TECHNOLOGY |
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