CN210575924U - Chip interconnection structure and chip - Google Patents

Abstract

The utility model provides a chip interconnection structure and chip, chip interconnection structure include first chip, second chip and at least one conducting component, first chip includes at least one first pad, the second chip includes at least one third pad that corresponds with the first pad; the conducting component set up in the second chip with between the first chip, every conducting component is used for connecting first pad with third pad, every conducting component includes at least one electrically conductive piece, the utility model provides a chip interconnect structure and chip can let two or more than two chip interconnect and high-speed communication.

Description

Chip interconnection structure and chip

Technical Field

The utility model relates to a semiconductor manufacturing technology field, in particular to chip interconnect structure and chip.

Background

With the development of semiconductor technology, the chip size tends to be miniaturized, and the communication speed of the chip is required to be higher and higher due to the development of technology.

At present, the traditional packaging mode depends on routing and a circuit board substrate to connect two or more chips, so that interconnection of pins among the chips is realized, and communication is completed. Wire bonding refers to the process of connecting the internal interconnection lines of solid circuits in microelectronic devices, i.e., the connection between chips and circuits or lead frames, which is commonly known in surface packaging technology, by using metal wires and utilizing hot pressing or ultrasonic energy sources.

However, when the above-mentioned conventional packaging method is used to interconnect two or more chips, the communication speed may have a bottleneck due to the excessively long wires of the lead and the substrate used when the two or more chips are interconnected, such as a decrease in the communication speed, and the power may need to be increased if the communication speed needs to be maintained. If two or more chips needing interconnection communication are directly manufactured on the same wafer, the production cost is greatly increased. Therefore, a chip interconnection technology capable of realizing high-speed communication is required.

SUMMERY OF THE UTILITY MODEL

The utility model provides a chip interconnect structure and chip can let two or more than two chip interconnect and high-speed communication.

In a first aspect, the present invention provides a chip interconnection structure, including:

a first chip including at least one first pad;

a second chip including at least one third pad corresponding to the first pad;

at least one conductive component disposed between the second chip and the first chip, each of the conductive components for connecting the first bonding pad and the third bonding pad, wherein each of the conductive components comprises at least one conductive member.

In the above chip interconnection structure, optionally, the at least two sequentially connected conductive members are stacked.

In the above chip interconnection structure, optionally, each of the conductive components includes a first conductive member and a second conductive member, a first end of the first conductive member is connected to the first pad, a second end of the first conductive member is butted against a first end of the second conductive member, and a second end of the second conductive member is connected to the third pad.

In the above chip interconnection structure, optionally, the conductive member is a metal member.

In the above chip interconnection structure, optionally, the first conductive member and the second conductive member are connected by soldering, or the first conductive member and the second conductive member are connected by a conductive adhesive.

In the above chip interconnection structure, the conductive member may be made of one or two of copper, silver, tin, gold, and aluminum.

In the above chip interconnection structure, optionally, the first conductive member and the second conductive member are conductive metals capable of forming a eutectic crystal.

In the above chip interconnection structure, optionally, when the first conductive component and the second conductive component are connected by soldering, a joint of the first conductive component and the second conductive component has a eutectic layer.

In the chip interconnection structure described above, optionally, the conductive member and the first pad or the third pad are of an integral structure.

In the above chip interconnection structure, optionally, the second end of the first conductive member and the first end of the second conductive member have the same cross-sectional shape.

In the above chip interconnection structure, optionally, the conductive member is vertically disposed between the third pad and the first pad.

In the chip interconnection structure as described above, the conductive member is optionally a cylinder or a prism.

As for the chip interconnection structure, optionally, the number of the second chips is at least two, and the second chips are all disposed on the same side of the first chip, or the second chips are disposed on the front and back sides of the first chip.

Optionally, in the chip interconnection structure described above, the first chip and the second chip are both single bare chips.

Optionally, the first chip includes a first wafer, the first wafer is provided with a first functional layer, the first functional layer is provided with the first pad, and the first functional layer is further provided with a second pad interconnected with an external circuit;

the second chip comprises a second wafer, a second functional layer is arranged on the second wafer, the third bonding pad is arranged on the second functional layer, and the conductive piece is connected between the third bonding pad and the first bonding pad.

As above, optionally, the first chip further includes a first insulating layer, the first insulating layer is provided with a first windowing structure communicated with the first pad, the second chip further includes a second insulating layer, the second insulating layer is provided with a second windowing structure communicated with the third pad, and the conductive member is located between the first windowing structure and the second windowing structure.

In the above chip interconnection structure, optionally, a sealing layer for sealing the conductive component is further disposed between the first chip and the second chip.

In a second aspect, the present invention provides a chip comprising a chip interconnect structure as described in any of the above.

The utility model provides a chip interconnection structure and chip, chip interconnection structure, including first chip and second chip, first chip includes at least one first pad, the second chip includes at least one third pad that corresponds with the first pad, conductive component sets up between second chip and the first chip, every conductive component is used for connecting the first pad with the third pad, every conductive component includes at least one conductive piece, the conductive piece is connected between the third pad of second chip and the first pad of first chip the utility model discloses connect between the first pad of first chip and the third pad of second chip through at least one conductive piece for the lead wire when at least more than two chips interconnect is the shortest, thereby reduces the power consumption of chip during operation, and then realize the high-speed communication of chip, consequently, the utility model provides a pair of chip interconnect structure and chip have realized two or more than two chip interconnect and can realize the high-speed communication's of interconnection chip purpose.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a chip interconnection structure according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another chip interconnection structure according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of an interconnection method according to a sixth embodiment of the present invention;

fig. 4 is a schematic structural diagram of a first wafer according to a sixth embodiment of the present invention;

fig. 5 is a schematic structural diagram of a second wafer according to a sixth embodiment of the present invention;

fig. 6 is a schematic structural diagram of a first chip according to a sixth embodiment of the present invention;

fig. 7 is a schematic structural diagram of a second chip according to a sixth embodiment of the present invention.

The attached drawings indicate the following:

1-a first chip;

101-a first conductive member;

102-a first wafer;

103-a first functional layer;

104-a first insulating layer;

105-a first pad;

106-second pad;

107-a first windowing structure;

2-a second chip;

201-a second conductive member;

202-a second wafer;

203-a second functional layer;

204-a second insulating layer;

205-third pad;

206-a second windowing structure;

3-a seal;

4-eutectic layer;

5-conductive adhesive.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

At present, the traditional packaging mode depends on routing and a circuit board substrate to connect two or more chips, so that interconnection of pins among the chips is realized, and communication is completed. As the technology develops, the communication speed of the chip is required to be higher and higher, and therefore, the communication speed of the chip cannot be reduced when the pins between the chips need to be interconnected. However, when the above conventional packaging method is used to interconnect two or more chips, the communication speed will be reduced, and if the communication speed of the chip needs to be maintained, the power needs to be increased. If two or more chips needing interconnection communication are directly manufactured on the same wafer, the production cost is greatly increased. When realizing the chip interconnection, the chip has normal communication speed, the utility model provides a chip interconnect structure and chip.

Example one

Fig. 1 is a schematic structural diagram of a chip interconnection structure provided in the first embodiment of the present invention, and fig. 2 is a schematic structural diagram of another chip interconnection structure provided in the first embodiment of the present invention.

The chip interconnection structure provided by the embodiment can be used for interconnection among chips in the field of semiconductor technicians, and is particularly suitable for interconnection among chips needing interconnection communication.

As shown in fig. 1 and 2, the chip interconnection structure includes: the chip comprises a first chip 1 and at least one second chip 2, wherein a transfer surface of the first chip 1 is opposite to a transfer surface of the second chip 2, and at least one conductive component is arranged between the second chip 2 and the first chip 1, wherein the first chip 1 comprises at least one first bonding pad 105, and the second chip 2 comprises at least one third bonding pad 205 corresponding to the first bonding pad 105; each for connecting the first pad 105 and the third pad 205, each comprising at least one conductive member connected between the first pad 105 and the third pad 205.

In this embodiment, the first chip 1 and the second chip 2 may be any chips that need to be interconnected for communication. In this embodiment, the first chip 1 and the second chip 2 may be a Micro Control Unit (MCU) chip and a Flash chip, and the first chip 1 and the second chip 2 may also be both storage chips, such as XROM chips, that is, the first chip 1 and the second chip 2 are not specifically limited in this embodiment, and the first chip 1 and the second chip 2 may be a logic chip, a storage chip, an image chip or a control chip.

In this embodiment, the transfer surface of the first chip 1 is a surface on which the first bonding pad 105 is disposed on the first chip 1, and the transfer surface of the second chip 2 is a surface on which the third bonding pad 205 is disposed on the second chip 2, in this embodiment, the transfer surface of the first chip 1 and the transfer surface of the second chip 2 are disposed oppositely, that is, when the first chip 1 and the second chip 2 are interconnected, the second chip 2 is reversely connected to the first chip 1, so that the first bonding pad 105 of the first chip 1 and the third bonding pad 205 of the second chip 2 are disposed oppositely, thereby facilitating to shorten the lead wire when the first chip 1 and the second chip 2 are interconnected as much as possible.

It should be noted that, in this embodiment, as shown in fig. 1 and fig. 3, since at least one second chip 2 needs to be interconnected with the first chip 1, a projected area of the first chip 1 on the at least one second chip 2 needs to be greater than or equal to a total area of the second chips 2, that is, when two or more second chips 2 are interconnected with the first chip 1, a projected area of the first chip 1 on the second chip 2 needs to be greater than or equal to a total area of all the second chips 2 interconnected with the first chip 1. In this embodiment, the area sizes of the first chip 1 and the second chip 2 are not further limited in this embodiment.

In this embodiment, as shown in fig. 1, the conductive component may be a conductive metal, in this embodiment, each conductive component includes at least one conductive component, at least one conductive component is disposed between the first chip 1 and the second chip 2, that is, at least one or more conductive components are included between the first chip 1 and the second chip 2, the conductive component is connected between the third pad 205 of the second chip 2 and the first pad 105 of the first chip 1, so that the first chip 1 and the second chip 2 can be electrically conducted, thereby realizing communication between the first chip 1 and the second chip 2, and the arrangement of the conductive component not only can greatly shorten a lead when the first chip 1 and the second chip 2 are interconnected, compared with a mode in the prior art in which two or more chips are connected by a wire bonding and a circuit board substrate without a wire bonding and a substrate wire winding, therefore, the power consumption of the chips during working is reduced, the high-speed communication of the chips is realized, the interconnection structure of the embodiment is simple and easy to operate, a complex process is not required to be introduced, and compared with the prior art that two or more chips needing interconnection communication are directly manufactured on the same wafer, the production cost can be greatly reduced.

In this embodiment, the conductive member and the first bonding pad 105 or the third bonding pad 205 are integrated, and in this embodiment, the conductive member may be integrated with the first bonding pad 105 of the first chip 1 and connected to the third bonding pad 205 of the second chip 2 through the conductive member; the conductive member may also be integrated with the third bonding pad 205 of the second chip 2, and connected to the first bonding pad 105 of the first chip 1 through the conductive member; that is, in the present embodiment, the first chip 1 and the second chip 2 can communicate with each other regardless of the method used.

It should be noted that, in this embodiment, the first pad 105 and the third pad 205 may be metal pads or other pads capable of implementing surface mount assembly of the first chip 1 and the second chip 2, where the pads are pads made of any material in the present embodiment.

It should be noted that, in this embodiment, the wafer on which the first chip 1 and the second chip 2 are respectively located is provided with a bonding pad before the wafer leaves a factory, and the surface of the wafer is provided with an insulating layer, and when the insulating layer provided by the wafer can reach the insulating standard and the protection standard that the theory in the prior art needs to meet, the insulating layer of the first chip 1 and the insulating layer of the second chip 2 do not need to be processed.

It should be noted that, in this embodiment, as shown in fig. 1, the conductive component may be an integrated structure or a split structure, that is, in this embodiment, when the conductive component is an integrated structure, the conductive component is located on the transfer surface of the first chip 1 or the second chip 2, when the conductive component is a split structure, the first portion of the conductive component is located on the first chip 1, the second portion of the conductive component is located on the second chip 2, and when the first chip 1 and the second chip 2 are interconnected, the first portion of the conductive component and the second portion of the conductive component are connected. In this embodiment, it is only necessary to ensure that the conductive member is connected between the third pad 205 of the second chip 2 and the first pad 105 of the first chip 1 to achieve the interconnection communication between the first chip 1 and the second chip 2, and the structure of the conductive member is not further limited in this embodiment.

In the present embodiment, as shown in fig. 1, in order to minimize the wire length when the first chip 1 and the second chip 2 are interconnected, the conductive member is vertically disposed between the third pad 205 of the second chip 2 and the first pad 105 of the first chip 1, so as to reduce power consumption when the first chip 1 and the second chip 2 operate, and implement high-speed communication between the first chip 1 and the second chip 2.

In this embodiment, the conductive element may be a cylinder, a prism, or other structures, that is, in this embodiment, the conductive element includes but is not limited to a cylinder or a prism.

In this embodiment, as shown in fig. 1, the first pad 105 of the first chip 1 is disposed on the interposer surface of the first chip 1, the third pad 205 of the second chip 2 is disposed on the interposer surface of the second chip 2, and the first pad 105 of the first chip 1 and the corresponding third pad 205 of the second chip 2 are interconnected through a conductive component.

In this embodiment, as shown in fig. 1, when the transfer surface of the first chip 1 and the transfer surface of the second chip 2 are oppositely disposed, the first bonding pads 105 and the third bonding pads 205 are oppositely disposed, and are equal in number and in one-to-one correspondence, and are connected between the third bonding pads 205 and the first bonding pads 105 through conductive members, so as to implement interconnection communication between the first chip 1 and the second chip 2.

It should be noted that, in this embodiment, as shown in fig. 1, the number of the first conductive members 101 on the first chip 1 is equal to and corresponds to the number of the first pads 105 on the first chip 1 one by one, and correspondingly, the number of the second conductive members 201 on the second chip 2 is equal to and corresponds to the number of the third pads 205 on the second chip 2 one by one, and in this embodiment, the number of the first conductive members 101 and the number of the second conductive members 201 are not further limited.

In this embodiment, the first chip 1 and the second chip 2 are both single bare chips.

In this embodiment, the bare chip is a chip in which a chip circuit is fabricated on a wafer and is cut from the wafer but is not completely packaged, that is, the first chip 1 and the second chip 2 interconnected in this embodiment are both single bare chips.

Specifically, compared with the flip chip in the prior art, the method is that tin lead balls are deposited on the bonding pads of the chip, and then the chip is turned over and heated to form the flip chip by combining the molten tin lead balls with the ceramic substrate. In the embodiment, two or more chips are interconnected through the conductive pieces, and the known flip chip connects the chips on the ceramic substrate through solder, so that the chip interconnection structure of the embodiment is different from the structure body of the flip chip.

Specifically, in the prior art, a single cut bare chip is flip-chip bonded to an uncut chip on a wafer, and finally, the chip is butt-welded to the whole wafer by dispensing, where the wafer in the CoW process is not cut, so that when the CoW process is used to realize the butt-welding of the chip to the whole wafer, it is necessary to introduce a special device and a special material, such as a wafer-level dispensing device and a thermally compressed non-conductive paste (TCNCP) material, where TCNCP is also called non-conductive thermosetting paste. Due to the introduction of wafer level dispensing equipment and TCNCP, the cost of interconnecting a chip and a whole wafer is greatly increased.

Compared with the CoW process in the prior art, the chip interconnection structure in the embodiment has the main function of two or more single bare chips, wherein each bare chip is an independent functional chip, so that the first chip 1 and the second chip 2 can be interconnected by using domestic conventional equipment, the purpose of high communication speed of the interconnected chips can be achieved, and wafer level dispensing equipment and TCNCP do not need to be introduced from foreign countries. Therefore, the chip interconnection structure of the embodiment has lower production cost. It should be noted that, in this embodiment, the conventional apparatus includes, but is not limited to, a chip-scale dispensing apparatus, and also includes other chip-scale packaging apparatuses. Compared with the mode of interconnecting the chip and the whole wafer by adopting the CoW process in the prior art, the interconnection main body of the embodiment is two or more single bare chips, and the interconnection of the chip can be realized by adopting chip-level dispensing equipment and chip-level other packaging equipment, so that the chip interconnection structure of the embodiment has lower production cost compared with the interconnection structure of the chip and the wafer manufactured by adopting the CoW process.

Therefore, the present embodiment provides a chip interconnection structure, which includes a first chip 1 and at least one second chip 2, wherein the interposer of the first chip 1 and the interposer of the second chip 2 are disposed opposite to each other, at least one conductive component is further disposed between the second chip 2 and the first chip 1, each conductive component includes at least one conductive element, the conductive element is connected between the third pad 205 of the second chip 2 and the first pad 105 of the first chip 1, the present invention is connected between the first pad 105 of the first chip 1 and the third pad 205 of the second chip 2 through the conductive element, leads are shortest when at least more than two chips are interconnected, thereby reducing the power consumption of the chips during operation, and then realize the high-speed communication of chip, consequently, the utility model provides a pair of chip interconnect structure and chip have realized two or more than two chip interconnect and can realize the high-speed communication's of interconnection chip purpose.

Example two

Further, on the basis of the above-mentioned embodiments, in this embodiment, as shown in fig. 1 and fig. 3, each conductive component includes at least two sequentially connected conductive members, wherein at least two sequentially connected conductive members are stacked, and the first pad 105 of the first chip 1 and the first pad 105 of the second chip 2 are connected by two or two sequentially connected conductive members.

In this embodiment, as shown in fig. 1 and 3, each conductive component includes a first conductive member 101 and a second conductive member 201, a first end of the first conductive member 101 is connected to the first pad 105 of the first chip 1, a second end of the first conductive member 101 is butted against a first end of the second conductive member 201, and a second end of the second conductive member 201 is connected to the third pad 205 of the second chip 2.

It should be noted that the first conductive member 101 is connected to the first bonding pad 105 of the first chip 1 and integrated with the first bonding pad 105 of the first chip 1, and the second conductive member 201 is connected to the third bonding pad 205 of the second chip 2 and integrated with the third bonding pad 205 of the second chip 2. In this embodiment, the first conductive member 101 and the second conductive member 201 connected to each other are located on the same central axis, so as to shorten a lead when the first chip 1 and the second chip 2 are interconnected, reduce power consumption when the first chip 1 and the second chip 2 operate, and implement high-speed communication between the first chip 1 and the second chip 2.

In this embodiment, the length, width and height of the conductive member are all in the micron level, preferably 1-100 um.

Wherein, in this embodiment, when the conductive piece is a cylinder, the diameter of the conductive pillar is preferably 45um, and the height is preferably 60 um.

In this embodiment, the conductive members are metal members, and the first conductive member 101 and the second conductive member 201 may be connected by welding. The welding method includes thermocompression bonding, reflow soldering, ultrasonic welding, or the like, and the welding method adapted to the material of the conductive component is selected according to the material specifically adopted by the conductive component.

In this embodiment, the conductive member is made of one or two of copper, silver, tin, gold, and aluminum. That is, in this embodiment, the materials of the first conductive member 101 and the second conductive member 201 may be the same material, or different materials may be used.

Specifically, in this embodiment, when the materials of the first conductive device 101 and the second conductive device 201 are the same, for example, when both the first conductive device 101 and the second conductive device 201 are tin, the second end of the first conductive device 101 and the first end of the second conductive device 201 are connected by the mutual melting and butt welding of tin and tin, preferably reflow welding, and when the first conductive device 101 and the second conductive device 201 are made of two materials of copper, silver, tin, gold, and aluminum, a certain welding method is adopted according to the selected materials.

Specifically, in this embodiment, the first conductive member 101 and the second conductive member 201 may be a combination of any two metals of copper, silver, tin, gold, and aluminum, and the first conductive member 101 and the second conductive member 201 may also be any two conductive metals of copper, silver, tin, gold, and aluminum capable of forming a eutectic crystal.

In this embodiment, the first conductive member 101 and the second conductive member 201 are conductive metals capable of forming a eutectic crystal, and when the first conductive member 101 and the second conductive member 201 are electrically connected by welding, the eutectic layer 4 is provided at the connection point of the first conductive member 101 and the second conductive member 201. Specifically, in this embodiment, when the first conductive member 101 and the second conductive member 201 are conductive metals capable of forming a eutectic, the first conductive member 101 and the second conductive member 201 may adopt a combination of tin and silver, tin and gold, gold and copper, gold and aluminum, and other conductive metals capable of forming a eutectic. In this embodiment, when the first conductive member 101 and the second conductive member 201 may use tin and silver, reflow soldering is preferably used, when the first conductive member 101 and the second conductive member 201 may use tin and gold or gold and copper, voltage soldering is preferably used, and when the first conductive member 101 and the second conductive member 201 may use gold and aluminum, ultrasonic soldering is preferably used, that is, in this embodiment, the materials and the soldering manner of the first conductive member 101 and the second conductive member 201 are not further limited.

Alternatively, as shown in fig. 2, the first conductive member 101 and the second conductive member 201 may be connected by a conductive paste 5. Specifically, in this embodiment, the conductive adhesive 5 is disposed between the second end of the first conductive member 101 and the first end of the second conductive member 201, and the first conductive member 101 and the second conductive member 201 are electrically connected through the conductive adhesive 5. Specifically, in this embodiment, the first conductive member 101 and the second conductive member 201 may be electrically connected by disposing the whole piece of conductive adhesive 5 between the first conductive member 101 and the second conductive member 201, or the first conductive member 101 and the second conductive member 201 may be electrically connected by disposing the single conductive adhesive 5 at the second end of the first conductive member 101 or the first end of the second conductive member 201 one by one. When the first conductive member 101 and the second conductive member 201 are connected by the conductive adhesive 5, the first conductive member 101 and the second conductive member 201 may be one or two of copper, silver, tin, gold, and aluminum.

Specifically, in this embodiment, when the first conductive device 101 and the second conductive device 201 are electrically connected by disposing the whole piece of conductive adhesive 5 between the first conductive device 101 and the second conductive device 201, the whole piece of conductive adhesive 5 between the first conductive device 101 and the second conductive device 201 forms the sealing layer 3 between the first chip 1 and the second chip 2 in the embodiment of the present invention while the first conductive device 101 and the second conductive device 201 are electrically connected by the whole piece of conductive adhesive 5. In this embodiment, the whole Conductive adhesive 5 may adopt an oriented Conductive adhesive having an oriented Conductive function, such as an Anisotropic Conductive Film (ACF), and presses Conductive particles in the ACF between the first Conductive member 101 and the second Conductive member 201 to achieve Conductive communication between the first chip 1 and the second chip 2.

Specifically, in this embodiment, when the first conductive member 101 and the second conductive member 201 are electrically connected by disposing the single conductive adhesives 5 on the second end of the first conductive member 101 or the first end of the second conductive member 201 one by one, the conductive adhesives between the first chip 1 and the second chip 2 are the single conductive adhesives 5, and the number of the conductive adhesives is opposite to and in one-to-one correspondence to the number of the first conductive member 101 or the second conductive member 201. The single conductive paste 5 in this embodiment includes, but is not limited to, a conductive paste containing silver particles, such as a conductive silver paste, and the first chip 1 and the second chip 2 are electrically connected with each other through the conductive silver paste.

It should be noted that, when the second end of the first conductive member 101 or the first end of the second conductive member 201 realizes the electrical connection between the first conductive member 101 and the second conductive member 201 by disposing the single conductive adhesive 5 one by one, the sealing layer 3 in the embodiment of the present invention still needs to be additionally disposed between the first chip 1 and the second chip 2.

In this embodiment, the second end of the first conductive member 101 and the first end of the second conductive member 201 have the same projection shape, where the projection shape is a projection shape of the first conductive member 101 on the first chip 1, or a projection shape of the second conductive member 201 on the second chip 2, and the projection shape may be a circle, an ellipse, or a polygon.

EXAMPLE III

Further, on the basis of the above embodiment, in this embodiment, as shown in fig. 2, the number of the second chips 2 is at least two, and the second chips 2 are all disposed on the same side of the first chip 1, or the second chips 2 are disposed on the front and back sides of the first chip 1.

It should be noted that, in this embodiment, as shown in fig. 2, when the number of the second chips 2 is two or more, the second chips 2 may be disposed on the same side of the first chip 1, and the transfer surfaces of all the second chips 2 are disposed opposite to the transfer surface of the first chip 1, and are connected between the bonding pads of the first chip 1 and the bonding pads of the second chips 2 through conductive members; the second chip 2 can set up the positive and negative both sides at first chip 1, second chip 2 can the equipartition in the positive and negative both sides of first chip 1 promptly, at this moment, the positive and negative both sides of first chip 1 all are equipped with the switching face, and all be equipped with first pad 105 on the switching face of first chip 1, first chip 1 is located between the second chip 2, and the switching face of first chip 1 sets up with the switching face of second chip 2 relatively, through connecing between first pad 105 of first chip 1 and the third pad 205 of second chip 2 mutually, realize the interconnection communication of first chip 1 and second chip 2.

Example four

Further, on the basis of the above embodiment, as shown in fig. 1, in this embodiment, the first chip 1 includes a first wafer 102, a first functional layer 103 is disposed on the first wafer 102, a first bonding pad 105 is disposed on the first functional layer 103 and can be used for interconnecting the first chip with other chips, and a second bonding pad 106 is further disposed on the first functional layer 103 and is interconnected with other external circuits; the number of the first pads 105 may be different according to the type, function, and the like of the first chip, and for example, there may be a plurality of first pads 105. Similarly, the number of the second pads 106 may be plural. The wafer in this application may be a silicon wafer or other semiconductor die.

In this embodiment, in order to facilitate interconnection of other external circuits with the first chip 1 via the second pad 106, the second pad 106 is located outside the first pad 105. Wherein, second pad 106 can be connected with other external circuit through the traditional routing mode among the prior art, also can pass through the utility model discloses well mode and other external circuit that electrically conductive piece are connected, in this embodiment, do not further limit to the mode that second pad 106 is connected with other external circuit.

In this embodiment, the second chip 2 includes a second wafer 202, a second functional layer 203 is disposed on the second wafer 202, a third bonding pad 205 is disposed on the second functional layer 203, and the conductive member is connected between the third bonding pad 205 and the first bonding pad 105.

In this embodiment, all structures capable of implementing the function of the first chip 1 are disposed in the first functional layer 103, wherein all structures capable of implementing the function of the first chip 1 include, but are not limited to, a metal layer and an active layer, the second functional layer 203 is similar to the first functional layer 103, and no further explanation is provided for the first functional layer 103 and the second functional layer 203 in this embodiment.

In this embodiment, the first chip 1 further includes a first insulating layer 104, the first insulating layer 104 is provided with a first windowing structure 107 communicated with the first bonding pad 105, the second chip 2 further includes a second insulating layer 204, the second insulating layer 204 is provided with a second windowing structure 206 communicated with the third bonding pad 205, and the conductive member is located between the first windowing structure 107 and the second windowing structure 206.

In this embodiment, the first windowing structure 107 is a windowing structure of the first insulating layer 104 that is processed on the first insulating layer 104 of the first chip 1 by a photolithography process or other processes on the surfaces of the first bonding pad 105 and the second bonding pad 106. Accordingly, the second window structure 206 is a window structure of the second insulating layer 204 processed on the surface of the third pad 205 by a photolithography process or other processes on the second insulating layer 204 of the second chip 2. The first windowing structure 107 and the second windowing structure 206 may be formed on the wafer on which the first chip 1 is located and the wafer on which the second chip 2 is located in advance, respectively, or the first windowing structure 107 and the second windowing structure 206 may be windowing structures formed during later chip interconnection, and in this embodiment, the forming time of the first windowing structure 107 is not further limited.

In the present embodiment, the insulating layer is used to realize surface insulation of the first chip 1 and the second chip 2, and has a certain protection effect on the first chip 1 and the second chip 2. In this embodiment, the insulating material used for the insulating layer may be an inorganic insulating material, such as polyimide or mica, or an organic insulating material, and in this embodiment, it is only required to ensure that the first insulating layer 104 and the second insulating layer 204 can respectively realize surface insulation of the first chip 1 and the second chip 2, and have a certain protection effect on the first chip 1 and the second chip 2, and the insulating material used for the first insulating layer 104 and the second insulating layer 204 is not further limited in this embodiment.

Note that the thickness of the first insulating layer 104 and the second insulating layer 204 is in the order of micrometers, for example, 5 um.

In this embodiment, a sealing layer 3 for sealing the conductive component is further disposed between the first chip 1 and the second chip 2, and the sealing layer 3 is used to protect the interconnection region of the first chip 1 and the second chip 2.

In this embodiment, the sealing material used for the sealing layer 3 may be water gel, epoxy glue, or any other colloid material capable of performing adhesion, corrosion prevention, and water vapor isolation.

EXAMPLE five

On the basis of the foregoing embodiments, the present embodiment provides a chip, where the chip includes the chip interconnection structure in any of the foregoing embodiments, and the chip including the chip interconnection structure in this embodiment can be used as a single chip to perform subsequent processes, for example, package and use by using a conventional packaging method, but the chip has functions of the first chip 1 and the second chip 2 at the same time.

EXAMPLE six

Fig. 3 is a schematic flow diagram of an interconnection method according to an embodiment of the present invention, fig. 4 is a schematic structural diagram of a first wafer according to an embodiment of the present invention, fig. 5 is a schematic structural diagram of a second wafer according to an embodiment of the present invention, fig. 6 is a schematic structural diagram of a first chip according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of a second chip according to an embodiment of the present invention.

As shown in fig. 3 to 7, based on the above embodiments, the present invention provides a chip interconnection method applied to the interconnection of a first chip 1 and at least one second chip 2 of the first chip 1, including:

step 101: forming a conductive member on at least one of the first wafer 102 and the second wafer 202, wherein the first wafer 102 is a wafer on which the first chip 1 is located, the second wafer 202 is a wafer on which the second chip 2 is located, and the positions of the conductive members correspond to the positions of the first bonding pad 105 and the third bonding pad 205;

step 102: obtaining a first chip 1 and a second chip 2 on the first wafer 102 and the second wafer 202, respectively;

step 103: the first chip 1 and the second chip 2 are butted, and the first bonding pad 105 of the first chip 1 and the third bonding pad 205 of the second chip 2 are connected by a conductive member.

In this embodiment, the conductive elements are formed on at least one of the first wafer 102 and the second wafer 202, that is, in this embodiment, the conductive elements may be formed on the first wafer 102 or the second wafer 202, at this time, the conductive elements are in an integral structure, or the conductive elements may be formed on the first wafer 102 and the second wafer 202, respectively, and at this time, the conductive elements are in a split structure.

In this embodiment, forming a conductive member on at least one of the first wafer 102 and the second wafer 202 includes:

conductive features are formed on first wafer 102 and second wafer 202, respectively.

In this embodiment, as shown in fig. 6 and 7, conductive members are formed on the first wafer 102 and the second wafer 202, respectively, and at this time, the conductive members include a first conductive member 101 and a second conductive member 201, a first end of the first conductive member 101 is connected to the first bonding pad 105 of the first wafer 102, and a second end of the second conductive member 201 is connected to the third bonding pad 205 of the second wafer 202.

In this embodiment, as shown in fig. 6 and 7, the first conductive member 101 includes a first conductive portion filled in the first window structure 107, and a second conductive portion located on the surface of the first insulating layer 104. In order to increase the contact area between the first conductive member 101 and the second conductive member 201, the projected area of the second conductive portion on the first chip 1 is larger than the projected area of the first conductive portion on the first chip 1. Accordingly, the second conductive member 202 also includes a third conductive portion filled in the second window structure 206 and a fourth conductive portion located on the surface of the second insulating layer 204. Similarly, in order to increase the contact area between the first conductive member 101 and the second conductive member 201, the projected area of the fourth conductive portion on the second chip 2 is larger than the projected area of the third conductive portion on the second chip 2.

It should be understood that, as shown in fig. 1 and 2, when the first chip 1 and the second chip 2 are interconnected by the first conductive member 101 and the second conductive member 201, the second conductive portion of the first conductive member 101 and the fourth conductive portion of the second conductive member 202 are in contact.

In this embodiment, the second end of the first conductive member 101 and the first end of the second conductive member 201 have the same projection shape, where the projection shape is a projection shape of the first conductive member 101 on the first chip 1, or a projection shape of the second conductive member 201 on the second chip 2, and the projection shape may be a circle, an ellipse, or a polygon.

In this embodiment, the forming manner of the conductive member includes one or more of the following: sputtering, evaporation plating, electroplating, chemical plating and conductive film pasting.

In this embodiment, specifically, when the conductive member is formed by sputtering, a Ti and Wu seed layer is firstly sputtered on the entire surface of the first insulating layer 104 or the second insulating layer 204, a photoresist is coated, a bump pit required by the conductive member is processed by a photolithography process, the pit is filled with electroplated gold, and the seed layer is etched after the photoresist is removed, so as to obtain the required structure. It should be noted that, it is a prior art to form a conductive device on an insulating layer of a wafer by sputtering, evaporation, electroplating, chemical plating, and attaching a conductive film, and a specific forming process thereof is not further described in this embodiment.

In this embodiment, obtaining the first chip 1 and the second chip 2 on the first wafer 102 and the second wafer 202 respectively includes:

a first chip 1 is cut on the first wafer 102, and a second chip 2 is cut on the second wafer 202, where the first chip 1 and the second chip 2 are both single bare chips.

In this embodiment, before dicing, the first wafer 102 and the second wafer 202 need to be ground and thinned to a specified thickness of the chip, and then the first wafer 102 and the second wafer 202 are diced into the first chip 1 and the second chip 2, so in this embodiment, the first chip 1 and the second chip 2 are both single bare chips.

In this embodiment, the connecting the first bonding pad 105 of the first chip 1 and the third bonding pad 205 of the second chip 2 by using the conductive member specifically includes:

the conductive member on the first chip 1 and/or the conductive member on the second chip 2 are connected by soldering or pressing, so that the conductive member connects the first pad 105 of the first chip 1 and the third pad 205 of the second chip 2.

In the present embodiment, the process adopted when the first chip 1 and the second chip 2 are interconnected is different according to the material selected by the conductive member, and the material of the conductive member and the connection manner corresponding to the different materials are described in the above embodiments, which will not be further described in the present embodiment.

In this embodiment, the first conductive member 101 and the second conductive member 201 may be electrically connected through the second chip 2 by disposing the conductive adhesive 5 between the first conductive member 101 and the second conductive member 201. Specifically, in this embodiment, the first conductive member 101 and the second conductive member 201 may be electrically connected by disposing the whole piece of conductive adhesive 5 between the first conductive member 101 and the second conductive member 201, or the first conductive member 101 and the second conductive member 201 may be electrically connected by disposing the single conductive adhesive 5 at the second end of the first conductive member 101 or the first end of the second conductive member 201 one by one.

In this embodiment, as shown in fig. 4 and fig. 5, before the step of forming the conductive member on at least one of the first wafer 102 and the second wafer 202, the method further includes:

determining whether both surfaces of the first wafer 102 and the second wafer 202 have an insulating layer;

if the surfaces of the first wafer 102 and the second wafer 202 have the insulating layer, a first windowing structure 107 communicated with the bonding pad of the first wafer 102 is formed on the insulating layer of the first wafer 102, and a second windowing structure 206 communicated with the bonding pad of the second wafer 202 is formed on the insulating layer of the second wafer 202;

if there is no insulating layer on the surfaces of the first wafer 102 and the second wafer 202, after forming insulating layers on the surfaces of the first wafer 102 and the second wafer 202, respectively, a first windowing structure 107 communicating with the bonding pad of the first wafer 102 is formed on the insulating layer of the first wafer 102, and a second windowing structure 206 communicating with the bonding pad of the second wafer 202 is formed on the insulating layer of the second wafer 202.

As shown in fig. 4 and 5, the first windowing structure 107 is formed on the first insulating layer 104 of the first chip 1, and the second windowing structure 206 is formed on the second insulating layer 204 of the second chip 2. The manner of forming the insulating layer on the surfaces of the first wafer 102 and the second wafer 202 includes processes such as spin coating, plasma spraying, printing, and film pasting, which are well known in the art and will not be further described in this embodiment.

In this embodiment, after the first bonding pad 105 of the first chip 1 and the third bonding pad 205 of the second chip 2 are connected by using the conductive member, the method further includes:

a sealing layer 3 for sealing the conductive components is formed between the first chip 1 and the second chip 2, and the interconnection regions of the first chip 1 and the second chip 2 are hermetically protected by the sealing layer 3.

It should be noted that the forming manner of the sealing layer 3 includes any colloid forming process such as dispensing, scribing, molding, etc., and the formation of the sealing layer by the above colloid forming process is the prior art, and will not be further described in this embodiment.

It should be noted that, when the first conductive member 101 and the second conductive member 201 are electrically connected by disposing the whole piece of conductive adhesive 5 between the first conductive member 101 and the second conductive member 201, the whole piece of conductive adhesive 5 between the first conductive member 101 and the second conductive member 201 forms the sealing layer 3 between the first chip 1 and the second chip 2 in this embodiment while the whole piece of conductive adhesive 5 between the first conductive member 101 and the second conductive member 201 is electrically connected.

The utility model provides a pair of chip interconnect structure and chip have realized two or more than two chip interconnection and can realize the high-speed communication's of interconnection chip purpose.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "comprises" and "comprising," and any variations thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral to one another; either directly or indirectly through intervening media, such as through internal communication or through an interaction between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims (18)

1. A chip interconnect structure, comprising:

a first chip including at least one first pad;

a second chip including at least one third pad corresponding to the first pad;

at least one conductive component disposed between the second chip and the first chip, each of the conductive components for connecting the first bonding pad and the third bonding pad, wherein each of the conductive components comprises at least one conductive member.

2. The chip interconnect structure of claim 1, wherein at least two of said conductive members that are connected in series are stacked.

3. The chip interconnect structure of claim 1, wherein each of the conductive components comprises a first conductive member and a second conductive member, a first end of the first conductive member is connected to the first pad, a second end of the first conductive member and a first end of the second conductive member are butted against each other, and a second end of the second conductive member is connected to the third pad.

4. The chip interconnect structure of claim 3, wherein the conductive member is a metal member.

5. The chip interconnection structure according to claim 3 or 4, wherein the first conductive member and the second conductive member are connected by soldering, or the first conductive member and the second conductive member are connected by a conductive adhesive.

6. The chip interconnection structure according to claim 3 or 4, wherein the conductive member is made of one or two of copper, silver, tin, gold, and aluminum.

7. The chip interconnect structure of claim 4, wherein the first and second conductive members are conductive metals capable of forming a eutectic.

8. The chip interconnection structure of claim 4, wherein when the first conductive member and the second conductive member are connected by soldering, a joint of the first conductive member and the second conductive member has a eutectic layer.

9. The chip interconnect structure of any of claims 1-3, wherein the conductive member and the first pad or the third pad are a unitary structure.

10. The chip interconnect structure of claim 3, wherein the second end of the first electrically conductive member has the same cross-sectional shape as the first end of the second electrically conductive member.

11. The chip interconnect structure of claim 10, wherein the conductive member is vertically disposed between the third pad and the first pad.

12. The chip interconnection structure according to claim 10 or 11, wherein the conductive member is a cylinder or a prism.

13. The chip interconnection structure of claim 1, wherein the number of the second chips is at least two, the second chips are disposed on the same side of the first chip, or the second chips are disposed on opposite sides of the first chip.

14. The chip interconnect structure of claim 1, wherein the first chip and the second chip are both single bare chips.

15. The chip interconnection structure according to claim 14, wherein the first chip comprises a first wafer, a first functional layer is disposed on the first wafer, the first functional layer is disposed with the first bonding pads, and the first functional layer is further disposed with second bonding pads interconnected with an external circuit;

the second chip comprises a second wafer, a second functional layer is arranged on the second wafer, the third bonding pad is arranged on the second functional layer, and the conductive piece is connected between the third bonding pad and the first bonding pad.

16. The chip interconnection structure according to claim 15, wherein the first chip further comprises a first insulating layer, the first insulating layer has a first window structure in communication with the first pad, the second chip further comprises a second insulating layer, the second insulating layer has a second window structure in communication with the third pad, and the conductive member is located between the first window structure and the second window structure.

17. The chip interconnect structure of claim 16, wherein a sealing layer for sealing the conductive component is further disposed between the first chip and the second chip.

18. A chip comprising a chip interconnect structure as claimed in any one of claims 1 to 17.

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