CN210490507U - Voltage equalization system - Google Patents
Voltage equalization system Download PDFInfo
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- CN210490507U CN210490507U CN201921703970.2U CN201921703970U CN210490507U CN 210490507 U CN210490507 U CN 210490507U CN 201921703970 U CN201921703970 U CN 201921703970U CN 210490507 U CN210490507 U CN 210490507U
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Abstract
The utility model provides a voltage equalization system for the voltage equalization control of group battery. The voltage balancing system comprises a simulation front end, a microcontroller, a communication isolation module and a balancing module, wherein the simulation front end is connected with the battery pack in parallel, the microcontroller is communicated with the simulation front end, the communication isolation module is connected between the simulation front end and the microcontroller, the input end of the balancing module is connected with the battery pack to input the total voltage of the battery pack, and the output end of the balancing module is respectively connected with the microcontroller and the communication isolation module to output the working voltage of the microcontroller and the communication isolation module. Compared with the prior art, the utility model discloses a voltage equalization system can avoid taking place the phenomenon of high, low side battery voltage unbalance.
Description
Technical Field
The utility model relates to a voltage equalization system belongs to the battery management field.
Background
Currently, in the battery pack industry, a plurality of battery cells are usually connected in series in order to realize high voltage, but the number of battery cells managed by an Analog Front End (AFE) is limited, so that 2 or even a plurality of AFEs are used for management respectively. In the market, some AFEs can be cascaded, some AFEs cannot be cascaded, and for the AFEs which cannot be cascaded, a communication isolation chip is needed to be used for realizing communication with a Microcontroller (MCU), while a general communication isolation chip needs to isolate two sides and supply power at the same time to normally work.
As shown in fig. 1, the power supplies on both sides of the communication isolation chip 1 are generally taken from 3.3V, 3.3V1 and 3.3V2 output by the internal power managers of the two AFEs, and the power supply of the MCU is also taken from 3.3V 1. The overall system appears to be simpler, but the high-side cell voltage and the low-side cell voltage are unbalanced after multiple charge-discharge cycles, the high-side cell voltage is significantly higher than the low-side cell voltage, and the high-side and low-side cell voltages are unbalanced due to the following reasons: the power consumption of the low-side cell is higher than the power consumption of the high-side cell. For example: 3.3V1 needs to supply power to MCU and B side of communication isolation chip 1, 3.3V2 only needs to supply power to A side of communication isolation chip 1, obviously, the power consumption of 3.3V1 is more than 3.3V2, and the power consumption of A side and B side of communication isolation chip 1 are different.
In view of the above, it is necessary to provide a voltage equalization system to solve the above problems.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a voltage balance system solves the problem that simulation front end AFE does not cascade and leads to the group battery voltage unbalance.
In order to achieve the above object, the utility model provides a voltage equalization system for the voltage equalization control of group battery, voltage equalization system includes the analog front end that sets up with the group battery is parallelly connected, carries out the microcontroller that communicates with the analog front end and connects the communication isolation module between analog front end and microcontroller, voltage equalization system still includes balanced module, balanced module's input links to each other with the group battery to the total voltage of input group battery, balanced module's output respectively with microcontroller with the communication isolation module links to each other, with output microcontroller and communication isolation module's operating voltage.
As a further improvement of the utility model, the group battery includes first group electric core and the second group electric core of mutual series connection, the simulation front end include with first group electric core parallel connection's low side simulation front end and with the second group electric core parallel connection's high side simulation front end, the communication isolation module connect in high side simulation front end with between the microcontroller.
As a further improvement of the present invention, the low side analog front end and the microcontroller communicate with each other through a first communication channel.
As a further improvement of the present invention, the communication isolation module communicates with the microcontroller through a second communication channel.
As a further improvement of the present invention, the high side analog front end and the low side analog front end are not cascaded.
As a further improvement of the utility model, the group battery still includes the third group's electric core with first group's electric core and second group's electric core series connection, with the corresponding simulation front end of third group's electric core with also be connected with between the microcontroller the module is kept apart in communication, the output of balanced module respectively with microcontroller and two the module is kept apart in communication links to each other.
As a further improvement of the present invention, the equalizing module is a voltage reducing chip.
As a further improvement of the utility model, the voltage reduction chip is a low dropout regulator.
As a further improvement of the utility model, the step-down chip is a step-down DC-DC converter.
As a further improvement of the present invention, the communication isolation module is an isolation chip, and the isolation chip is integrated with an isolated DC/DC converter.
The utility model has the advantages that: the utility model discloses a voltage equalization system is through setting up balanced module to link to each other the input of balanced module with the group battery, with the total voltage of input group battery, link to each other balanced module's output with microcontroller and communication respectively simultaneously, thereby can guarantee that microcontroller and communication keep apart the module and all get the electricity from total voltage, then can avoid taking place the phenomenon of high, low side battery voltage unbalance.
Drawings
Fig. 1 is a schematic diagram of a conventional battery pack voltage management system.
Fig. 2 is a schematic structural diagram of the voltage equalization system of the present invention.
Fig. 3 is a functional block diagram of the communication isolation module of fig. 2.
Fig. 4 is a schematic structural diagram of the voltage equalization system of fig. 2 according to the first embodiment.
Fig. 5 is a schematic structural diagram of a second embodiment of the voltage equalization system shown in fig. 2.
Fig. 6 is a schematic structural diagram of a third embodiment of the voltage equalization system shown in fig. 2.
Fig. 7 is a schematic diagram of the voltage equalization system shown in fig. 2 applied to three groups of analog front end AFEs.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
The utility model discloses a voltage equalization system for carry out equalizing control to the voltage of group battery in the battery package. For convenience and clarity of description, the battery pack including two sets of battery cells will be described in detail below, but the invention should not be limited thereto.
As shown in fig. 2 and 3, the voltage equalization system includes an Analog Front End (AFE), a Microcontroller (MCU)30, a communication isolation module 40, and an equalization module 50.
The battery pack 10 is defined to include a first group of battery cells 11 and a second group of battery cells 12, and the first group of battery cells 11 and the second group of battery cells 12 are connected in series with each other. The Analog Front End (AFE) is arranged in parallel with the battery pack 10 and comprises a low side analog front end 21 connected in parallel with the first set of cells 11 and a high side analog front end 22 connected in parallel with the second set of cells 12. The low-side analog front end 21 is configured to collect analog voltages of a first group of battery cells 11 and transmit the collected analog voltages to the microcontroller 30, and the high-side analog front end 22 is configured to collect analog voltages of a second group of battery cells 12 and transmit the collected analog voltages to the microcontroller 30.
Preferably, both the low-side analog front end 21 and the high-side analog front end 22 have an analog-to-digital converter (i.e., ADC module) integrated therein, and the low-side analog front end 21 communicates with the microcontroller 30 through the first communication channel 211, so that when the microcontroller 30 needs to collect the analog voltage of any one cell in the first set of cells 11, the first communication channel 211 can be used to transmit a command, and the low-side analog front end 21 can detect and extract the analog voltage value of the corresponding cell immediately after receiving such a command. Meanwhile, since the ADC module is integrated inside the low-side analog front end 21, after the low-side analog front end 21 detects the analog voltage value of the first group of battery cells 11, the analog voltage value can be directly converted into a digital value and sent to the microcontroller 30 through the first communication channel 211.
The high-side analog front end 22 and the low-side analog front end 21 are not cascaded, so a communication isolation module 40 is required to realize the communication between the high-side analog front end 22 and the microcontroller 30. Specifically, the communication isolation module 40 is connected between the high-side analog front end 22 and the microcontroller 30, and connects the communication interface of the high-side analog front end 22 and the communication interface of the microcontroller 30, so as to implement communication between the high-side analog front end 22 and the microcontroller 30. Preferably, the high-side analog front end 22, the communication isolation module 40 and the microcontroller 30 communicate with each other through the second communication channel 221, and the specific communication process may refer to the communication process between the low-side analog front end 21 and the microcontroller 30, which is not described herein.
In this embodiment, the communication isolation module 40 is an isolation chip, and an isolated DC/DC converter is integrated in the isolation chip, so that the isolation chip only needs one side to supply power, and does not need two sides to supply power.
An input terminal VIN of the equalizing module 50 is connected to the battery pack 10 to input a total voltage of the battery pack 10 (i.e., a sum of voltages of the first set of battery cells 11 and the second set of battery cells 12), and an output terminal VOUT of the equalizing module 50 is connected to the microcontroller 30 and the communication isolating module 40, respectively, to output an operating voltage (e.g., 3.3V) of the microcontroller 30 and the communication isolating module 40, so as to simultaneously supply power to the microcontroller 30 and the communication isolating module 40. The purpose of this design is: the microcontroller 30 and the communication isolation module 40 are both powered from the total voltage, and the working voltages of the microcontroller 30 and the communication isolation module 40 are the same, so that the phenomenon of unbalanced voltages of the high-side battery and the low-side battery can be avoided.
In this embodiment, the equalizing module 50 is a voltage-reducing chip, and is configured to directly perform a voltage-reducing step after the input terminal VIN of the equalizing module 50 receives the total voltage of the battery pack 10, so that the voltage output by the output terminal VOUT of the equalizing module 50 can safely start the microcontroller 30 and the communication isolating module 40, and at this time, the voltage output by the output terminal VOUT is the working voltage of the microcontroller 30 and the communication isolating module 40. Preferably, the buck chip may be a low dropout regulator (LDO) or a buck DC-DC converter.
Fig. 4 shows a first embodiment of the voltage equalization system according to the present invention. In this embodiment, step-down chip 50 is LDO, this moment, the utility model discloses a voltage equalization system has that stability is good, load response is fast, output ripple advantage such as little.
Fig. 5 shows a second embodiment of the voltage equalization system according to the present invention. In this embodiment, the voltage reduction chip 50 is a voltage reduction type DC-DC converter, and at this time, the utility model discloses a voltage equalization system has advantages such as efficient, input voltage range broad. Of course, the LDO also belongs to one of the DC-DC converters in a strict sense, but the current DC-DC converter is a multi-finger switching power supply.
Fig. 6 shows a third embodiment of the voltage equalization system according to the present invention. In the present embodiment, the low-side analog front end 21 ' and the high-side analog front end 22 ' have no integrated analog-to-digital converter (i.e., ADC module) inside, and at this time, the voltage equalization system of the present invention further includes a subtractor 60 for obtaining an analog voltage (i.e., actual voltage) of the second group of battery cells 12 outputted by the high-side analog front end 22 ' with respect to the ground.
For the first group of cells 11 and the low-side analog front end 21 ', the interface Uout1 of the low-side analog front end 21 ' is connected to the interface AD1 of the microcontroller 30, so that the analog voltage of the corresponding cell can be directly output to the microcontroller 30 after the low-side analog front end 21 ' detects the analog voltage.
For the second group of cells 12 and the high-side analog front end 22 ', the positive input terminal of the subtractor 60 is connected to the interface Uout2 of the high-side analog front end 22 ' to receive the voltage output by the high-side analog front end 22 '; a negative input terminal of the subtractor 60 is connected to the overall positive terminal of the first group of cells 11 to input the sum of the voltages of the first group of cells 11; the output OUT of the subtractor 60 is connected to the interface AD2 of the microcontroller 30, so as to transmit the analog voltage (i.e., the actual voltage) of the second group of battery cells 12, which is output by the subtractor 60, with respect to the ground to the microcontroller 30.
It should be noted that: with GND as a reference, the voltage value output by the low-side analog front end 21 'is the actual voltage value detected from the first group of battery cells 11, and the voltage value output by the high-side analog front end 22' is the voltage value detected from the second group of battery cells 12 superimposed on the voltage value detected from the first group of battery cells 11. Therefore, if the true detected voltage value of the second group of battery cells 12 is to be obtained, the sum of the voltages of the first group of battery cells 11 must be subtracted by the subtractor 60.
Besides, the first communication channel, the second communication channel, the equalizing module and the communication isolating module in fig. 6 are the same as the first communication channel 211, the second communication channel 221, the equalizing module 50 and the communication isolating module 40 in fig. 2 in structure, connection relationship therebetween and functions that can be realized, and are not described in detail here.
Fig. 7 is a schematic diagram illustrating the voltage equalization system shown in fig. 2 applied to three groups of analog front end AFEs. From this figure it can be seen that: the utility model discloses a voltage equalization system not only is applicable to the situation of two sets of analog front end AFE, also is applicable to the situation of three even more multiunit analog front end AFE of group equally, and no matter under which kind of situation, all only needs to set up an equalizing module 50, just can realize the equilibrium of high, low side battery voltage.
When the utility model discloses a voltage equalization system is applied to three analog front end AFE of group, first group battery cell 11, second group battery cell 12, the mutual series connection of third group battery cell 13, analog front end AFE1 and first group battery cell 11 parallel connection, analog front end AFE2 and second group battery cell 12 parallel connection, analog front end AFE3 and third group battery cell 13 parallel connection, microcontroller 30 can communicate with analog front end AFE1, analog front end AFE2, analog front end AFE3 simultaneously to usable analog front end AFE1 gathers the analog voltage of first group battery cell 11 and transmits to microcontroller 30, utilizes analog front end AFE2 to gather and transmit to microcontroller 30 the analog voltage of second group battery cell 12, utilizes analog front end AFE3 to gather and transmit to microcontroller 30 the analog voltage of third group AFE battery cell 13 simultaneously.
Meanwhile, the analog front end AFE1 communicates with the microcontroller 30 through the first communication channel 111, the communication isolation module 40 is connected between the analog front end AFE2 and the microcontroller 30, and the three communicate with each other through the second communication channel 121, and the communication isolation module 40' is also connected between the analog front end AFE3 and the microcontroller 30, and the three communicate with each other through the third communication channel 131.
It should be noted that: in the voltage equalizing system shown in fig. 7, only one equalizing module 50 is provided, and an input end VIN of the equalizing module 50 is connected to the battery pack 10 ' to input a total voltage of the battery pack 10 ' (i.e., a sum of voltages of the first group of battery cells 11, the second group of battery cells 12, and the third group of battery cells 13), and an output end VOUT of the equalizing module 50 is connected to the microcontroller 30, the communication isolating module 40, and the communication isolating module 40 ' respectively to output operating voltages (e.g., 3.3V) of the microcontroller 30, the communication isolating module 40, and the communication isolating module 40 ', so as to simultaneously supply power to the microcontroller 30, the communication isolating module 40, and the communication isolating module 40 '.
So set up: on one hand, the microcontroller 30, the communication isolation module 40 and the communication isolation module 40 'all take power from the total voltage, and the working voltages of the microcontroller 30, the communication isolation module 40 and the communication isolation module 40' are the same, so that the imbalance of the battery voltages at the high side and the low side is avoided; on the other hand, the effect can be realized by using one equalizing module 50, the structure is simple, and the cost can be reduced.
Analogize with this, when the utility model discloses a voltage equalization system is applied to four group's analog front end AFE, also can utilize a balanced module 50 to solve the unbalanced problem of high, low side battery voltage equally, only need this moment with balanced module 50 the output with correspond to analog front end AFE4 the communication isolation module link to each other can, here is no longer detailed description.
To sum up, the utility model discloses a voltage equalization system is through being provided with balanced module 50 to link to each other input VIN and group battery 10, 10 ' balanced module 50, with the total voltage of input group battery 10, 10 ', link to each other balanced module 50's output VOUT with microcontroller 30 and communication isolation module 40, 40 ' respectively simultaneously, thereby can guarantee that microcontroller 30 and communication isolation module 40, 40 ' all follow the total voltage and get the electricity, can avoid then taking place the phenomenon of high, low side battery voltage unbalance.
The above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present invention can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present invention.
Claims (10)
1. The utility model provides a voltage equalization system for the voltage equalization control of group battery, voltage equalization system includes the simulation front end that sets up with the group battery is parallelly connected, carries out the microcontroller that communicates with the simulation front end and connects the communication isolation module between simulation front end and microcontroller, its characterized in that: the voltage balancing system further comprises a balancing module, wherein the input end of the balancing module is connected with the battery pack so as to input the total voltage of the battery pack, and the output end of the balancing module is respectively connected with the microcontroller and the communication isolation module so as to output the working voltages of the microcontroller and the communication isolation module.
2. The voltage equalization system of claim 1, wherein: the battery pack comprises a first group of battery cells and a second group of battery cells which are connected in series, the analog front end comprises a low-side analog front end connected with the first group of battery cells in parallel and a high-side analog front end connected with the second group of battery cells in parallel, and the communication isolation module is connected between the high-side analog front end and the microcontroller.
3. The voltage equalization system of claim 2, wherein: the low-side analog front end and the microcontroller communicate with each other through a first communication channel.
4. The voltage equalization system of claim 2, wherein: the communication isolation module communicates with the microcontroller through a second communication channel.
5. The voltage equalization system of claim 2, wherein: the high-side analog front end is not cascaded with the low-side analog front end.
6. The voltage equalization system of claim 2, wherein: the battery pack further comprises a third group of battery cells connected with the first group of battery cells and the second group of battery cells in series, the communication isolation module is also connected between the analog front end corresponding to the third group of battery cells and the microcontroller, and the output end of the equalization module is respectively connected with the microcontroller and the two communication isolation modules.
7. The voltage equalization system of claim 1, wherein: the equalization module is a voltage reduction chip.
8. The voltage equalization system of claim 7, wherein: the voltage reduction chip is a low dropout regulator.
9. The voltage equalization system of claim 7, wherein: the voltage reduction chip is a voltage reduction type DC-DC converter.
10. The voltage equalization system of claim 1, wherein: the communication isolation module is an isolation chip, and an isolated DC/DC converter is integrated in the isolation chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921703970.2U CN210490507U (en) | 2019-10-12 | 2019-10-12 | Voltage equalization system |
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| CN201921703970.2U CN210490507U (en) | 2019-10-12 | 2019-10-12 | Voltage equalization system |
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| CN210490507U true CN210490507U (en) | 2020-05-08 |
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Address after: No.65-1 Xinggang Road, Zhonglou Economic Development Zone, Changzhou City, Jiangsu Province Patentee after: Gelibo (Jiangsu) Co., Ltd Address before: 213023 Jiangsu province Changzhou Xingang Tower Road Economic Development Zone No. 65 Patentee before: CHANGZHOU GLOBE Co.,Ltd. |