CN210489212U - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN210489212U CN210489212U CN201922119775.1U CN201922119775U CN210489212U CN 210489212 U CN210489212 U CN 210489212U CN 201922119775 U CN201922119775 U CN 201922119775U CN 210489212 U CN210489212 U CN 210489212U
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Abstract
The utility model provides a display panel and display device belongs to and shows technical field, and it can solve the more quantity of pixel control line among the current display panel, and the display panel's that causes hardware is with high costs, the big problem of the technology degree of difficulty. The utility model discloses display panel, include: the pixel structure comprises a plurality of sub-pixels arranged in an array, a plurality of first grid lines, a plurality of second grid lines, a plurality of data lines and a plurality of sensing lines; each row of sub-pixels is respectively connected with a first grid line and a second grid line; in any continuous three rows of sub-pixels, two adjacent rows of sub-pixels share one first grid line, and the other two adjacent rows of sub-pixels share one second grid line; each column of sub-pixels corresponds to two data lines, and the sub-pixels are connected with the two data lines in turn; all the column sub-pixels are divided into a plurality of first groups, each first group is two adjacent columns of sub-pixels, and two columns of sub-pixels of each first group share one sensing line.
Description
Technical Field
The utility model relates to a show technical field, specifically, relate to a display panel and display device.
Background
With the continuous development of display technology, the AMOLED (Active Matrix/organic light emitting diode) panel has gained wide attention due to its advantages of fast response speed, high contrast, wide viewing angle, self-luminescence, etc.
Currently, high resolution (e.g., 8K) AMOLED panels are relatively rare, for the main reasons: the more the sub-pixels are, the more the pixel control lines (e.g., the first gate line, the second gate line, the sensing lines, etc.) are required, for example, each row of sub-pixels needs to correspond to one first gate line and one second gate line, and each column of sub-pixels needs to correspond to one sensing line, etc., however, the arrangement space of the display panel is limited, and therefore, in order to achieve high resolution of the display panel, the sizes of the sub-pixels and the pixel control lines need to be compressed, thereby easily causing low yield of the display panel. Meanwhile, after a high-resolution panel is manufactured, a COF (Chip on film) is required
On Film) connects the driver chip with a plurality of pixel control lines in the display panel, and in order to input the signal provided by the driver chip to the pixel control lines, signal transmission lines required to be designed On the COF need to be increased, so that the hardware cost is increased, and the process difficulty is increased.
Therefore, reducing the number of pixel control lines in a high-resolution display panel is an urgent problem to be solved.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the quantity of pixel control line is more among the partial solution current display panel at least, and the display panel's that causes hardware is with high costs, the big problem of the technology degree of difficulty provides one kind and can reduce the pixel control line, practices thrift display panel and display device of hardware cost and reduction technology degree of difficulty.
Solve the utility model discloses technical scheme that technical problem adopted is a display panel, include: the pixel structure comprises a plurality of sub-pixels arranged in an array, a plurality of first grid lines, a plurality of second grid lines, a plurality of data lines and a plurality of sensing lines;
each row of the sub-pixels is respectively connected with one first grid line and one second grid line;
in any continuous three rows of the sub-pixels, two adjacent rows of the sub-pixels share one first grid line, and the other two adjacent rows of the sub-pixels share one second grid line;
each column of the sub-pixels corresponds to two data lines, and the sub-pixels are connected with the two data lines in turn;
all the columns of the sub-pixels are divided into a plurality of first groups, each first group is two adjacent columns of the sub-pixels, and two columns of the sub-pixels of each first group share one sensing line.
Optionally, the display device further includes a plurality of power lines, the sub-pixels in all columns are divided into a plurality of second groups, each of the second groups is adjacent to 4 columns of the sub-pixels, and each of the 4 columns of the sub-pixels in each second group shares one power line.
Optionally, the power line extends in a column direction, and two columns of sub-pixels sharing the power line are respectively arranged on two sides of the power line in the row direction.
Optionally, the first gate line and the second gate line extend along a row direction, the first gate line and the second gate line are arranged in a row direction, and one of the first gate line and the second gate line is arranged between any two adjacent rows of the sub-pixels.
Optionally, the sensing lines extend in a column direction, and each sensing line is located between two columns of the sub-pixels sharing the sensing line.
Optionally, the plurality of sub-pixels are divided into a first color sub-pixel, a second color sub-pixel, a third color sub-pixel and a fourth color sub-pixel according to different displayed colors.
Optionally, in any row, the sub-pixels with two colors are arranged in turn, and the sub-pixels displaying different colors are arranged in turn;
and any column is provided with the sub-pixels with two colors, and the sub-pixels displaying different colors are arranged in turn.
Optionally, each of the sub-pixels comprises: a first transistor, a driving transistor, a second transistor, and a light emitting unit;
the grid electrode of the first transistor is connected with the first grid line and used for introducing a data signal of a data line into the grid electrode of the driving transistor under the control of a first control signal of the first grid line;
the driving transistor is used for driving the light-emitting unit to emit light according to the data signal;
and the grid electrode of the second transistor is connected with the second grid line and used for sending a feedback signal to the sensing line or acquiring a compensation signal from the sensing line under the control of a second control signal of the second grid line.
Optionally, the light emitting unit is an organic light emitting diode.
Optionally, the number of the sub-pixels per row is smaller than the number of the sub-pixels per column.
Solve the technical problem the utility model discloses the technical scheme that technical problem adopted is a display device, including foretell display panel.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a display panel according to the present invention;
fig. 2 is a schematic structural diagram of another embodiment of a display panel according to the present invention;
fig. 3 is a schematic diagram of a pixel circuit according to still another embodiment of the present invention;
wherein the reference numbers indicate: 10. a pixel unit; 11. a sub-pixel; 11a, a first color sub-pixel; 11b, a second color sub-pixel; 11c, a third color sub-pixel; 11d of,
A fourth color sub-pixel; g1, a first gate line; g2, a second grid line; D. a data line; d1,
A first data line; d2, a second data line; s, a sensing line; E. a power line; s1, a first sensing line; s2, a second sensing line; C. a power line; 01. a first branch line; 02. a second branch line; DT, drive transistor; t1, a first transistor; t2, a second transistor; an OLED, a light emitting unit; c1, storage capacitor; VDD, a first power supply; VSS, a second power supply.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in the following description in order to provide a more thorough understanding of the invention.
However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or the same devices of other characteristics.
Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the embodiments of the invention do not denote any order, quantity, or importance, but rather the embodiments are used to distinguish one element from another.
The word "comprising" or "comprises", and the like, means that a element or item that precedes the word is identified by error or that the element or item listed after the word is identified by error, and that other elements or items are not excluded. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
"row", "column", "left", "right", and the like are used merely to indicate a relative positional relationship, and when the absolute position of the object being described is changed, the relative positional relationship may also be changed accordingly.
In general, in color display, the smallest unit of a displayed image is called a pixel. Accordingly, in the display panel, the portion for displaying each pixel in the image is a pixel unit, and each pixel unit includes a plurality of (e.g., 3 or 4) sub-pixels, and each sub-pixel can display a basic color. For example, each pixel unit includes 4 sub-pixels, respectively, a first color sub-pixel displaying red (R), a second sub-color sub-pixel displaying green (G), a third color sub-pixel displaying white (W), and a fourth color sub-pixel displaying blue (B).
In a conventional display panel, each sub-pixel includes a pixel circuit (e.g., a 3T1C pixel circuit), and the pixel circuit of each sub-pixel is connected to the first gate line, the second gate line, the data line, and the sensing line.
The first grid line transmits a first control signal (such as high level and low level) to the pixel circuit, so that a data signal (such as an image signal) transmitted by the data line is introduced into the pixel circuit, and the sub-pixel displays basic color; the second gate line transmits a second control signal (e.g., high level, low level) to the pixel circuit, so that the pixel circuit outputs a feedback signal (for indicating how the pixel circuit should be compensated) to the sensing line, or the sensing line transmits a compensation signal (for compensating the pixel circuit) to the pixel circuit, thereby realizing the display compensation of the pixel circuit.
Each row of sub-pixels is respectively connected with a first grid line and a second grid line, each column of sub-pixels is connected with a sensing line, each column of sub-pixels corresponds to at least one data line, the sub-pixels used for outputting the same color are connected with the same data line, and the sub-pixels used for outputting different colors are connected with different data lines.
Example 1:
as shown in fig. 1 to 3, the present embodiment provides a display panel including: a plurality of sub-pixels 11 arranged in an array, a plurality of first gate lines G1, a plurality of second gate lines G2, a plurality of data lines D, and a plurality of sensing lines S;
each row of sub-pixels 11 is connected to one first gate line G1 and one second gate line G2 respectively;
in any continuous three rows of sub-pixels 11, two adjacent rows of sub-pixels 11 share one first gate line G1, and the other two adjacent rows of sub-pixels 11 share one second gate line G2;
each column of sub-pixels 11 corresponds to two data lines D, wherein the sub-pixels 11 are connected with the two data lines D in turn;
all the column sub-pixels 11 are divided into a plurality of first groups, each first group is two adjacent columns of sub-pixels 11, and two columns of sub-pixels 11 of each first group share one sensing line S.
In this embodiment, in any three consecutive rows of sub-pixels 11, two adjacent rows of sub-pixels 11 share one first gate line G1, and another two adjacent rows of sub-pixels 11 share one second gate line G2, that is, any first gate line G1 and any second gate line G2 are shared by two rows of sub-pixels 11. As can be seen, compared to the conventional display panel, the number of the first gate lines G1 and the number of the second gate lines G2 in the display panel of the embodiment are both reduced by half. Similarly, two rows of sub-pixels 11 share one sensing line S, and the number of sensing lines S in the display panel of the embodiment is also reduced by half compared with the conventional display panel. The first gate line G1, the second gate line G2 and the sensing line S are halved, which is equivalent to increase the arrangement space of the display panel, so that the space occupied by the sub-pixel 11, the first gate line G1, the second gate line G2, the sensing line S and the like can be increased, the yield of the sub-pixel 11, the first gate line G1, the second gate line G2, the sensing line S and the like can be improved, and the yield of the display panel can be increased. For example, increasing the width of the first gate line G1, i.e., the gate line extending in the row direction, increases the size of the first gate line G1 in the column direction.
Meanwhile, in the display panel of the embodiment, each column of sub-pixels 11 is connected to two data lines D in turn, so that it is ensured that two sub-pixels 11 sharing the same first gate line G1 do not share the same data line D, and normal display of each sub-pixel 11 is ensured.
Further, when a COF is adopted to connect a driving chip, a circuit board and the like with the first gate line G1, the second gate line G2, the sensing line S and the like in the display panel, signal transmission lines which need to be designed on the driving chip and the COF are correspondingly reduced, so that the hardware cost of the circuit board and the COF is reduced, and when the COF is adopted for bonding, the difficulty of bonding is reduced, and the bonding yield is improved.
Optionally, as shown in fig. 1 and 2, the display panel of this embodiment further includes a plurality of power lines E, all the column sub-pixels 11 are divided into a plurality of second groups, each second group is an adjacent 4-column sub-pixel 11, and each second group shares one power line E with each 4-column sub-pixel 11.
Wherein the pixel circuit of the sub-pixel 11 is supplied with the driving voltage through the power supply line E, for example, which is connected to the first power supply terminal VDD or the second power supply terminal VSS (determined positive or negative according to the power supply line E) in the pixel circuit of 3T1C of fig. 3.
In the above scheme, the adjacent 4 columns of sub-pixels 11 share one power line E, and compared with the case that one power line E is connected to every 2 columns of sub-pixels 11 in the conventional display panel, the number of the power lines E of the display panel in the above scheme is reduced by half, thereby further saving the arrangement space of the display panel.
Alternatively, the power supply line E extends in the column direction, and two columns of sub-pixels 11 sharing the power supply line E are arranged on both sides of the power supply line E in the row direction, respectively.
The 4 columns of sub-pixels 11 sharing one power line E are symmetrically distributed in the row direction with the power line E as a symmetry axis, for example, as shown in fig. 1 and 2, the first column of sub-pixels 11, the second column of sub-pixels 11, the third column of sub-pixels 11, and the fourth column of sub-pixels 11 share one power line E. The first and second columns of sub-pixels 11 and 11 are arranged on the left side of the power supply line E, and the third and fourth columns of sub-pixels 11 and 11 are arranged on the right side of the power supply line E.
In the above scheme, the 4 columns of pixels sharing one power line E are arranged on both sides of the power line E, so that the power line E is conveniently connected to the plurality of sub-pixels 11 sharing the power line E.
Of course, it is more preferable that the plurality of power lines E in the display panel are arranged at equal intervals.
Furthermore, each power line E and the 4 columns of sub-pixels 11 sharing the power line E are connected by a plurality of first branch lines 01, all the sub-pixels 11 sharing the same power line E are divided into a plurality of first common line groups, each first common line group is two adjacent rows of sub-pixels 11, and two rows of sub-pixels 11 of each first common line group share one first branch line 01.
Wherein, a plurality of first branch lines 01 may extend along the row direction, and the first branch lines 01 are arranged between two rows of pixels sharing the first branch lines 01.
The sub-pixels 11 of the same pixel unit 10 may share the first branch line 01, and the sub-pixels 11 of different pixel units 10 may share the first branch line 01. For example, as shown in fig. 1 and 2, 4 sub-pixels 11 for displaying different colors constitute one pixel unit 10 (4 sub-pixels 11 in each dashed line frame in the drawing constitute one pixel unit 10). In fig. 1, of the 8 sub-pixels 11 sharing the first branch line 01, 4 sub-pixels 11 located on the left side of the power supply line E constitute 4 pixels of one pixel unit 10, and 4 sub-pixels 11 located on the right side of the power supply line E constitute one pixel unit 10. In fig. 2, of the 8 sub-pixels 11 sharing the first branch line 01, 4 sub-pixels 11 located on the left side of the power supply line E belong to 2 pixel units 10, and similarly, 4 sub-pixels 11 located on the right side of the power supply line E belong to 2 pixel units 10.
Alternatively, the first gate line G1 and the second gate line G2 both extend in the row direction, the first gate line G1 and the second gate line G2 are arranged in a row direction, and one of the first gate line G1 and the second gate line G2 is arranged between any two adjacent rows of sub-pixels 11.
The number of rows of the sub-pixels 11 in the display panel is N, so that the display panel has N-1 row spaces (spaces between two adjacent rows of the sub-pixels 11), and the sum of the numbers of the first gate lines G1 and the second gate lines G2 is N, so that one first gate line G1 or one second gate line G2 is not arranged between two adjacent rows of the sub-pixels 11.
In the above scheme, the first gate line G1 and the second gate line G2 are alternately arranged to facilitate connection of the first gate line G1 and the second gate line G2 to each row of sub-pixels 11. Meanwhile, the first gate line G1 and the second gate line G2 are regularly arranged, so that when a COF is adopted to connect the driving chip with the first gate line G1 and the second gate line G2, the hardware cost and the bonding difficulty can be reduced, and the bonding yield can be improved.
More preferably, the pitches between any adjacent first gate lines G1 and second gate lines G2 are equal.
Of course, as shown in fig. 1 and 2, two columns of data lines D corresponding to each column of sub-pixels 11 may extend in the column direction, and each column of sub-pixels 11 is arranged between two corresponding data lines D.
In this way, the connection of the data line D and the sub-pixel 11 is facilitated.
Optionally, the sensing lines S extend in a column direction, and each sensing line S is located between two columns of sub-pixels 11 sharing the sensing line S.
In the above scheme, the sensing line S is located between two columns of sub-pixels 11, so that the two columns of sub-pixels 11 sharing the sensing line S are connected to the sensing line S.
More preferably, the plurality of sensing lines S in the display panel are arranged at equal intervals. Specifically, as shown in fig. 1 and 2, 2 columns of sub-pixels 11 are disposed between the adjacent first sensing lines S1 and second sensing lines S2.
Optionally, each sensing line S is connected to 2 columns of sub-pixels 11 sharing the sensing line S through a plurality of second branch lines 02, all the sub-pixels 11 sharing the same sensing line S are divided into a plurality of second common line groups, each second common line group is two adjacent rows of sub-pixels 11, and two rows of sub-pixels 11 sharing the same second common line group share the second branch line 02.
Wherein, a plurality of first branch lines 01 may extend along the row direction, and the first branch lines 01 are arranged between two rows of pixels sharing the first branch lines 01.
Alternatively, the plurality of sub-pixels 11 are divided into a first color sub-pixel 11a, a second color sub-pixel 11b, a third color sub-pixel 11c, and a fourth color sub-pixel 11d according to the displayed colors.
In the above-described scheme, in order to ensure that the pixel unit 10 of the display panel can display images of various colors, the 4 sub-pixels 11 constituting one pixel can display different colors. The 4 colors may be red (R), green (G), blue (B), and white (W).
Of course, the sub-pixels 11 can be further divided into a first color sub-pixel 11a, a second color sub-pixel 11b, and a third color sub-pixel 11c according to the displayed colors, i.e. 3 colors, for example: red, green, blue (three primary colors). However, in addition to the 3 sub-pixels 11 capable of displaying three primary colors, the sub-pixel 11 capable of displaying white is added to each pixel unit 10, so that the brightness of the display panel can be improved, and the contrast of the display panel can be improved.
Alternatively, in any row, the sub-pixels 11 with two colors are arranged, and the sub-pixels 11 displaying different colors are arranged in turn;
in any column, there are two colors of sub-pixels 11, and the sub-pixels 11 displaying different colors are arranged alternately.
In the above scheme, in any column, the two adjacent sub-pixels 11 display different colors, and one sub-pixel 11 displaying another color is located between the two sub-pixels 11 displaying the same color.
As shown in fig. 1 and 2, the first column has a plurality of first color sub-pixels 11a displaying red (R) and a plurality of second color sub-pixels 11b displaying green (G), and the first color sub-pixels 11a and the second color sub-pixels 11b are alternately arranged; a second column having a plurality of third color sub-pixels 11c displaying white (W) and a plurality of fourth color sub-pixels 11d displaying blue (B), the third color sub-pixels 11c and the fourth color sub-pixels 11d being alternately arranged; the third row is the same as the first row, and the fourth row is the same as the second row, which are not described herein.
In general, when the display panel displays an image, the display panel scans line by line, that is, a first control signal is sequentially input to each row of the sub-pixels 11 through each first gate line G1, and a data signal (e.g., an image signal) is input to each row of the sub-pixels 11 through the data line D at the same time, so that the sub-pixels 11 in the row display a color (image).
Meanwhile, the display panel may also scan line by line when performing compensation, that is, the second control signal is input to each row of sub-pixels 11 through each second gate line G2 in sequence, and the sensing line S transmits a feedback signal or a compensation signal to compensate the corresponding two rows of sub-pixels 11.
In the arrangement of the sub-pixels 11 in the above scheme, the driving timing when the display panel displays different colors is relatively simple.
Furthermore, as shown in fig. 1 and 2, since two data lines D, namely, the first data line D1 and the second data line D2, correspond to each column of sub-pixels 11, and each column of sub-pixels 11 is connected to the first data line D1 and the second data line D2 in turn, the sub-pixels 11 displaying the same color in each column are connected to the same data line D, so that the sub-pixels 11 displaying the same color can be ensured to have the same brightness when receiving the same gray scale voltage as much as possible.
Optionally, each sub-pixel 11 comprises: a first transistor T1, a driving transistor DT, a second transistor T2, a light emitting unit OLED;
a gate electrode of the first transistor T1 is connected to the first gate line G1 for introducing a data signal of the data line D to the gate electrode of the driving transistor DT under the control of a first control signal of the first gate line G1;
a driving transistor DT for driving the light emitting unit OLED to emit light according to a data signal;
a gate of the second transistor T2 is connected to the second gate line G2 for transmitting a feedback signal to the sensing line S or acquiring a compensation signal from the sensing line S under the control of the second control signal of the second gate line G2.
In the above scheme, the pixel circuit of the sub-pixel 11 includes the compensation circuit, so that the threshold voltage compensation of the driving transistor DT can be realized, and the display effect is better.
Further preferably, the light emitting unit OLED is an Organic Light Emitting Diode (OLED).
Specifically, as shown in fig. 3, an alternative circuit structure of the pixel circuit of the sub-pixel 11 includes: a driving transistor DT, a first transistor T1, a second transistor T2, a storage capacitor C1, and a light emitting unit OLED. The drain electrode of the driving transistor DT is connected with a first power supply end VDD which is connected with a power line E; a gate electrode of the first transistor T1 is connected to the first gate line G1, a first electrode of the first transistor T1 is connected to the data line D, and a second electrode of the first transistor T1 is connected to the gate electrode of the driving transistor DT and one end of the storage capacitor C1, respectively; a gate electrode of the second transistor T2 is connected to the second gate line G2, a first electrode of the second transistor T2 is connected to the sensing line S, and a second electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT, the other end of the storage capacitor C1, and one end of the light emitting cell OLED, respectively; the other end of the light emitting unit OLED is connected to a second power source terminal VSS.
When displaying an image, the driving chip outputs high level signals to the first gate line G1 and the second gate line G2, respectively, at this time, the first transistor T1 and the second transistor T2 are both turned on, and at the same time, the driving chip outputs a data voltage to the data line D, and since the first transistor T1 is turned on, the data voltage on the data line D is written into the gate of the driving transistor DT through the first transistor T1, so as to control the current flowing through the driving transistor DT, that is, the current flowing through the light emitting unit OLED, so that the light emitting unit OLED emits light at a desired brightness; meanwhile, the point a is charged based on the sensing action of the storage capacitor C1, and after a certain period of charging, the driving unit obtains a charging voltage (feedback signal) through the second transistor T2 and the sensing line S, then determines a threshold voltage of the driving transistor DT according to the charging voltage, and then performs compensation (i.e., provides a compensation signal) through the sensing line S and the second transistor T2.
Optionally, the number of sub-pixels 11 per row is smaller than the number of sub-pixels 11 per column.
In the above scheme, the number of rows in the display panel is greater than the number of columns, and the first gate line G1 and the second gate line G2 are reduced more than the number of columns in the display panel.
Specifically, for example, the resolution of an 8K display panel is 7680 × 4320, i.e., the display panel includes 7680 × 4320 pixel cells 10. In the arrangement of fig. 1 and 2, the number of the first gate lines G1 and the second gate lines G2 is 7680X2 to 15360, and the number of the sensing lines S is 4320. However, in the conventional display panel, the total number of the first gate lines G1 and the second gate lines G2 is 7680X 4 — 30720, and it can be seen that the total number of the first gate lines G1 and the second gate lines G2 is greatly reduced, and the number of the sensing lines S is also greatly reduced.
Example 2:
the embodiment provides a display device, which comprises the display panel.
The display device further comprises a driving chip, and the driving chip is respectively connected with the first grid line, the second grid line, the data line, the sensing line and the power line in the display panel.
Specifically, the driving chip is fixed on the circuit board, and then the first portion of the COF is bonded to the first gate line, the second gate line, the data line, the sensing line and the power line in the display panel, and the second portion of the COF is bonded to the driving chip.
For specific description of the display panel, reference may be made to the description of embodiment 1, which is not repeated in this embodiment.
In this embodiment, the first gate line and the second gate line are shared by a plurality of rows of sub-pixels, and the sensing line and the power line are shared by a plurality of columns of sub-pixels, so that the first gate line, the second gate line, the sensing line and the power line in the display panel are greatly reduced, the arrangement space of the display panel is saved, the sizes of the sub-pixels, the first gate line, the second gate line, the sensing line, the power line and the like can be increased, and the yield of the display device is improved.
Furthermore, the number of the first grid line, the second grid line, the sensing line and the power line is reduced, when the COF is adopted to connect the driving chip with the first grid line, the second grid line, the data line, the sensing line and the power line in the display panel, the hardware cost and the bonding difficulty can be reduced, and the bonding yield is improved.
In practical applications, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator and the like.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (11)
1. A display panel, comprising: the pixel structure comprises a plurality of sub-pixels arranged in an array, a plurality of first grid lines, a plurality of second grid lines, a plurality of data lines and a plurality of sensing lines; it is characterized in that the preparation method is characterized in that,
each row of the sub-pixels is respectively connected with one first grid line and one second grid line;
in any continuous three rows of the sub-pixels, two adjacent rows of the sub-pixels share one first grid line, and the other two adjacent rows of the sub-pixels share one second grid line;
each column of the sub-pixels corresponds to two data lines, and the sub-pixels are connected with the two data lines in turn;
all the columns of the sub-pixels are divided into a plurality of first groups, each first group is two adjacent columns of the sub-pixels, and two columns of the sub-pixels of each first group share one sensing line.
2. The display panel according to claim 1, further comprising a plurality of power lines, wherein all columns of the sub-pixels are divided into a plurality of second groups, each of the second groups is 4 adjacent columns of the sub-pixels, and each of the 4 columns of the sub-pixels of the second groups shares one of the power lines.
3. The display panel according to claim 2, wherein the power supply line extends in a column direction, and two columns of sub-pixels sharing the power supply line are arranged on both sides of the power supply line in a row direction, respectively.
4. The display panel according to claim 1, wherein the first gate line and the second gate line each extend in a row direction, the first gate line and the second gate line are arranged in a column direction in a staggered manner, and one of the first gate line and the second gate line is arranged between any two adjacent rows of the subpixels.
5. The display panel of claim 1, wherein the sensing lines extend in a column direction, and each sensing line is located between two columns of the sub-pixels sharing the sensing line.
6. The display panel according to claim 1, wherein the plurality of sub-pixels are divided into a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a fourth color sub-pixel according to a display color.
7. The display panel according to claim 6,
any row is provided with the sub-pixels with two colors, and the sub-pixels displaying different colors are arranged in turn;
and any column is provided with the sub-pixels with two colors, and the sub-pixels displaying different colors are arranged in turn.
8. The display panel of claim 1, wherein each of the sub-pixels comprises: a first transistor, a driving transistor, a second transistor, and a light emitting unit;
the grid electrode of the first transistor is connected with the first grid line and used for introducing a data signal of a data line into the grid electrode of the driving transistor under the control of a first control signal of the first grid line;
the driving transistor is used for driving the light-emitting unit to emit light according to the data signal;
and the grid electrode of the second transistor is connected with the second grid line and used for sending a feedback signal to the sensing line or acquiring a compensation signal from the sensing line under the control of a second control signal of the second grid line.
9. The display panel according to claim 8, wherein the light-emitting unit is an organic light-emitting diode.
10. The display panel of claim 1, wherein the number of sub-pixels per row is less than the number of sub-pixels per column.
11. A display device comprising the display panel according to any one of claims 1 to 10.
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| CN201922119775.1U CN210489212U (en) | 2019-11-29 | 2019-11-29 | Display panel and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653591A (en) * | 2020-06-09 | 2020-09-11 | 合肥京东方卓印科技有限公司 | Display substrate and display device |
| CN113053976A (en) * | 2021-03-12 | 2021-06-29 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2023206167A1 (en) * | 2022-04-27 | 2023-11-02 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
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2019
- 2019-11-29 CN CN201922119775.1U patent/CN210489212U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653591A (en) * | 2020-06-09 | 2020-09-11 | 合肥京东方卓印科技有限公司 | Display substrate and display device |
| WO2021249105A1 (en) * | 2020-06-09 | 2021-12-16 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111653591B (en) * | 2020-06-09 | 2023-12-19 | 合肥京东方卓印科技有限公司 | Display substrate and display device |
| CN113053976A (en) * | 2021-03-12 | 2021-06-29 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2023206167A1 (en) * | 2022-04-27 | 2023-11-02 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
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