LED display screen line scanning driving circuit and chip integrating blanking adjustable function
Technical Field
The utility model relates to an integrated circuit technical field, concretely relates to LED display screen line scanning drive circuit and chip of integrated blanking adjustable function.
Background
In general, LED display screen systems can be classified into Common anode and Common Group types. The common anode system is characterized in that the anodes of RGB LEDs are connected together, the anodes of the LEDs of each row of scanning lines are connected together, power is supplied to the row of scanning lines in sequence during row scanning, and then the cathodes of the LEDs are respectively driven by constant currents for gray control. Since the common anode system needs RGB to supply power together, and the forward voltage drop of the R LED is smaller than the G LED and the bler, a large power consumption is wasted by the R LED driving. The power loss can cause the chip to generate heat seriously on the driving chip, and the temperature of the LED module is increased. Therefore, the common anode system has the disadvantages of high power consumption and high temperature of the LED module.
The Common Group type system is that the cathodes of RGB LEDs are connected together, the cathodes of the LEDs of each row of scanning lines are connected together, when the row scanning line works, the row scanning lines are sequentially pulled to the ground, and then the anodes of the LEDs are respectively driven by constant currents for gray control. Because the power supplies of the R LED, the G LED and the B LED of the Common Group type system can be separated, the power supply voltage of the R LED can be reduced, so that the power consumption of the R LED drive is reduced, the power consumption is saved, and the working temperature of the LED module is also reduced. The prior art provides a line scan driving circuit for a common group type system with poor blanking performance.
SUMMERY OF THE UTILITY MODEL
Therefore, the utility model aims at providing a LED display screen line scanning drive circuit and chip of adjustable function are blanked in integration adopts unique blanking technique, has blanking voltage adjustable function, can realize better blanking performance.
In a first aspect, an LED display screen line scan driving circuit integrated with blanking adjustable function comprises a status register, a shift register, a reference voltage generating module and a plurality of output driving modules;
one input end of the state register is used as a setting end of the driving circuit and is connected with an external setting signal; the other input end of the state register and one input end of the shift register are used as clock ends of the driving circuit and are connected with an external clock signal; the other input end of the shift register is used as the data end of the drive circuit and is connected with an external input signal;
the output end of the state register is connected with the input end of the reference voltage generating module, the output ends of the reference voltage generating module are all connected to one input end of the output driving module, a plurality of first output ends of the shift register are respectively connected to the other input end of the output driving module, the output end of the output driving module serves as the driving end of the driving circuit, and the second output end of the shift register serves as the output end of the driving circuit.
Preferably, the output driving module comprises a field effect transistor N1, a field effect transistor P1, an amplifier U1, an amplifier U2, a NAND gate U3, a NOT gate U4, a switch S1 and an overcurrent protection module;
the first output end of the shift register is connected with one input end of the NAND gate U3, the output end of the overcurrent protection module is connected with the other input end of the NAND gate U3, the output end of the NAND gate U3 is connected with the input end of the NOT gate U4, the output end of the NOT gate U4 is connected with the grid of the field effect transistor N1, the source of the field effect transistor N1 is grounded, the drain series resistor R1 of the field effect transistor N1 is connected with the drain of the field effect transistor P1, and the source of the field effect transistor P1 is connected with high level;
the output end of the reference voltage generation module is respectively connected with one input end of an amplifier U1 and an input end of an amplifier U2, the middle nodes of a resistor R1 and a field-effect tube N1 are respectively connected with the other input ends of an amplifier U1 and an amplifier U2, the output end of an amplifier U2 is connected with the grid electrode of a field-effect tube P1, the output end of the amplifier U1 is connected with the grid electrode of the field-effect tube P1 through a switch S1, the middle nodes of a resistor R1 and a field-effect tube N1 are connected with the input end of the over-current protection module, and the middle nodes of a resistor R1 and a field-effect tube N1.
Preferably, the fet P1 is a PMOS transistor, and the fet N1 is an NMOS transistor.
In a second aspect, an LED display screen line scanning driving chip integrated with blanking adjustable function,
the circuit comprises a state register, a shift register, a reference voltage generation module and a plurality of output driving modules;
one input end of the state register is used as a setting end of the driving chip and is connected with an external setting signal; the other input end of the state register and one input end of the shift register are used as clock ends of the driving chip and are connected with an external clock signal; the other input end of the shift register is used as the data end of the driving chip and is connected with an external input signal;
the output end of the state register is connected with the input end of the reference voltage generating module, the output ends of the reference voltage generating module are all connected to one input end of the output driving module, a plurality of first output ends of the shift register are respectively connected to the other input end of the output driving module, the output end of the output driving module serves as the driving end of the driving chip, and the second output end of the shift register serves as the output end of the driving chip.
Preferably, the driving end of the driving chip is connected with an external row scanning line switch.
Preferably, the output driving module comprises a field effect transistor N1, a field effect transistor P1, an amplifier U1, an amplifier U2, a NAND gate U3, a NOT gate U4, a switch S1 and an overcurrent protection module;
the first output end of the shift register is connected with one input end of the NAND gate U3, the output end of the overcurrent protection module is connected with the other input end of the NAND gate U3, the output end of the NAND gate U3 is connected with the input end of the NOT gate U4, the output end of the NOT gate U4 is connected with the grid of the field effect transistor N1, the source of the field effect transistor N1 is grounded, the drain series resistor R1 of the field effect transistor N1 is connected with the drain of the field effect transistor P1, and the source of the field effect transistor P1 is connected with high level;
the output end of the reference voltage generation module is respectively connected with one input end of an amplifier U1 and an input end of an amplifier U2, the middle nodes of a resistor R1 and a field-effect tube N1 are respectively connected with the other input ends of an amplifier U1 and an amplifier U2, the output end of an amplifier U2 is connected with the grid electrode of a field-effect tube P1, the output end of the amplifier U1 is connected with the grid electrode of the field-effect tube P1 through a switch S1, the middle nodes of a resistor R1 and a field-effect tube N1 are connected with the input end of the over-current protection module, and the middle nodes of a resistor R1 and a field-effect tube N1.
Preferably, the fet P1 is a PMOS transistor, and the fet N1 is an NMOS transistor.
The utility model provides a but LED display screen line scanning drive circuit and chip of integrated blanking adjustable function adopts unique blanking technique, has blanking voltage adjustable function, can eliminate the last ghost of LED display screen, can adjust blanking effect according to external signal, realizes better blanking performance, has integrateed the overcurrent protection function simultaneously, and reinforcing chip reliability in utilization security.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below. In the drawings, elements or portions are not necessarily drawn to scale.
Fig. 1 is a block diagram of a driving circuit according to a first embodiment.
Fig. 2 is a circuit diagram of the output driving module in fig. 1.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.
Example (b):
a line scanning driving circuit of an LED display screen integrated with a blanking adjustable function is disclosed, referring to fig. 1, and comprises a state register, a shift register, a reference voltage generating module and a plurality of output driving modules;
one input end of the state register is used as a setting end SET of the driving circuit and is connected with an external setting signal; the other input end of the state register and one input end of the shift register are used as a clock end CLK of the driving circuit and are connected with an external clock signal; the other input end of the shift register is used as a data end SDI of the drive circuit and is connected with an external input signal;
the output end of the state register is connected with the input end of the reference voltage generating module, the output ends of the reference voltage generating module are all connected to one input end of the output driving module, a plurality of first output ends of the shift register are respectively connected to the other input end of the output driving module, the output end of the output driving module is used as a driving end OUT of the driving circuit, and the second output end of the shift register is used as an output end SDO of the driving circuit.
Specifically, the driving circuit in fig. 1 is provided with 8 output driving modules, and the shift register includes 8 registers. The reference voltage generating module is used for outputting a reference voltage, and the driving circuit is particularly suitable for Common Group type systems. The external set signal is used to configure the status register. The external input signal is used for controlling the display of the LED display screen in the Common Group type system. The working principle of the driving circuit is that high-level signals of the SDI are sent to the shift register through CLK signals, when one CLK signal is sent, the value of the shift register shifts once, the value of the shift register is simultaneously sent to the output driving module, and the output driving module is responsible for driving the switching of an external row scanning line switch. When the driving circuits are connected, the output end SDO of the previous driving circuit can be connected with the data end SDI of the next driving circuit, so as to realize the line scanning serial control.
The drive circuit adopts a unique blanking technology, has a blanking voltage adjustable function, can eliminate the upper ghost of the LED display screen, can adjust the blanking effect according to an external signal, realizes better blanking performance, integrates an overcurrent protection function, and enhances the use reliability and safety of a chip.
Referring to fig. 2, the output driving module includes a field effect transistor N1, a field effect transistor P1, an amplifier U1, an amplifier U2, a nand gate U3, a not gate U4, a switch S1, and an overcurrent protection module;
the first output end of the shift register is connected with one input end of the NAND gate U3, the output end of the overcurrent protection module is connected with the other input end of the NAND gate U3, the output end of the NAND gate U3 is connected with the input end of the NOT gate U4, the output end of the NOT gate U4 is connected with the grid of the field effect transistor N1, the source of the field effect transistor N1 is grounded, the drain series resistor R1 of the field effect transistor N1 is connected with the drain of the field effect transistor P1, and the source of the field effect transistor P1 is connected with high level;
the output end of the reference voltage generation module is respectively connected with one input end of an amplifier U1 and an input end of an amplifier U2, the middle nodes of a resistor R1 and a field-effect tube N1 are respectively connected with the other input ends of an amplifier U1 and an amplifier U2, the output end of an amplifier U2 is connected with the grid electrode of a field-effect tube P1, the output end of the amplifier U1 is connected with the grid electrode of the field-effect tube P1 through a switch S1, the middle nodes of a resistor R1 and a field-effect tube N1 are connected with the input end of the over-current protection module, and the middle nodes of a resistor R1 and a field-effect tube N1.
Preferably, the fet P1 is a PMOS transistor, and the fet N1 is an NMOS transistor.
Specifically, N1 is a power tube for line scan output, and is responsible for driving the cathode of the LED in the LED system. P1 is a blanking function control transistor, and is responsible for turning on when the row scan is turned off, pulling up the output terminal OUT, and discharging the excess charges on the row line, thereby implementing the blanking function. R1 is a current limiting resistor. U1, U2 and S1 are responsible for controlling P1. The U1 controls the closing of P1 through switch S1, the output of U2 is connected to the gate of P1, and P1 is controlled to be opened. P1 is connected to the OUT output through a current limiting resistor R1. The On/Off signal controls N1 through U3 and U4, the overcurrent protection module is connected to the OUT output end, the output of the overcurrent protection module is connected to U3, and the N1 power tube is closed through U3 and U4 after overcurrent protection occurs.
When the On/Off signal of the first output end of the shift register is in a low level, the N1 is closed, the overcurrent protection module is closed, and when the On/Off signal is in a high level, the N1 is opened through the U3 and the U4, the overcurrent protection module starts to work, and the voltage of OUT is detected in real time. When the OUT output is normal, the over-current protection module always outputs a high-level signal, and N1 is completely controlled by the On/Off signal. During the opening process of the N1, when a large current flows into the OUT output, which will cause the OUT output voltage to be too high, the overcurrent protection module detects that the OUT output voltage exceeds a set threshold value, and then the output low level turns off the N1 power tube through the U3 and the U4. If the On/Off signal is high and is always effective in the overcurrent protection process, the overcurrent protection module outputs high level again to open the N1 power tube until the On/Off signal becomes low and close the N1 power tube.
After the On/Off signal goes low, N1 is turned Off, and after a short delay, U1 and U2 are turned On, controlling P1 to turn On and pulling up the OUT output. Then, when the U1 detects that the OUT level reaches the set reference voltage, S1 closes, and the P1 tube is closed. Thereby turning off the blanking action.
Example two:
an LED display screen line scanning driving chip integrated with blanking adjustable function,
the circuit comprises a state register, a shift register, a reference voltage generation module and a plurality of output driving modules;
one input end of the state register is used as a setting end of the driving chip and is connected with an external setting signal; the other input end of the state register and one input end of the shift register are used as clock ends of the driving chip and are connected with an external clock signal; the other input end of the shift register is used as the data end of the driving chip and is connected with an external input signal;
the output end of the state register is connected with the input end of the reference voltage generating module, the output ends of the reference voltage generating module are all connected to one input end of the output driving module, a plurality of first output ends of the shift register are respectively connected to the other input end of the output driving module, the output end of the output driving module serves as the driving end of the driving chip, and the second output end of the shift register serves as the output end of the driving chip.
Preferably, the driving end of the driving chip is connected with an external row scanning line switch.
Preferably, the output driving module comprises a field effect transistor N1, a field effect transistor P1, an amplifier U1, an amplifier U2, a NAND gate U3, a NOT gate U4, a switch S1 and an overcurrent protection module;
the first output end of the shift register is connected with one input end of the NAND gate U3, the output end of the overcurrent protection module is connected with the other input end of the NAND gate U3, the output end of the NAND gate U3 is connected with the input end of the NOT gate U4, the output end of the NOT gate U4 is connected with the grid of the field effect transistor N1, the source of the field effect transistor N1 is grounded, the drain series resistor R1 of the field effect transistor N1 is connected with the drain of the field effect transistor P1, and the source of the field effect transistor P1 is connected with high level;
the output end of the reference voltage generation module is respectively connected with one input end of an amplifier U1 and an input end of an amplifier U2, the middle nodes of a resistor R1 and a field-effect tube N1 are respectively connected with the other input ends of an amplifier U1 and an amplifier U2, the output end of an amplifier U2 is connected with the grid electrode of a field-effect tube P1, the output end of the amplifier U1 is connected with the grid electrode of the field-effect tube P1 through a switch S1, the middle nodes of a resistor R1 and a field-effect tube N1 are connected with the input end of the over-current protection module, and the middle nodes of a resistor R1 and a field-effect tube N1.
Preferably, the fet P1 is a PMOS transistor, and the fet N1 is an NMOS transistor.
For a brief description, the chip provided in the embodiment of the present invention may refer to the corresponding content in the foregoing circuit embodiment.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the scope of the embodiments of the present invention, and are intended to be covered by the claims and the specification.