CN210429264U - Miniature display device - Google Patents
Miniature display device Download PDFInfo
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- CN210429264U CN210429264U CN201921398757.5U CN201921398757U CN210429264U CN 210429264 U CN210429264 U CN 210429264U CN 201921398757 U CN201921398757 U CN 201921398757U CN 210429264 U CN210429264 U CN 210429264U
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Abstract
The utility model discloses a miniature display device, kind miniature display device, including a plurality of pixels and light emitting component, every the pixel includes drive transistor, voltage control transistor, first switch transistor and second switch transistor, the voltage control transistor is provided with the gate pole terminal, when keep to the bias voltage is applyed to the gate pole terminal, the voltage control transistor control drive transistor's drain voltage, first switch transistor transmission data signal gives the gate pole terminal, second switch transistor sets up drive transistor with between the light emitting component, second switch transistor control drive transistor's current flows. The utility model discloses can improve display device's resolution ratio, improve and improve user experience, can also reduce the size of pixel, help reduction in production cost.
Description
Technical Field
The utility model belongs to the technical field of display device, concretely relates to miniature display device.
Background
As the information-oriented society develops, the demand for display devices increases, and various types of display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices are widely used. Recently, interest in high resolution display devices using micro light emitting diodes (hereinafter, referred to as "micro display devices") has been increasing.
In order to fully embody VR, AR, and MR technologies, more excellent characteristics of display devices are required, and accordingly, development of micro led on Silicon or AMOLED on Silicon is increasing, and particularly, a demand for minimizing a pixel size is increasing to realize high-resolution image quality.
SUMMERY OF THE UTILITY MODEL
The utility model aims to provide a: the miniature display device is provided aiming at the defects of the prior art, the resolution ratio of the display device can be improved, the user experience is improved, the size of pixels can be reduced, and the reduction of the production cost is facilitated.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a micro display device includes a plurality of pixels each including a driving transistor, a voltage control transistor provided with a gate terminal, a first switching transistor controlling a drain voltage of the driving transistor when a bias voltage is kept applied to the gate terminal, the first switching transistor transmitting a data signal to the gate terminal, and a second switching transistor provided between the driving transistor and a light emitting element, the second switching transistor controlling a current flow of the driving transistor, and a light emitting element.
As an improvement of the micro display device of the present invention, the driving transistor is provided with a triode region.
As an improvement of the micro display device of the present invention, the gate terminal is connected to a bias line of the bias voltage.
As an improvement of the micro display device of the present invention, the voltage control transistor is further provided with a first terminal and a second terminal, the first terminal is connected to the second switch transistor, and the second terminal is connected to the drain terminal of the driving transistor.
As an improvement of the micro display device of the present invention, the voltage control transistor is disposed between the driving transistor and the second switching transistor.
As an improvement of the micro display device of the present invention, the micro display device further includes a bias voltage supply portion, the bias voltage supply portion generates the bias voltage and outputs the bias voltage to the gate terminal.
As an improvement of the micro display device, the micro display device further includes a control portion, a scan driving portion and a data driving portion, the control portion is respectively connected to the scan driving portion, the data driving portion and the bias voltage supply portion.
As an improvement of the micro display device of the present invention, the bias voltage supply unit includes an operational amplifier and a reference voltage generating unit connected in series.
The beneficial effects of the utility model reside in that, the utility model discloses a plurality of pixels and light-emitting component, every the pixel includes driving transistor, voltage control transistor, first switch transistor and second switch transistor, the voltage control transistor is provided with the gate terminal, when keep to the bias voltage is applyed to the gate terminal, voltage control transistor control driving transistor's drain voltage, first switch transistor transmits data signal and gives the gate terminal, second switch transistor sets up driving transistor with between the light-emitting component, second switch transistor control driving transistor's current flows. The utility model discloses can improve display device's resolution ratio, improve and improve user experience, can also reduce the size of pixel, help reduction in production cost.
Drawings
Fig. 1 is a schematic structural diagram of a display device according to the present invention;
fig. 2 is a circuit diagram of a pixel according to the present invention;
fig. 3 is a schematic diagram of the Voltage (VDS) -current (IDS) characteristics of the transistor gate voltage of the present invention;
fig. 4 is a schematic circuit diagram of the bias voltage supply unit according to the present invention;
wherein: 121-a control section; 122-scan drive section; 123-a data driving part; 124-bias voltage supply; 131-an operational amplifier; 133-standard voltage generation section.
Detailed Description
As used in the specification and in the claims, certain terms are used to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. "substantially" means within an acceptable error range, and a person skilled in the art can solve the technical problem within a certain error range to substantially achieve the technical effect.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", horizontal "and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, detachable connections, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
The present invention will be described in further detail with reference to the accompanying drawings, which are not intended to limit the present invention.
As shown in fig. 1 to 4, a micro display device includes a plurality of pixels each including a driving transistor, a voltage control transistor having a gate terminal, the voltage control transistor controlling a drain voltage of the driving transistor when a bias voltage is maintained to be applied to the gate terminal, a first switching transistor transmitting a data signal to the gate terminal, and a second switching transistor disposed between the driving transistor and a light emitting element, the second switching transistor controlling a current flow of the driving transistor, and the light emitting element.
Preferably, the driving transistor is provided with a triode region; the gate terminal is connected with a bias line of bias voltage; the voltage control transistor is also provided with a first terminal and a second terminal, the first terminal is connected with the second switch crystal, and the second terminal is connected with the drain terminal of the driving transistor; the voltage control transistor is arranged between the driving transistor and the second switching transistor; the micro display device further includes a bias voltage supply unit 124, the bias voltage supply unit 124 generating a bias voltage and outputting the bias voltage to the gate terminal; the micro display device further includes a control unit 121, a scan driving unit 122, and a data driving unit 123, wherein the control unit 121 is electrically connected to the scan driving unit 122, the data driving unit 123, and the bias voltage supplying unit 124, respectively; the bias voltage supply unit 124 includes an operational amplifier 131 and a standard voltage generation unit 133 connected in series.
The display device may include: the light emitting device comprises a light emitting element array and a driving circuit substrate. The light emitting element array may be combined with the driving circuit substrate. The display device may be a micro display device.
The light emitting device array may include a plurality of light emitting devices. The light emitting elements may be light emitting diodes, LEDs. The light emitting element may be a micro or nano unit size light emitting diode LED. A plurality of light emitting diodes may be grown on a semiconductor wafer to fabricate at least one light emitting device array. Therefore, the display device can be manufactured by combining the light emitting element array and the driving circuit substrate without transferring the light emitting diodes individually to the driving circuit substrate.
The pixel circuits each corresponding to the light emitting diode on the light emitting element array may be arranged on the driving circuit substrate. The light emitting diodes on the light emitting element array and the pixel circuits on the driving circuit substrate may constitute pixels in an electrically connected manner.
The utility model discloses a display device of an embodiment can include: a pixel section and a driving section.
The pixel part may be disposed in the image display region. The pixel part may have a predetermined form including: for example, a plurality of pixels PX arranged in various forms such as a matrix shape, a zigzag shape, and the like. The pixel PX emits one color, for example, one color among red, cyan, green, and white. The pixel PX may emit other colors in addition to red, cyan, green, and white.
The pixel PX may include a light emitting element. The light emitting element may be a sub light emitting element. For example, the light emitting elements may be light emitting diodes, LEDs. The light-emitting element may emit light of a single peak wavelength or may emit light of a plurality of peak wavelengths.
The pixel PX may further include a pixel circuit connected to the light emitting element. The pixel circuit may include: at least one thin film transistor and at least one capacitor, etc. The pixel circuit may be implemented in a semiconductor stacked structure on a substrate.
In the pixel portion, scan lines SL-SLn for applying scan signals to the pixels PX, and data lines DL-DLm for applying data signals to the pixels PX are arranged to be spaced apart. The scanning lines SL to SLn are each connected to the pixels PX arranged in the same row, and the data lines DL to DLm are each connected to the pixels PX arranged in the same column.
In the pixel section, an emission control line EL-ELn for applying an emission control signal to the pixel PX may be additionally arranged. The emission control lines EL to ELn are each connected to pixels PX arranged in the same row, which are arranged apart from the scan lines SL to SLn.
In the pixel portion, a bias line BL-BLn for applying a bias voltage to the pixel PX may be additionally disposed. The bias lines BL to BLn are each connected to pixels PX arranged in the same row, which are arranged apart from the scan lines SL to SLn.
The drive unit includes a non-display region around the pixel unit and can drive and control the pixel unit. The driving part may include: a control section 121, a scan driving section 122, a data driving section 123, and a bias voltage supply section 124.
Under the control of the control section 121, the scan driving section 122 may sequentially apply scan signals to the scan lines SL to SLn, and the data driving section 123 may apply data signals to the respective pixels PX. The pixels PX at this time respond to the scan signals received through the scan lines SL-SLn and emit light with a luminance corresponding to the voltage level or the current level of the data signals received through the data lines DL-DLm.
And a bias voltage supply unit 124 for supplying a bias voltage for controlling the drain voltage of the driving transistor of each pixel PX to turn on the bias transistor to the bias line BL-BLn.
The control unit 121, the scan driving unit 122, the data driving unit 123, and the bias voltage supplying unit 124 may be directly mounted on a substrate on which the pixel unit is formed, may be attached to a flexible printed circuit file or may be attached to a substrate in a TCPtape carrier package format, or may be directly formed in the substrate after each is formed as an independent ic chip or a single ic chip.
The pixel PX of the nth row and the mth column will be exemplified. The pixel PX is one of a plurality of pixels included in the nth row, and is connected to the scan line SLn corresponding to the nth row and the data line DLm corresponding to the mth column.
The pixels PX may be connected to scan lines SLn transmitting scan signals, data lines DLm transmitting data signals crossing the scan lines SLn, and power lines transmitting a first power voltage VDD.
The pixel PX may include: a light emitting diode ED and a pixel circuit connected to the light emitting diode ED. The pixel circuit may include: first to third transistors T1 to T3, a bias transistor BT, and a capacitor C. The respective first terminals of the first to third transistors T1 to T3 and the bias transistor BT may be drain terminals, and the second terminals may be source terminals.
The first transistor T1 may include: a gate terminal connected to a first terminal of the capacitor C, a first terminal connected to the light emitting diode ED through the third transistor T, and a second terminal connected to the second power supply voltage VSS. The second power supply voltage VSS may be a ground voltage GND. The first transistor T1 functions as a driving transistor for supplying current to the light emitting diode ED in response to a data signal received by the switching operation of the second transistor T2. The first transistor T1 can operate in a low voltage region. For example, the first transistor T1 may operate in the triode region.
The second transistor T2 may include: a gate terminal connected to the scan line SLn, a first terminal connected to the data line DLm, and a second terminal connected to the gate terminal of the first transistor T1. The second transistor T2 will function as a switching transistor which transmits a data signal received through the data line DLm to the gate electrode of the first transistor T1 after receiving a scan signal through the scan line SLn and being successfully turned on. The second transistor T2 can operate in a low voltage region together with the first transistor T1. The second transistor T2 may operate in the triode region. At this time, the data signal may be converted to a voltage range corresponding to the low voltage operation of the first and second transistors T1 and T2.
The third transistor T may include: a gate terminal to which the emission control line ELn is connected, a first terminal to which the second electrode of the light emitting diode ED is connected, and a second terminal to which the first terminal of the bias transistor BT is connected. The third transistor T will function as a switching transistor which flows a driving current of the first transistor T1 to the light emitting diode ED after being turned on according to the light emission control signal received through the light emission control line ELn. The light emission control line ELn is connected to the scan driving section 122, and receives a light emission control signal from the scan driving section 122. In another embodiment, the light emitting control line ELn may be connected to the scan driving part 122 and the independent light emitting control driving part, not shown, and then receive the light emitting control signal. The third transistor T may be omitted.
The bias transistor BT may include: a gate terminal connected to the bias line BLn, a first terminal connected to the second terminal of the third transistor T, and a second terminal connected to the first terminal of the first transistor T1. The bias transistor BT, which may be a voltage controlled transistor controlling the drain voltage of the first transistor T1, is kept in an on state by a bias voltage applied to the gate terminal. The drain voltage of the first transistor T1 is controlled by the bias transistor BT, and the first transistor T1 and the second transistor T2 will function as low voltage transistors. In one embodiment, the bias transistor BT controls the drain voltage of the first transistor T1 to ensure the operation of the first transistor T1 in the triode region.
The bias transistor BT may be turned on with a bias voltage applied through the bias line BLn. The bias voltage may be a DC voltage DC of a certain level for keeping the bias transistor BT in an on state at all times. Depending on the on-state of the bias transistor BT, the node voltage Vx between the first transistor T1 and the bias transistor BT, i.e., the first transistor T1 drain voltage, can be controlled. The channel resistance of the bias transistor BT is variable according to the bias voltage. That is, the bias transistor BT can operate with a variable linear resistance.
The node voltage Vx, i.e., the drain voltage of the first transistor T1, is determined by the channel resistance of the bias transistor BT. Therefore, the bias voltage will be controlled such that the drain voltage of the first transistor T1 controls the first transistor T1 to ensure the voltage condition required for operation in the triode region.
The capacitor C may include: a first terminal connected to the gate terminal of the first transistor T1, and a second terminal connected to the second power supply voltage VSS.
The first electrode of the light emitting diode ED may obtain a first supply voltage VDD. A second electrode of the light emitting diode ED may be connected to a first electrode of the third transistor T. The light emitting diode ED displays an image by emitting light with a luminance corresponding to the data signal.
The transistor has the characteristics of voltage VDS-current IDS in the following formula in a triode region and the characteristics of voltage VDS-current IDS in the following formula in a saturation region.
IDS＝K(VGS-VT)VDS-VDS/...(1)
IDS＝K/VGS-VT...(2)
Here, IDS denotes a drain-source current of the transistor, K denotes a Process transconductance parameter, and K may be the same parameter as Mobility of a channel carrier Electron, capacitance Cox of a gate region, and a channel size. The lane size may be defined in a Width ratio Width/Length to Length. VGS is the gate-source Voltage of the transistor, VT is the Threshold Voltage, and VDS is the drain-source Voltage.
The operating condition of the first transistor T1 as a driving transistor operating in the triode region is VGS-VT>VDS. Wherein VDSSince the node voltage Vx is controlled by the bias voltage depending on the node voltage Vx, the normal operation of the first transistor T1 in the triode region can be ensured by controlling the bias voltage. The first transistor T1 has the same linear characteristic as a resistor when operating in the triode region. Thus, the first transistor T1 may output an input voltage, i.e., an output current, i.e., IDS, which is linearized by VGS.
Since the first transistor T1 operates in the triode region, the drain-source current variation due to threshold voltage variation can be eliminated, and a wide input voltage range can be used due to the low transconductance Gm.
When the drain terminal of the first transistor T1 is connected to the second electrode cathode of the light-emitting element ED, a high-voltage transistor having high withstand voltage characteristics is required, and thus the threshold voltage mismatch characteristics may be adversely affected.
The embodiment of the utility model discloses a through controlling first transistor T1 drain voltage, will act the regional restriction in triode region to restriction drain-source voltage action voltage range. Therefore, a transistor having a low breakdown voltage can be used as a driving transistor.
The bias voltage supply part 124 may include: an Operational Amplifier 131, an Operational Amplifier, and a reference voltage generating unit 133.
The operational amplifier 131 has a first input terminal + connected to the standard voltage generator 133 of the supply source of the standard voltage Vref, and a second input terminal connected to the output terminal. The output terminal of the operational amplifier 131 is connected to the bias line BLn.
In one embodiment, the bias voltage supply unit 124 is formed by a single operational amplifier 131, and the output terminal of the operational amplifier 131 may be connected to a plurality of bias lines BL-BLn. In another embodiment, the bias voltage supply unit 124 is composed of a plurality of first to nth operational amplifiers 131, and each output terminal of the plurality of first to nth operational amplifiers 131 may be connected to a corresponding bias line of the plurality of bias lines BL to BLn.
The bias voltage supply unit 124 may generate and apply a bias voltage VBIAS capable of determining a channel resistance of the bias transistor BT to the bias line BLn in order to control a drain voltage of the first transistor T1 so as to ensure that the first transistor T1 operates in a low voltage region. The bias voltage supply unit 124 generates and applies a bias voltage VBIAS capable of determining the channel resistance of the bias transistor BT to the bias line BLn in order to ensure that the first transistor T1 satisfies the operating condition of VGSVT > VDS.
When the operation region of the driving transistor is used in a saturation region, a long channel driving transistor may be used or a large resistor may be added in order to secure a sufficient input voltage region due to a high transconductance Gm value. In addition, in order to reduce the influence of threshold voltage mismatch, a large-sized driving transistor is sometimes used. It is difficult to embody a high-resolution micro display device at this time.
The embodiment of the utility model discloses a can control drive transistor's drain voltage, limit drive transistor's action region in the triode region to optimize transconductance Gm value, eliminate threshold voltage mismatch's influence with short-channel drive transistor, in order to ensure wide input voltage value range.
In addition, the embodiment of the present invention applies an external bias, and can limit the operating voltages of the driving transistor and the driving portion to a low voltage range, and can realize a high-resolution pixel circuit without using a high-voltage transistor in the micro display device.
The utility model also discloses a miniature display device's control method, include:
generating a bias voltage;
applying a bias voltage to a gate terminal of the voltage control transistor and maintaining an on state;
the drain voltage of the driving transistor is controlled and then the current of the driving transistor is controlled to flow after the driving transistor and the light emitting element are connected.
Variations and modifications to the above-described embodiments may become apparent to those skilled in the art from the disclosure and teachings of the above description. Therefore, the present invention is not limited to the above-mentioned embodiments, and any obvious modifications, replacements or variations made by those skilled in the art on the basis of the present invention belong to the protection scope of the present invention. Furthermore, although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (8)
1. A micro display device, comprising: the pixel structure includes a plurality of pixels and a light emitting element, each of the pixels includes a driving transistor, a voltage control transistor, a first switching transistor, and a second switching transistor, the voltage control transistor having a gate terminal, the voltage control transistor controlling a drain voltage of the driving transistor when a bias voltage is maintained to be applied to the gate terminal, the first switching transistor transmitting a data signal to the gate terminal, the second switching transistor being disposed between the driving transistor and the light emitting element, the second switching transistor controlling a current flow of the driving transistor.
2. A microdisplay device as in claim 1 wherein: the driving transistor is provided with a triode region.
3. A microdisplay device as in claim 1 wherein: the gate terminal is connected to a bias line for the bias voltage.
4. A microdisplay device as in claim 3 wherein: the voltage control transistor is further provided with a first terminal connected to the second switching transistor and a second terminal connected to the drain terminal of the driving transistor.
5. A microdisplay device as in claim 1 wherein: the voltage control transistor is disposed between the driving transistor and the second switching transistor.
6. A microdisplay device as in claim 1 wherein: the micro display device further includes a bias voltage supply unit (124), and the bias voltage supply unit (124) generates the bias voltage and outputs the bias voltage to the gate terminal.
7. A microdisplay device as in claim 6 wherein: the micro display device further comprises a control part (121), a scanning driving part (122) and a data driving part (123), wherein the control part (121) is electrically connected with the scanning driving part (122), the data driving part (123) and the bias voltage supply part (124) respectively.
8. A microdisplay device as in claim 6 wherein: the bias voltage supply unit (124) includes an operational amplifier (131) and a standard voltage generation unit (133) connected in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921398757.5U CN210429264U (en) | 2019-08-27 | 2019-08-27 | Miniature display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921398757.5U CN210429264U (en) | 2019-08-27 | 2019-08-27 | Miniature display device |
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| CN210429264U true CN210429264U (en) | 2020-04-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974086A (en) * | 2022-05-19 | 2022-08-30 | 京东方科技集团股份有限公司 | Pixel circuit, display panel and display device |
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2019
- 2019-08-27 CN CN201921398757.5U patent/CN210429264U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114974086A (en) * | 2022-05-19 | 2022-08-30 | 京东方科技集团股份有限公司 | Pixel circuit, display panel and display device |
| CN114974086B (en) * | 2022-05-19 | 2023-09-26 | 京东方科技集团股份有限公司 | Pixel circuit, display panel and display device |
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Effective date of registration: 20210317 Address after: 210000 B-5, 69 Shuangfeng Road, Pukou Economic Development Zone, Pukou District, Nanjing City, Jiangsu Province Patentee after: Yuchuang semiconductor (Nanjing) Co.,Ltd. Address before: 518000 Room 201, building A, 1 front Bay Road, Shenzhen Qianhai cooperation zone, Shenzhen, Guangdong Patentee before: Yuchuang semiconductor (Shenzhen) Co.,Ltd. |
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Effective date of registration: 20210513 Address after: 518000 Room 201, building A, No. 1, Qian Wan Road, Qianhai Shenzhen Hong Kong cooperation zone, Shenzhen, Guangdong (Shenzhen Qianhai business secretary Co., Ltd.) Patentee after: Yuchuang semiconductor (Shenzhen) Co.,Ltd. Address before: 210000 B-5, 69 Shuangfeng Road, Pukou Economic Development Zone, Pukou District, Nanjing City, Jiangsu Province Patentee before: Yuchuang semiconductor (Nanjing) Co.,Ltd. |